1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2009
4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5 * Copyright (C) 2011
6 * HALE electronic GmbH, <helmut.raiger@hale.at>
7 */
8 #include <common.h>
9 #include <malloc.h>
10 #include <video_fb.h>
11
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
14 #include <linux/errno.h>
15 #include <asm/io.h>
16
17 #include "videomodes.h"
18
19 /* this might need panel specific set-up as-well */
20 #define IF_CONF 0
21
22 /* -------------- controller specific stuff -------------- */
23
24 /* IPU DMA Controller channel definitions. */
25 enum ipu_channel {
26 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
27 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
28 IDMAC_ADC_0 = 1,
29 IDMAC_IC_2 = 2,
30 IDMAC_ADC_1 = 2,
31 IDMAC_IC_3 = 3,
32 IDMAC_IC_4 = 4,
33 IDMAC_IC_5 = 5,
34 IDMAC_IC_6 = 6,
35 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
36 IDMAC_IC_8 = 8,
37 IDMAC_IC_9 = 9,
38 IDMAC_IC_10 = 10,
39 IDMAC_IC_11 = 11,
40 IDMAC_IC_12 = 12,
41 IDMAC_IC_13 = 13,
42 IDMAC_SDC_0 = 14, /* Background synchronous display data */
43 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
44 IDMAC_SDC_2 = 16,
45 IDMAC_SDC_3 = 17,
46 IDMAC_ADC_2 = 18,
47 IDMAC_ADC_3 = 19,
48 IDMAC_ADC_4 = 20,
49 IDMAC_ADC_5 = 21,
50 IDMAC_ADC_6 = 22,
51 IDMAC_ADC_7 = 23,
52 IDMAC_PF_0 = 24,
53 IDMAC_PF_1 = 25,
54 IDMAC_PF_2 = 26,
55 IDMAC_PF_3 = 27,
56 IDMAC_PF_4 = 28,
57 IDMAC_PF_5 = 29,
58 IDMAC_PF_6 = 30,
59 IDMAC_PF_7 = 31,
60 };
61
62 /* More formats can be copied from the Linux driver if needed */
63 enum pixel_fmt {
64 /* 2 bytes */
65 IPU_PIX_FMT_RGB565,
66 IPU_PIX_FMT_RGB666,
67 IPU_PIX_FMT_BGR666,
68 /* 3 bytes */
69 IPU_PIX_FMT_RGB24,
70 };
71
72 struct pixel_fmt_cfg {
73 u32 b0;
74 u32 b1;
75 u32 b2;
76 u32 acc;
77 };
78
79 static struct pixel_fmt_cfg fmt_cfg[] = {
80 [IPU_PIX_FMT_RGB24] = {
81 0x1600AAAA, 0x00E05555, 0x00070000, 3,
82 },
83 [IPU_PIX_FMT_RGB666] = {
84 0x0005000F, 0x000B000F, 0x0011000F, 1,
85 },
86 [IPU_PIX_FMT_BGR666] = {
87 0x0011000F, 0x000B000F, 0x0005000F, 1,
88 },
89 [IPU_PIX_FMT_RGB565] = {
90 0x0004003F, 0x000A000F, 0x000F003F, 1,
91 }
92 };
93
94 enum ipu_panel {
95 IPU_PANEL_SHARP_TFT,
96 IPU_PANEL_TFT,
97 };
98
99 /* IPU Common registers */
100 /* IPU_CONF and its bits already defined in imx-regs.h */
101 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
102 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
103 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
104 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
105 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
106 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
107 #define IPU_TASKS_STAT (0x1C + IPU_BASE)
108 #define IPU_IMA_ADDR (0x20 + IPU_BASE)
109 #define IPU_IMA_DATA (0x24 + IPU_BASE)
110 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
111 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
112 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
113 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
114 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
115 #define IPU_INT_STAT_1 (0x3C + IPU_BASE)
116 #define IPU_INT_STAT_2 (0x40 + IPU_BASE)
117 #define IPU_INT_STAT_3 (0x44 + IPU_BASE)
118 #define IPU_INT_STAT_4 (0x48 + IPU_BASE)
119 #define IPU_INT_STAT_5 (0x4C + IPU_BASE)
120 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
121 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
122 #define IPU_BRK_STAT (0x58 + IPU_BASE)
123 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
124
125 /* Image Converter Registers */
126 #define IC_CONF (0x88 + IPU_BASE)
127 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
128 #define IC_PRP_VF_RSC (0x90 + IPU_BASE)
129 #define IC_PP_RSC (0x94 + IPU_BASE)
130 #define IC_CMBP_1 (0x98 + IPU_BASE)
131 #define IC_CMBP_2 (0x9C + IPU_BASE)
132 #define PF_CONF (0xA0 + IPU_BASE)
133 #define IDMAC_CONF (0xA4 + IPU_BASE)
134 #define IDMAC_CHA_EN (0xA8 + IPU_BASE)
135 #define IDMAC_CHA_PRI (0xAC + IPU_BASE)
136 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
137
138 /* Image Converter Register bits */
139 #define IC_CONF_PRPENC_EN 0x00000001
140 #define IC_CONF_PRPENC_CSC1 0x00000002
141 #define IC_CONF_PRPENC_ROT_EN 0x00000004
142 #define IC_CONF_PRPVF_EN 0x00000100
143 #define IC_CONF_PRPVF_CSC1 0x00000200
144 #define IC_CONF_PRPVF_CSC2 0x00000400
145 #define IC_CONF_PRPVF_CMB 0x00000800
146 #define IC_CONF_PRPVF_ROT_EN 0x00001000
147 #define IC_CONF_PP_EN 0x00010000
148 #define IC_CONF_PP_CSC1 0x00020000
149 #define IC_CONF_PP_CSC2 0x00040000
150 #define IC_CONF_PP_CMB 0x00080000
151 #define IC_CONF_PP_ROT_EN 0x00100000
152 #define IC_CONF_IC_GLB_LOC_A 0x10000000
153 #define IC_CONF_KEY_COLOR_EN 0x20000000
154 #define IC_CONF_RWS_EN 0x40000000
155 #define IC_CONF_CSI_MEM_WR_EN 0x80000000
156
157 /* SDC Registers */
158 #define SDC_COM_CONF (0xB4 + IPU_BASE)
159 #define SDC_GW_CTRL (0xB8 + IPU_BASE)
160 #define SDC_FG_POS (0xBC + IPU_BASE)
161 #define SDC_BG_POS (0xC0 + IPU_BASE)
162 #define SDC_CUR_POS (0xC4 + IPU_BASE)
163 #define SDC_PWM_CTRL (0xC8 + IPU_BASE)
164 #define SDC_CUR_MAP (0xCC + IPU_BASE)
165 #define SDC_HOR_CONF (0xD0 + IPU_BASE)
166 #define SDC_VER_CONF (0xD4 + IPU_BASE)
167 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
168 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
169
170 /* Register bits */
171 #define SDC_COM_TFT_COLOR 0x00000001UL
172 #define SDC_COM_FG_EN 0x00000010UL
173 #define SDC_COM_GWSEL 0x00000020UL
174 #define SDC_COM_GLB_A 0x00000040UL
175 #define SDC_COM_KEY_COLOR_G 0x00000080UL
176 #define SDC_COM_BG_EN 0x00000200UL
177 #define SDC_COM_SHARP 0x00001000UL
178
179 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
180
181 /* Display Interface registers */
182 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
183 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
184 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
185 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
186 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
187 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
188 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
189 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
190 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
191 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
192 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
193 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
194 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
195 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
196 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
197 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
198 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
199 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
200 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
201 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
202 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
203 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
204 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
205 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
206 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
207 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
208 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
209 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
210 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
211 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
212 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
213 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
214 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
215 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
216 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
217 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
218 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
219 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
220 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
221
222 /* DI_DISP_SIG_POL bits */
223 #define DI_D3_VSYNC_POL (1 << 28)
224 #define DI_D3_HSYNC_POL (1 << 27)
225 #define DI_D3_DRDY_SHARP_POL (1 << 26)
226 #define DI_D3_CLK_POL (1 << 25)
227 #define DI_D3_DATA_POL (1 << 24)
228
229 /* DI_DISP_IF_CONF bits */
230 #define DI_D3_CLK_IDLE (1 << 26)
231 #define DI_D3_CLK_SEL (1 << 25)
232 #define DI_D3_DATAMSK (1 << 24)
233
234 #define IOMUX_PADNUM_MASK 0x1ff
235 #define IOMUX_GPIONUM_SHIFT 9
236 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
237
238 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
239
240 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
241
242 struct chan_param_mem_planar {
243 /* Word 0 */
244 u32 xv:10;
245 u32 yv:10;
246 u32 xb:12;
247
248 u32 yb:12;
249 u32 res1:2;
250 u32 nsb:1;
251 u32 lnpb:6;
252 u32 ubo_l:11;
253
254 u32 ubo_h:15;
255 u32 vbo_l:17;
256
257 u32 vbo_h:9;
258 u32 res2:3;
259 u32 fw:12;
260 u32 fh_l:8;
261
262 u32 fh_h:4;
263 u32 res3:28;
264
265 /* Word 1 */
266 u32 eba0;
267
268 u32 eba1;
269
270 u32 bpp:3;
271 u32 sl:14;
272 u32 pfs:3;
273 u32 bam:3;
274 u32 res4:2;
275 u32 npb:6;
276 u32 res5:1;
277
278 u32 sat:2;
279 u32 res6:30;
280 } __attribute__ ((packed));
281
282 struct chan_param_mem_interleaved {
283 /* Word 0 */
284 u32 xv:10;
285 u32 yv:10;
286 u32 xb:12;
287
288 u32 yb:12;
289 u32 sce:1;
290 u32 res1:1;
291 u32 nsb:1;
292 u32 lnpb:6;
293 u32 sx:10;
294 u32 sy_l:1;
295
296 u32 sy_h:9;
297 u32 ns:10;
298 u32 sm:10;
299 u32 sdx_l:3;
300
301 u32 sdx_h:2;
302 u32 sdy:5;
303 u32 sdrx:1;
304 u32 sdry:1;
305 u32 sdr1:1;
306 u32 res2:2;
307 u32 fw:12;
308 u32 fh_l:8;
309
310 u32 fh_h:4;
311 u32 res3:28;
312
313 /* Word 1 */
314 u32 eba0;
315
316 u32 eba1;
317
318 u32 bpp:3;
319 u32 sl:14;
320 u32 pfs:3;
321 u32 bam:3;
322 u32 res4:2;
323 u32 npb:6;
324 u32 res5:1;
325
326 u32 sat:2;
327 u32 scc:1;
328 u32 ofs0:5;
329 u32 ofs1:5;
330 u32 ofs2:5;
331 u32 ofs3:5;
332 u32 wid0:3;
333 u32 wid1:3;
334 u32 wid2:3;
335
336 u32 wid3:3;
337 u32 dec_sel:1;
338 u32 res6:28;
339 } __attribute__ ((packed));
340
341 union chan_param_mem {
342 struct chan_param_mem_planar pp;
343 struct chan_param_mem_interleaved ip;
344 };
345
346 /* graphics setup */
347 static GraphicDevice panel;
348 static struct ctfb_res_modes *mode;
349 static struct ctfb_res_modes var_mode;
350
351 /*
352 * sdc_init_panel() - initialize a synchronous LCD panel.
353 * @width: width of panel in pixels.
354 * @height: height of panel in pixels.
355 * @di_setup: pixel format of the frame buffer
356 * @di_panel: either SHARP or normal TFT
357 * @return: 0 on success or negative error code on failure.
358 */
sdc_init_panel(u16 width,u16 height,enum pixel_fmt di_setup,enum ipu_panel di_panel)359 static int sdc_init_panel(u16 width, u16 height,
360 enum pixel_fmt di_setup, enum ipu_panel di_panel)
361 {
362 u32 reg, div;
363 uint32_t old_conf;
364 int clock;
365
366 debug("%s(width=%d, height=%d)\n", __func__, width, height);
367
368 /* Init clocking, the IPU receives its clock from the hsp divder */
369 clock = mxc_get_clock(MXC_IPU_CLK);
370 if (clock < 0)
371 return -EACCES;
372
373 /* Init panel size and blanking periods */
374 reg = width + mode->left_margin + mode->right_margin - 1;
375 if (reg > 1023) {
376 printf("mx3fb: Display width too large, coerced to 1023!");
377 reg = 1023;
378 }
379 reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
380 writel(reg, SDC_HOR_CONF);
381
382 reg = height + mode->upper_margin + mode->lower_margin - 1;
383 if (reg > 1023) {
384 printf("mx3fb: Display height too large, coerced to 1023!");
385 reg = 1023;
386 }
387 reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
388 writel(reg, SDC_VER_CONF);
389
390 switch (di_panel) {
391 case IPU_PANEL_SHARP_TFT:
392 writel(0x00FD0102L, SDC_SHARP_CONF_1);
393 writel(0x00F500F4L, SDC_SHARP_CONF_2);
394 writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
395 /* TODO: probably IF_CONF must be adapted (see below)! */
396 break;
397 case IPU_PANEL_TFT:
398 writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
399 break;
400 default:
401 return -EINVAL;
402 }
403
404 /*
405 * Calculate divider: The fractional part is 4 bits so simply
406 * multiple by 2^4 to get it.
407 *
408 * Opposed to the kernel driver mode->pixclock is the time of one
409 * pixel in pico seconds, so:
410 * pixel_clk = 1e12 / mode->pixclock
411 * div = ipu_clk * 16 / pixel_clk
412 * leads to:
413 * div = ipu_clk * 16 / (1e12 / mode->pixclock)
414 * or:
415 * div = ipu_clk * 16 * mode->pixclock / 1e12
416 *
417 * To avoid integer overflows this is split into 2 shifts and
418 * one divide with sufficient accuracy:
419 * 16*1024*128*476837 = 0.9999996682e12
420 */
421 div = ((clock/1024) * (mode->pixclock/128)) / 476837;
422 debug("hsp_clk is %d, div=%d\n", clock, div);
423 /* coerce to not less than 4.0, not more than 255.9375 */
424 if (div < 0x40)
425 div = 0x40;
426 else if (div > 0xFFF)
427 div = 0xFFF;
428 /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
429 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
430 * based on timing debug DISP3_IF_CLK_UP_WR is 0
431 */
432 writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
433
434 /* DI settings for display 3: clock idle (bit 26) during vsync */
435 old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
436 writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
437
438 /* only set display 3 polarity bits */
439 old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
440 writel(old_conf | mode->sync, DI_DISP_SIG_POL);
441
442 writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
443 writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
444 writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
445 writel(readl(DI_DISP_ACC_CC) |
446 ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
447
448 debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
449 debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
450 debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
451 debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
452 debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
453
454 return 0;
455 }
456
ipu_ch_param_set_size(union chan_param_mem * params,uint pixelfmt,uint16_t width,uint16_t height,uint16_t stride)457 static void ipu_ch_param_set_size(union chan_param_mem *params,
458 uint pixelfmt, uint16_t width,
459 uint16_t height, uint16_t stride)
460 {
461 debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
462 __func__, pixelfmt, width, height, stride);
463
464 params->pp.fw = width - 1;
465 params->pp.fh_l = height - 1;
466 params->pp.fh_h = (height - 1) >> 8;
467 params->pp.sl = stride - 1;
468
469 /* See above, for further formats see the Linux driver */
470 switch (pixelfmt) {
471 case GDF_16BIT_565RGB:
472 params->ip.bpp = 2;
473 params->ip.pfs = 4;
474 params->ip.npb = 7;
475 params->ip.sat = 2; /* SAT = 32-bit access */
476 params->ip.ofs0 = 0; /* Red bit offset */
477 params->ip.ofs1 = 5; /* Green bit offset */
478 params->ip.ofs2 = 11; /* Blue bit offset */
479 params->ip.ofs3 = 16; /* Alpha bit offset */
480 params->ip.wid0 = 4; /* Red bit width - 1 */
481 params->ip.wid1 = 5; /* Green bit width - 1 */
482 params->ip.wid2 = 4; /* Blue bit width - 1 */
483 break;
484 case GDF_32BIT_X888RGB:
485 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
486 params->ip.pfs = 4;
487 params->ip.npb = 7;
488 params->ip.sat = 2; /* SAT = 32-bit access */
489 params->ip.ofs0 = 16; /* Red bit offset */
490 params->ip.ofs1 = 8; /* Green bit offset */
491 params->ip.ofs2 = 0; /* Blue bit offset */
492 params->ip.ofs3 = 24; /* Alpha bit offset */
493 params->ip.wid0 = 7; /* Red bit width - 1 */
494 params->ip.wid1 = 7; /* Green bit width - 1 */
495 params->ip.wid2 = 7; /* Blue bit width - 1 */
496 break;
497 default:
498 printf("mx3fb: Pixel format not supported!\n");
499 break;
500 }
501
502 params->pp.nsb = 1;
503 }
504
ipu_ch_param_set_buffer(union chan_param_mem * params,void * buf0,void * buf1)505 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
506 void *buf0, void *buf1)
507 {
508 params->pp.eba0 = (u32)buf0;
509 params->pp.eba1 = (u32)buf1;
510 }
511
ipu_write_param_mem(uint32_t addr,uint32_t * data,uint32_t num_words)512 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
513 uint32_t num_words)
514 {
515 for (; num_words > 0; num_words--) {
516 writel(addr, IPU_IMA_ADDR);
517 writel(*data++, IPU_IMA_DATA);
518 addr++;
519 if ((addr & 0x7) == 5) {
520 addr &= ~0x7; /* set to word 0 */
521 addr += 8; /* increment to next row */
522 }
523 }
524 }
525
dma_param_addr(enum ipu_channel channel)526 static uint32_t dma_param_addr(enum ipu_channel channel)
527 {
528 /* Channel Parameter Memory */
529 return 0x10000 | (channel << 4);
530 }
531
ipu_init_channel_buffer(enum ipu_channel channel,void * fbmem)532 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
533 {
534 union chan_param_mem params = {};
535 uint32_t reg;
536 uint32_t stride_bytes;
537
538 stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
539
540 debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
541
542 /* Build parameter memory data for DMA channel */
543 ipu_ch_param_set_size(¶ms, panel.gdfIndex,
544 panel.plnSizeX, panel.plnSizeY, stride_bytes);
545 ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
546 params.pp.bam = 0;
547 /* Some channels (rotation) have restriction on burst length */
548
549 switch (channel) {
550 case IDMAC_SDC_0:
551 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
552 params.pp.npb = 16 - 1;
553 break;
554 default:
555 break;
556 }
557
558 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
559
560 /* Disable double-buffering */
561 reg = readl(IPU_CHA_DB_MODE_SEL);
562 reg &= ~(1UL << channel);
563 writel(reg, IPU_CHA_DB_MODE_SEL);
564 }
565
ipu_channel_set_priority(enum ipu_channel channel,int prio)566 static void ipu_channel_set_priority(enum ipu_channel channel,
567 int prio)
568 {
569 u32 reg = readl(IDMAC_CHA_PRI);
570
571 if (prio)
572 reg |= 1UL << channel;
573 else
574 reg &= ~(1UL << channel);
575
576 writel(reg, IDMAC_CHA_PRI);
577 }
578
579 /*
580 * ipu_enable_channel() - enable an IPU channel.
581 * @channel: channel ID.
582 * @return: 0 on success or negative error code on failure.
583 */
ipu_enable_channel(enum ipu_channel channel)584 static int ipu_enable_channel(enum ipu_channel channel)
585 {
586 uint32_t reg;
587
588 /* Reset to buffer 0 */
589 writel(1UL << channel, IPU_CHA_CUR_BUF);
590
591 switch (channel) {
592 case IDMAC_SDC_0:
593 ipu_channel_set_priority(channel, 1);
594 break;
595 default:
596 break;
597 }
598
599 reg = readl(IDMAC_CHA_EN);
600 writel(reg | (1UL << channel), IDMAC_CHA_EN);
601
602 return 0;
603 }
604
ipu_update_channel_buffer(enum ipu_channel channel,void * buf)605 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
606 {
607 uint32_t reg;
608
609 reg = readl(IPU_CHA_BUF0_RDY);
610 if (reg & (1UL << channel))
611 return -EACCES;
612
613 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
614 writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
615 writel((u32)buf, IPU_IMA_DATA);
616
617 return 0;
618 }
619
idmac_tx_submit(enum ipu_channel channel,void * buf)620 static int idmac_tx_submit(enum ipu_channel channel, void *buf)
621 {
622 int ret;
623
624 ipu_init_channel_buffer(channel, buf);
625
626
627 /* ipu_idmac.c::ipu_submit_channel_buffers() */
628 ret = ipu_update_channel_buffer(channel, buf);
629 if (ret < 0)
630 return ret;
631
632 /* ipu_idmac.c::ipu_select_buffer() */
633 /* Mark buffer 0 as ready. */
634 writel(1UL << channel, IPU_CHA_BUF0_RDY);
635
636
637 ret = ipu_enable_channel(channel);
638 return ret;
639 }
640
sdc_enable_channel(void * fbmem)641 static void sdc_enable_channel(void *fbmem)
642 {
643 int ret;
644 u32 reg;
645
646 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
647
648 /* mx3fb.c::sdc_fb_init() */
649 if (ret >= 0) {
650 reg = readl(SDC_COM_CONF);
651 writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
652 }
653
654 /*
655 * Attention! Without this msleep the channel keeps generating
656 * interrupts. Next sdc_set_brightness() is going to be called
657 * from mx3fb_blank().
658 */
659 udelay(2000);
660 }
661
662 /*
663 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
664 * @return: 0 on success or negative error code on failure.
665 * TODO: currently only 666 and TFT as DI setup supported
666 */
mx3fb_set_par(void)667 static int mx3fb_set_par(void)
668 {
669 int ret;
670
671 ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
672 IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
673 if (ret < 0)
674 return ret;
675
676 writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
677
678 return 0;
679 }
680
ll_disp3_enable(void * base)681 static void ll_disp3_enable(void *base)
682 {
683 u32 reg;
684
685 debug("%s(base=0x%x)\n", __func__, (u32) base);
686 /* pcm037.c::mxc_board_init() */
687
688 /* Display Interface #3 */
689 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
690 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
691 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
692 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
693 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
694 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
695 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
696 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
697 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
698 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
699 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
700 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
701 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
702 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
703 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
704 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
705 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
706 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
707 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
708 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
709 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
710 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
711 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
712 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
713 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
714 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
715
716
717 /* ipu_idmac.c::ipu_probe() */
718
719 /* Start the clock */
720 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
721
722
723 /* ipu_idmac.c::ipu_idmac_init() */
724
725 /* Service request counter to maximum - shouldn't be needed */
726 writel(0x00000070, IDMAC_CONF);
727
728
729 /* ipu_idmac.c::ipu_init_channel() */
730
731 /* Enable IPU sub modules */
732 reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
733 writel(reg, IPU_CONF);
734
735
736 /* mx3fb.c::init_fb_chan() */
737
738 /* set Display Interface clock period */
739 writel(0x00100010L, DI_HSP_CLK_PER);
740 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
741
742
743 /* mx3fb.c::sdc_set_brightness() */
744
745 /* This might be board-specific */
746 writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
747
748
749 /* mx3fb.c::sdc_set_global_alpha() */
750
751 /* Use global - not per-pixel - Alpha-blending */
752 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
753 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
754
755 reg = readl(SDC_COM_CONF);
756 writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
757
758
759 /* mx3fb.c::sdc_set_color_key() */
760
761 /* Disable colour-keying for background */
762 reg = readl(SDC_COM_CONF) &
763 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
764 writel(reg, SDC_COM_CONF);
765
766
767 mx3fb_set_par();
768
769 sdc_enable_channel(base);
770
771 /*
772 * Linux driver calls sdc_set_brightness() here again,
773 * once is enough for us
774 */
775 debug("%s() done\n", __func__);
776 }
777
778 /* ------------------------ public part ------------------- */
calc_fbsize(void)779 ulong calc_fbsize(void)
780 {
781 return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
782 }
783
784 /*
785 * The current implementation is only tested for GDF_16BIT_565RGB!
786 * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
787 * because the lcd code seemed loaded with color table stuff, that
788 * does not relate to most modern TFTs. cfb_console.c looks more
789 * straight forward.
790 * This is the environment setting for the original setup
791 * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
792 * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
793 * "videomode=unknown"
794 *
795 * Settings for VBEST VGG322403 display:
796 * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
797 * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
798 *
799 * Settings for COM57H5M10XRC display:
800 * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
801 * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
802 */
video_hw_init(void)803 void *video_hw_init(void)
804 {
805 char *penv;
806 u32 memsize;
807 unsigned long t1, hsynch, vsynch;
808 int bits_per_pixel, i, tmp, videomode;
809
810 tmp = 0;
811
812 puts("Video: ");
813
814 videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
815 /* get video mode via environment */
816 penv = env_get("videomode");
817 if (penv) {
818 /* decide if it is a string */
819 if (penv[0] <= '9') {
820 videomode = (int) simple_strtoul(penv, NULL, 16);
821 tmp = 1;
822 }
823 } else {
824 tmp = 1;
825 }
826 if (tmp) {
827 /* parameter are vesa modes */
828 /* search params */
829 for (i = 0; i < VESA_MODES_COUNT; i++) {
830 if (vesa_modes[i].vesanr == videomode)
831 break;
832 }
833 if (i == VESA_MODES_COUNT) {
834 printf("No VESA Mode found, switching to mode 0x%x ",
835 CONFIG_SYS_DEFAULT_VIDEO_MODE);
836 i = 0;
837 }
838 mode = (struct ctfb_res_modes *)
839 &res_mode_init[vesa_modes[i].resindex];
840 bits_per_pixel = vesa_modes[i].bits_per_pixel;
841 } else {
842 mode = (struct ctfb_res_modes *) &var_mode;
843 bits_per_pixel = video_get_params(mode, penv);
844 }
845
846 /* calculate hsynch and vsynch freq (info only) */
847 t1 = (mode->left_margin + mode->xres +
848 mode->right_margin + mode->hsync_len) / 8;
849 t1 *= 8;
850 t1 *= mode->pixclock;
851 t1 /= 1000;
852 hsynch = 1000000000L / t1;
853 t1 *= (mode->upper_margin + mode->yres +
854 mode->lower_margin + mode->vsync_len);
855 t1 /= 1000;
856 vsynch = 1000000000L / t1;
857
858 /* fill in Graphic device struct */
859 sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
860 mode->xres, mode->yres,
861 bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
862 printf("%s\n", panel.modeIdent);
863 panel.winSizeX = mode->xres;
864 panel.winSizeY = mode->yres;
865 panel.plnSizeX = mode->xres;
866 panel.plnSizeY = mode->yres;
867
868 switch (bits_per_pixel) {
869 case 24:
870 panel.gdfBytesPP = 4;
871 panel.gdfIndex = GDF_32BIT_X888RGB;
872 break;
873 case 16:
874 panel.gdfBytesPP = 2;
875 panel.gdfIndex = GDF_16BIT_565RGB;
876 break;
877 default:
878 panel.gdfBytesPP = 1;
879 panel.gdfIndex = GDF__8BIT_INDEX;
880 break;
881 }
882
883 /* set up Hardware */
884 memsize = calc_fbsize();
885
886 debug("%s() allocating %d bytes\n", __func__, memsize);
887
888 /* fill in missing Graphic device struct */
889 panel.frameAdrs = (u32) malloc(memsize);
890 if (panel.frameAdrs == 0) {
891 printf("%s() malloc(%d) failed\n", __func__, memsize);
892 return 0;
893 }
894 panel.memSize = memsize;
895
896 ll_disp3_enable((void *) panel.frameAdrs);
897 memset((void *) panel.frameAdrs, 0, memsize);
898
899 debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
900 __func__, panel.frameAdrs, memsize);
901
902 return (void *) &panel;
903 }
904