1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Amlogic Meson Video Processing Unit driver 4 * 5 * Copyright (c) 2018 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9 #include "meson_vpu.h" 10 #include <power-domain.h> 11 #include <efi_loader.h> 12 #include <dm/device-internal.h> 13 #include <dm/uclass-internal.h> 14 #include <fdt_support.h> 15 #include <linux/sizes.h> 16 #include <asm/arch/mem.h> 17 #include "meson_registers.h" 18 #include "simplefb_common.h" 19 20 #define MESON_VPU_OVERSCAN SZ_64K 21 22 /* Static variable for use in meson_vpu_rsv_fb() */ 23 static struct meson_framebuffer { 24 u64 base; 25 u64 fb_size; 26 unsigned int xsize; 27 unsigned int ysize; 28 bool is_cvbs; 29 } meson_fb = { 0 }; 30 31 static int meson_vpu_setup_mode(struct udevice *dev, struct udevice *disp) 32 { 33 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 34 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 35 struct display_timing timing; 36 bool is_cvbs = false; 37 int ret = 0; 38 39 if (disp) { 40 ret = display_read_timing(disp, &timing); 41 if (ret) { 42 debug("%s: Failed to read timings\n", __func__); 43 goto cvbs; 44 } 45 46 uc_priv->xsize = timing.hactive.typ; 47 uc_priv->ysize = timing.vactive.typ; 48 49 ret = display_enable(disp, 0, &timing); 50 if (ret) 51 goto cvbs; 52 } else { 53 cvbs: 54 /* CVBS has a fixed 720x480i (NTSC) and 720x576i (PAL) */ 55 is_cvbs = true; 56 timing.flags = DISPLAY_FLAGS_INTERLACED; 57 uc_priv->xsize = 720; 58 uc_priv->ysize = 576; 59 } 60 61 uc_priv->bpix = VPU_MAX_LOG2_BPP; 62 63 meson_fb.is_cvbs = is_cvbs; 64 meson_fb.xsize = uc_priv->xsize; 65 meson_fb.ysize = uc_priv->ysize; 66 67 /* Move the framebuffer to the end of addressable ram */ 68 meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * 69 ((1 << VPU_MAX_LOG2_BPP) / 8) + 70 MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); 71 meson_fb.base = gd->bd->bi_dram[0].start + 72 gd->bd->bi_dram[0].size - meson_fb.fb_size; 73 74 /* Override the framebuffer address */ 75 uc_plat->base = meson_fb.base; 76 77 meson_vpu_setup_plane(dev, timing.flags & DISPLAY_FLAGS_INTERLACED); 78 meson_vpu_setup_venc(dev, &timing, is_cvbs); 79 meson_vpu_setup_vclk(dev, &timing, is_cvbs); 80 81 video_set_flush_dcache(dev, 1); 82 83 return 0; 84 } 85 86 static const struct udevice_id meson_vpu_ids[] = { 87 { .compatible = "amlogic,meson-gxbb-vpu", .data = VPU_COMPATIBLE_GXBB }, 88 { .compatible = "amlogic,meson-gxl-vpu", .data = VPU_COMPATIBLE_GXL }, 89 { .compatible = "amlogic,meson-gxm-vpu", .data = VPU_COMPATIBLE_GXM }, 90 { } 91 }; 92 93 static int meson_vpu_probe(struct udevice *dev) 94 { 95 struct meson_vpu_priv *priv = dev_get_priv(dev); 96 struct power_domain pd; 97 struct udevice *disp; 98 int ret; 99 100 /* Before relocation we don't need to do anything */ 101 if (!(gd->flags & GD_FLG_RELOC)) 102 return 0; 103 104 priv->dev = dev; 105 106 priv->io_base = dev_remap_addr_index(dev, 0); 107 if (!priv->io_base) 108 return -EINVAL; 109 110 priv->hhi_base = dev_remap_addr_index(dev, 1); 111 if (!priv->hhi_base) 112 return -EINVAL; 113 114 priv->dmc_base = dev_remap_addr_index(dev, 2); 115 if (!priv->dmc_base) 116 return -EINVAL; 117 118 ret = power_domain_get(dev, &pd); 119 if (ret) 120 return ret; 121 122 ret = power_domain_on(&pd); 123 if (ret) 124 return ret; 125 126 meson_vpu_init(dev); 127 128 /* probe the display */ 129 ret = uclass_get_device(UCLASS_DISPLAY, 0, &disp); 130 131 return meson_vpu_setup_mode(dev, ret ? NULL : disp); 132 } 133 134 static int meson_vpu_bind(struct udevice *dev) 135 { 136 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 137 138 plat->size = VPU_MAX_WIDTH * VPU_MAX_HEIGHT * 139 (1 << VPU_MAX_LOG2_BPP) / 8; 140 141 return 0; 142 } 143 144 #if defined(CONFIG_VIDEO_DT_SIMPLEFB) 145 static void meson_vpu_setup_simplefb(void *fdt) 146 { 147 const char *pipeline = NULL; 148 u64 mem_start, mem_size; 149 int offset, ret; 150 151 if (meson_fb.is_cvbs) 152 pipeline = "vpu-cvbs"; 153 else 154 pipeline = "vpu-hdmi"; 155 156 offset = meson_simplefb_fdt_match(fdt, pipeline); 157 if (offset < 0) { 158 eprintf("Cannot setup simplefb: node not found\n"); 159 160 /* If simplefb is missing, add it as reserved memory */ 161 meson_board_add_reserved_memory(fdt, meson_fb.base, 162 meson_fb.fb_size); 163 164 return; 165 } 166 167 /* 168 * SimpleFB will try to iomap the framebuffer, so we can't use 169 * fdt_add_mem_rsv on the memory area. Instead, the FB is stored 170 * at the end of the RAM and we strip this portion from the kernel 171 * allowed region 172 */ 173 mem_start = gd->bd->bi_dram[0].start; 174 mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; 175 ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); 176 if (ret) { 177 eprintf("Cannot setup simplefb: Error reserving memory\n"); 178 return; 179 } 180 181 ret = fdt_setup_simplefb_node(fdt, offset, meson_fb.base, 182 meson_fb.xsize, meson_fb.ysize, 183 meson_fb.xsize * 4, "x8r8g8b8"); 184 if (ret) 185 eprintf("Cannot setup simplefb: Error setting properties\n"); 186 } 187 #endif 188 189 void meson_vpu_rsv_fb(void *fdt) 190 { 191 if (!meson_fb.base || !meson_fb.xsize || !meson_fb.ysize) 192 return; 193 194 #if defined(CONFIG_EFI_LOADER) 195 efi_add_memory_map(meson_fb.base, meson_fb.fb_size >> EFI_PAGE_SHIFT, 196 EFI_RESERVED_MEMORY_TYPE, false); 197 #endif 198 #if defined(CONFIG_VIDEO_DT_SIMPLEFB) 199 meson_vpu_setup_simplefb(fdt); 200 #endif 201 } 202 203 U_BOOT_DRIVER(meson_vpu) = { 204 .name = "meson_vpu", 205 .id = UCLASS_VIDEO, 206 .of_match = meson_vpu_ids, 207 .probe = meson_vpu_probe, 208 .bind = meson_vpu_bind, 209 .priv_auto_alloc_size = sizeof(struct meson_vpu_priv), 210 .flags = DM_FLAG_PRE_RELOC, 211 }; 212