1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 */ 7 8 #ifndef __MESON_DW_HDMI_H 9 #define __MESON_DW_HDMI_H 10 11 /* 12 * Bit 7 RW Reserved. Default 1. 13 * Bit 6 RW Reserved. Default 1. 14 * Bit 5 RW Reserved. Default 1. 15 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. 16 * Default 1. 17 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; 18 * 0=Release from reset. 19 * Default 1. 20 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. 21 * Default 1. 22 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; 23 * 0=Release from reset. Default 1. 24 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; 25 * 0=Release from reset. Default 1. 26 */ 27 #define HDMITX_TOP_SW_RESET (0x000) 28 29 /* 30 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. 31 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. 32 * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. 33 * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. 34 * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. 35 * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. 36 * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. 37 * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. 38 * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. 39 * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. 40 */ 41 #define HDMITX_TOP_CLK_CNTL (0x001) 42 43 /* 44 * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. 45 * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. 46 */ 47 #define HDMITX_TOP_HPD_FILTER (0x002) 48 49 /* 50 * intr_maskn: MASK_N, one bit per interrupt source. 51 * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. 52 * [ 4] hdcp22_rndnum_err 53 * [ 3] nonce_rfrsh_rise 54 * [ 2] hpd_fall_intr 55 * [ 1] hpd_rise_intr 56 * [ 0] core_intr 57 */ 58 #define HDMITX_TOP_INTR_MASKN (0x003) 59 60 /* 61 * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt 62 * bit, read back the interrupt status. 63 * Bit 31 R IP interrupt status 64 * Bit 2 RW hpd_fall 65 * Bit 1 RW hpd_rise 66 * Bit 0 RW IP interrupt 67 */ 68 #define HDMITX_TOP_INTR_STAT (0x004) 69 70 /* 71 * [4] hdcp22_rndnum_err 72 * [3] nonce_rfrsh_rise 73 * [2] hpd_fall 74 * [1] hpd_rise 75 * [0] core_intr_rise 76 */ 77 #define HDMITX_TOP_INTR_STAT_CLR (0x005) 78 79 #define HDMITX_TOP_INTR_CORE BIT(0) 80 #define HDMITX_TOP_INTR_HPD_RISE BIT(1) 81 #define HDMITX_TOP_INTR_HPD_FALL BIT(2) 82 83 /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; 84 * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. 85 * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern 86 * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. 87 * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable. 88 * Default 0. 89 * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. 90 * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; 91 * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. 92 * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. 93 */ 94 #define HDMITX_TOP_BIST_CNTL (0x006) 95 96 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ 97 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ 98 /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ 99 #define HDMITX_TOP_SHIFT_PTTN_012 (0x007) 100 101 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ 102 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ 103 /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ 104 #define HDMITX_TOP_SHIFT_PTTN_345 (0x008) 105 106 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ 107 /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ 108 #define HDMITX_TOP_SHIFT_PTTN_67 (0x009) 109 110 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ 111 /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ 112 #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A) 113 114 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ 115 /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ 116 #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) 117 118 /* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, 119 * used when TMDS CLK rate = TMDS character rate /4. Default 0. 120 * Bit 0 R Reserved. Default 0. 121 * [ 1] shift_tmds_clk_pttn 122 * [ 0] load_tmds_clk_pttn 123 */ 124 #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) 125 126 /* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM 127 * failure, write 1 to clear the failure flag. Default 0. 128 */ 129 #define HDMITX_TOP_REVOCMEM_STAT (0x00D) 130 131 /* Bit 0 R filtered HPD status. */ 132 #define HDMITX_TOP_STAT0 (0x00E) 133 134 #endif /* __MESON_DW_HDMI_H */ 135