1 /* 2 * (C) Copyright 2007 3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime 26 * PCI and video mode code was derived from smiLynxEM driver. 27 */ 28 29 #include <common.h> 30 31 #include <asm/io.h> 32 #include <pci.h> 33 #include <video_fb.h> 34 #include "videomodes.h" 35 #include <mb862xx.h> 36 37 #if defined(CONFIG_POST) 38 #include <post.h> 39 #endif 40 41 /* 42 * Graphic Device 43 */ 44 GraphicDevice mb862xx; 45 46 /* 47 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; 48 */ 49 #define VIDEO_MEM_SIZE 0x01FC0000 50 51 #if defined(CONFIG_PCI) 52 #if defined(CONFIG_VIDEO_CORALP) 53 54 static struct pci_device_id supported[] = { 55 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, 56 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, 57 { } 58 }; 59 60 /* Internal clock frequency divider table, index is mode number */ 61 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; 62 #endif 63 #endif 64 65 #if defined(CONFIG_VIDEO_CORALP) 66 #define rd_io in32r 67 #define wr_io out32r 68 #else 69 #define rd_io(addr) in_be32((volatile unsigned *)(addr)) 70 #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) 71 #endif 72 73 #define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off))) 74 #define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \ 75 (val)) 76 #define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off))) 77 #define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \ 78 (val)) 79 #define DE_RD_REG(off) rd_io((dev->dprBase + (off))) 80 #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val)) 81 82 #if defined(CONFIG_VIDEO_CORALP) 83 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val)) 84 #else 85 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val)) 86 #endif 87 88 #define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \ 89 (GC_DISP_BASE | GC_L0PAL0) + \ 90 ((idx) << 2)), (val)) 91 92 static void gdc_sw_reset (void) 93 { 94 GraphicDevice *dev = &mb862xx; 95 96 HOST_WR_REG (GC_SRST, 0x1); 97 udelay (500); 98 video_hw_init (); 99 } 100 101 102 static void de_wait (void) 103 { 104 GraphicDevice *dev = &mb862xx; 105 int lc = 0x10000; 106 107 /* 108 * Sync with software writes to framebuffer, 109 * try to reset if engine locked 110 */ 111 while (DE_RD_REG (GC_CTR) & 0x00000131) 112 if (lc-- < 0) { 113 gdc_sw_reset (); 114 puts ("gdc reset done after drawing engine lock.\n"); 115 break; 116 } 117 } 118 119 static void de_wait_slots (int slots) 120 { 121 GraphicDevice *dev = &mb862xx; 122 int lc = 0x10000; 123 124 /* Wait for free fifo slots */ 125 while (DE_RD_REG (GC_IFCNT) < slots) 126 if (lc-- < 0) { 127 gdc_sw_reset (); 128 puts ("gdc reset done after drawing engine lock.\n"); 129 break; 130 } 131 } 132 133 #if !defined(CONFIG_VIDEO_CORALP) 134 static void board_disp_init (void) 135 { 136 GraphicDevice *dev = &mb862xx; 137 const gdc_regs *regs = board_get_regs (); 138 139 while (regs->index) { 140 DISP_WR_REG (regs->index, regs->value); 141 regs++; 142 } 143 } 144 #endif 145 146 /* 147 * Init drawing engine 148 */ 149 static void de_init (void) 150 { 151 GraphicDevice *dev = &mb862xx; 152 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000; 153 154 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; 155 156 /* Setup mode and fbbase, xres, fg, bg */ 157 de_wait_slots (2); 158 DE_WR_FIFO (0xf1010108); 159 DE_WR_FIFO (cf | 0x0300); 160 DE_WR_REG (GC_FBR, 0x0); 161 DE_WR_REG (GC_XRES, dev->winSizeX); 162 DE_WR_REG (GC_FC, 0x0); 163 DE_WR_REG (GC_BC, 0x0); 164 /* Reset clipping */ 165 DE_WR_REG (GC_CXMIN, 0x0); 166 DE_WR_REG (GC_CXMAX, dev->winSizeX); 167 DE_WR_REG (GC_CYMIN, 0x0); 168 DE_WR_REG (GC_CYMAX, dev->winSizeY); 169 170 /* Clear framebuffer using drawing engine */ 171 de_wait_slots (3); 172 DE_WR_FIFO (0x09410000); 173 DE_WR_FIFO (0x00000000); 174 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); 175 /* sync with SW access to framebuffer */ 176 de_wait (); 177 } 178 179 #if defined(CONFIG_VIDEO_CORALP) 180 unsigned int pci_video_init (void) 181 { 182 GraphicDevice *dev = &mb862xx; 183 pci_dev_t devbusfn; 184 185 if ((devbusfn = pci_find_devices (supported, 0)) < 0) { 186 puts ("PCI video controller not found!\n"); 187 return 0; 188 } 189 190 /* PCI setup */ 191 pci_write_config_dword (devbusfn, PCI_COMMAND, 192 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 193 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs); 194 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs); 195 196 if (dev->frameAdrs == 0) { 197 puts ("PCI config: failed to get base address\n"); 198 return 0; 199 } 200 201 dev->pciBase = dev->frameAdrs; 202 203 /* Setup clocks and memory mode for Coral-P Eval. Board */ 204 HOST_WR_REG (GC_CCF, 0x00090000); 205 udelay (200); 206 HOST_WR_REG (GC_MMR, 0x11d7fa13); 207 udelay (100); 208 return dev->frameAdrs; 209 } 210 211 unsigned int card_init (void) 212 { 213 GraphicDevice *dev = &mb862xx; 214 unsigned int cf, videomode, div = 0; 215 unsigned long t1, hsync, vsync; 216 char *penv; 217 int tmp, i, bpp; 218 struct ctfb_res_modes *res_mode; 219 struct ctfb_res_modes var_mode; 220 221 memset (dev, 0, sizeof (GraphicDevice)); 222 223 if (!pci_video_init ()) 224 return 0; 225 226 puts ("CoralP\n"); 227 228 tmp = 0; 229 videomode = 0x310; 230 /* get video mode via environment */ 231 if ((penv = getenv ("videomode")) != NULL) { 232 /* decide if it is a string */ 233 if (penv[0] <= '9') { 234 videomode = (int) simple_strtoul (penv, NULL, 16); 235 tmp = 1; 236 } 237 } else { 238 tmp = 1; 239 } 240 241 if (tmp) { 242 /* parameter are vesa modes, search params */ 243 for (i = 0; i < VESA_MODES_COUNT; i++) { 244 if (vesa_modes[i].vesanr == videomode) 245 break; 246 } 247 if (i == VESA_MODES_COUNT) { 248 printf ("\tno VESA Mode found, fallback to mode 0x%x\n", 249 videomode); 250 i = 0; 251 } 252 res_mode = (struct ctfb_res_modes *) 253 &res_mode_init[vesa_modes[i].resindex]; 254 if (vesa_modes[i].resindex > 2) { 255 puts ("\tUnsupported resolution, using default\n"); 256 bpp = vesa_modes[1].bits_per_pixel; 257 div = fr_div[1]; 258 } 259 bpp = vesa_modes[i].bits_per_pixel; 260 div = fr_div[vesa_modes[i].resindex]; 261 } else { 262 res_mode = (struct ctfb_res_modes *) &var_mode; 263 bpp = video_get_params (res_mode, penv); 264 } 265 266 /* calculate hsync and vsync freq (info only) */ 267 t1 = (res_mode->left_margin + res_mode->xres + 268 res_mode->right_margin + res_mode->hsync_len) / 8; 269 t1 *= 8; 270 t1 *= res_mode->pixclock; 271 t1 /= 1000; 272 hsync = 1000000000L / t1; 273 t1 *= (res_mode->upper_margin + res_mode->yres + 274 res_mode->lower_margin + res_mode->vsync_len); 275 t1 /= 1000; 276 vsync = 1000000000L / t1; 277 278 /* fill in Graphic device struct */ 279 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 280 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); 281 printf ("\t%s\n", dev->modeIdent); 282 dev->winSizeX = res_mode->xres; 283 dev->winSizeY = res_mode->yres; 284 dev->memSize = VIDEO_MEM_SIZE; 285 286 switch (bpp) { 287 case 8: 288 dev->gdfIndex = GDF__8BIT_INDEX; 289 dev->gdfBytesPP = 1; 290 break; 291 case 15: 292 case 16: 293 dev->gdfIndex = GDF_15BIT_555RGB; 294 dev->gdfBytesPP = 2; 295 break; 296 default: 297 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n", 298 bpp); 299 puts ("\tfallback to 15bpp\n"); 300 dev->gdfIndex = GDF_15BIT_555RGB; 301 dev->gdfBytesPP = 2; 302 } 303 304 /* Setup dot clock (internal pll, division rate) */ 305 DISP_WR_REG (GC_DCM1, div); 306 /* L0 init */ 307 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; 308 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | 309 (dev->winSizeY - 1) | cf); 310 DISP_WR_REG (GC_L0OA0, 0x0); 311 DISP_WR_REG (GC_L0DA0, 0x0); 312 DISP_WR_REG (GC_L0DY_L0DX, 0x0); 313 DISP_WR_REG (GC_L0EM, 0x0); 314 DISP_WR_REG (GC_L0WY_L0WX, 0x0); 315 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX); 316 317 /* Display timing init */ 318 DISP_WR_REG (GC_HTP_A, (dev->winSizeX + 319 res_mode->left_margin + 320 res_mode->right_margin + 321 res_mode->hsync_len - 1) << 16); 322 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 | 323 (dev->winSizeX - 1)); 324 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 | 325 (res_mode->hsync_len - 1) << 16 | 326 (dev->winSizeX + 327 res_mode->right_margin - 1)); 328 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin + 329 res_mode->upper_margin + 330 res_mode->vsync_len - 1) << 16); 331 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 | 332 (dev->winSizeY + 333 res_mode->lower_margin - 1)); 334 DISP_WR_REG (GC_WY_WX, 0x0); 335 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX); 336 /* Display enable, L0 layer */ 337 DISP_WR_REG (GC_DCM1, 0x80010000 | div); 338 339 return dev->frameAdrs; 340 } 341 #endif 342 343 344 #if !defined(CONFIG_VIDEO_CORALP) 345 int mb862xx_probe(unsigned int addr) 346 { 347 GraphicDevice *dev = &mb862xx; 348 unsigned int reg; 349 350 dev->frameAdrs = addr; 351 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; 352 353 /* Try to access GDC ID/Revision registers */ 354 reg = HOST_RD_REG (GC_CID); 355 reg = HOST_RD_REG (GC_CID); 356 if (reg == 0x303) { 357 reg = DE_RD_REG(GC_REV); 358 reg = DE_RD_REG(GC_REV); 359 if ((reg & ~0xff) == 0x20050100) 360 return MB862XX_TYPE_LIME; 361 } 362 363 return 0; 364 } 365 #endif 366 367 void *video_hw_init (void) 368 { 369 GraphicDevice *dev = &mb862xx; 370 371 puts ("Video: Fujitsu "); 372 373 memset (dev, 0, sizeof (GraphicDevice)); 374 375 #if defined(CONFIG_VIDEO_CORALP) 376 if (card_init () == 0) 377 return NULL; 378 #else 379 /* 380 * Preliminary init of the onboard graphic controller, 381 * retrieve base address 382 */ 383 if ((dev->frameAdrs = board_video_init ()) == 0) { 384 puts ("Controller not found!\n"); 385 return NULL; 386 } else { 387 puts ("Lime\n"); 388 389 /* Set Change of Clock Frequency Register */ 390 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF); 391 /* Delay required */ 392 udelay(300); 393 /* Set Memory I/F Mode Register) */ 394 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR); 395 } 396 #endif 397 398 de_init (); 399 400 #if !defined(CONFIG_VIDEO_CORALP) 401 board_disp_init (); 402 #endif 403 404 #if (defined(CONFIG_LWMON5) || \ 405 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) 406 /* Lamp on */ 407 board_backlight_switch (1); 408 #endif 409 410 return dev; 411 } 412 413 /* 414 * Set a RGB color in the LUT 415 */ 416 void video_set_lut (unsigned int index, unsigned char r, 417 unsigned char g, unsigned char b) 418 { 419 GraphicDevice *dev = &mb862xx; 420 421 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); 422 } 423 424 /* 425 * Drawing engine Fill and BitBlt screen region 426 */ 427 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, 428 unsigned int dst_y, unsigned int dim_x, 429 unsigned int dim_y, unsigned int color) 430 { 431 GraphicDevice *dev = &mb862xx; 432 433 de_wait_slots (3); 434 DE_WR_REG (GC_FC, color); 435 DE_WR_FIFO (0x09410000); 436 DE_WR_FIFO ((dst_y << 16) | dst_x); 437 DE_WR_FIFO ((dim_y << 16) | dim_x); 438 de_wait (); 439 } 440 441 void video_hw_bitblt (unsigned int bpp, unsigned int src_x, 442 unsigned int src_y, unsigned int dst_x, 443 unsigned int dst_y, unsigned int width, 444 unsigned int height) 445 { 446 GraphicDevice *dev = &mb862xx; 447 unsigned int ctrl = 0x0d000000L; 448 449 if (src_x >= dst_x && src_y >= dst_y) 450 ctrl |= 0x00440000L; 451 else if (src_x >= dst_x && src_y <= dst_y) 452 ctrl |= 0x00460000L; 453 else if (src_x <= dst_x && src_y >= dst_y) 454 ctrl |= 0x00450000L; 455 else 456 ctrl |= 0x00470000L; 457 458 de_wait_slots (4); 459 DE_WR_FIFO (ctrl); 460 DE_WR_FIFO ((src_y << 16) | src_x); 461 DE_WR_FIFO ((dst_y << 16) | dst_x); 462 DE_WR_FIFO ((height << 16) | width); 463 de_wait (); /* sync */ 464 } 465