1 /* 2 * (C) Copyright 2007 3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime 26 * PCI and video mode code was derived from smiLynxEM driver. 27 */ 28 29 #include <common.h> 30 31 #include <asm/io.h> 32 #include <pci.h> 33 #include <video_fb.h> 34 #include "videomodes.h" 35 #include <mb862xx.h> 36 37 #if defined(CONFIG_POST) 38 #include <post.h> 39 #endif 40 /* 41 * Graphic Device 42 */ 43 GraphicDevice mb862xx; 44 45 /* 46 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; 47 */ 48 #define VIDEO_MEM_SIZE 0x01FC0000 49 50 #if defined(CONFIG_PCI) 51 #if defined(CONFIG_VIDEO_CORALP) 52 53 static struct pci_device_id supported[] = { 54 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, 55 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, 56 { } 57 }; 58 59 /* Internal clock frequency divider table, index is mode number */ 60 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; 61 #endif 62 #endif 63 64 #if defined(CONFIG_VIDEO_CORALP) 65 #define rd_io in32r 66 #define wr_io out32r 67 #else 68 #define rd_io(addr) in_be32((volatile unsigned*)(addr)) 69 #define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) 70 #endif 71 72 #define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) 73 #define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) 74 #define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) 75 #define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) 76 #define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) 77 #define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) 78 79 #if defined(CONFIG_VIDEO_CORALP) 80 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) 81 #else 82 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) 83 #endif 84 85 #define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) 86 #define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) 87 #define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) 88 #define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) 89 #define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) 90 #define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) 91 #define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) 92 #define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) 93 94 static void gdc_sw_reset(void) 95 { 96 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 97 HOST_WR_REG (0x002c, 0x00000001); 98 udelay (500); 99 video_hw_init (); 100 } 101 102 103 static void de_wait(void) 104 { 105 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 106 int lc = 0x10000; 107 108 /* Sync with software writes to framebuffer, 109 try to reset if engine locked */ 110 while (DE_RD_REG (0x0400) & 0x00000131) 111 if (lc-- < 0) { 112 gdc_sw_reset (); 113 printf ("gdc reset done after drawing engine lock...\n"); 114 break; 115 } 116 } 117 118 static void de_wait_slots(int slots) 119 { 120 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 121 int lc = 0x10000; 122 123 /* Wait for free fifo slots */ 124 while (DE_RD_REG (0x0408) < slots) 125 if (lc-- < 0) { 126 gdc_sw_reset (); 127 printf ("gdc reset done after drawing engine lock...\n"); 128 break; 129 } 130 } 131 132 #if !defined(CONFIG_VIDEO_CORALP) 133 static void board_disp_init(void) 134 { 135 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 136 const gdc_regs *regs = board_get_regs (); 137 138 while (regs->index) { 139 DISP_WR_REG (regs->index, regs->value); 140 regs++; 141 } 142 } 143 #endif 144 145 /* 146 * Init drawing engine 147 */ 148 static void de_init (void) 149 { 150 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 151 int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; 152 153 pGD->dprBase = pGD->frameAdrs + 0x01ff0000; 154 155 /* Setup mode and fbbase, xres, fg, bg */ 156 de_wait_slots (2); 157 DE_WR_FIFO (0xf1010108); 158 DE_WR_FIFO (cf | 0x0300); 159 DE_WR_REG (0x0440, 0x0000); 160 DE_WR_REG (0x0444, pGD->winSizeX); 161 DE_WR_REG (0x0480, 0x0000); 162 DE_WR_REG (0x0484, 0x0000); 163 /* Reset clipping */ 164 DE_WR_REG (0x0454, 0x0000); 165 DE_WR_REG (0x0458, pGD->winSizeX); 166 DE_WR_REG (0x045c, 0x0000); 167 DE_WR_REG (0x0460, pGD->winSizeY); 168 169 /* Clear framebuffer using drawing engine */ 170 de_wait_slots (3); 171 DE_WR_FIFO (0x09410000); 172 DE_WR_FIFO (0x00000000); 173 DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); 174 /* sync with SW access to framebuffer */ 175 de_wait (); 176 } 177 178 #if defined(CONFIG_VIDEO_CORALP) 179 unsigned int pci_video_init(void) 180 { 181 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 182 pci_dev_t devbusfn; 183 184 if ((devbusfn = pci_find_devices(supported, 0)) < 0) 185 { 186 printf ("PCI video controller not found!\n"); 187 return 0; 188 } 189 190 /* PCI setup */ 191 pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 192 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); 193 pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); 194 195 if (pGD->frameAdrs == 0) { 196 printf ("PCI config: failed to get base address\n"); 197 return 0; 198 } 199 200 pGD->pciBase = pGD->frameAdrs; 201 202 /* Setup clocks and memory mode for Coral-P Eval. Board */ 203 HOST_WR_REG (0x0038, 0x00090000); 204 udelay (200); 205 HOST_WR_REG (0xfffc, 0x11d7fa13); 206 udelay (100); 207 return pGD->frameAdrs; 208 } 209 210 unsigned int card_init (void) 211 { 212 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 213 unsigned int cf, videomode, div = 0; 214 unsigned long t1, hsync, vsync; 215 char *penv; 216 int tmp, i, bpp; 217 struct ctfb_res_modes *res_mode; 218 struct ctfb_res_modes var_mode; 219 220 memset (pGD, 0, sizeof (GraphicDevice)); 221 222 if (!pci_video_init ()) { 223 return 0; 224 } 225 226 printf ("CoralP\n"); 227 228 tmp = 0; 229 videomode = 0x310; 230 /* get video mode via environment */ 231 if ((penv = getenv ("videomode")) != NULL) { 232 /* deceide if it is a string */ 233 if (penv[0] <= '9') { 234 videomode = (int) simple_strtoul (penv, NULL, 16); 235 tmp = 1; 236 } 237 } else { 238 tmp = 1; 239 } 240 if (tmp) { 241 /* parameter are vesa modes */ 242 /* search params */ 243 for (i = 0; i < VESA_MODES_COUNT; i++) { 244 if (vesa_modes[i].vesanr == videomode) 245 break; 246 } 247 if (i == VESA_MODES_COUNT) { 248 printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); 249 i = 0; 250 } 251 res_mode = 252 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; 253 if (vesa_modes[i].resindex > 2) { 254 printf ("\tUnsupported resolution, switching to default\n"); 255 bpp = vesa_modes[1].bits_per_pixel; 256 div = fr_div[1]; 257 } 258 bpp = vesa_modes[i].bits_per_pixel; 259 div = fr_div[vesa_modes[i].resindex]; 260 } else { 261 262 res_mode = (struct ctfb_res_modes *) &var_mode; 263 bpp = video_get_params (res_mode, penv); 264 } 265 266 /* calculate hsync and vsync freq (info only) */ 267 t1 = (res_mode->left_margin + res_mode->xres + 268 res_mode->right_margin + res_mode->hsync_len) / 8; 269 t1 *= 8; 270 t1 *= res_mode->pixclock; 271 t1 /= 1000; 272 hsync = 1000000000L / t1; 273 t1 *= (res_mode->upper_margin + res_mode->yres + 274 res_mode->lower_margin + res_mode->vsync_len); 275 t1 /= 1000; 276 vsync = 1000000000L / t1; 277 278 /* fill in Graphic device struct */ 279 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 280 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); 281 printf ("\t%s\n", pGD->modeIdent); 282 pGD->winSizeX = res_mode->xres; 283 pGD->winSizeY = res_mode->yres; 284 pGD->memSize = VIDEO_MEM_SIZE; 285 286 switch (bpp) { 287 case 8: 288 pGD->gdfIndex = GDF__8BIT_INDEX; 289 pGD->gdfBytesPP = 1; 290 break; 291 case 15: 292 case 16: 293 pGD->gdfIndex = GDF_15BIT_555RGB; 294 pGD->gdfBytesPP = 2; 295 break; 296 default: 297 printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); 298 printf ("\tSwitching back to 15bpp\n"); 299 pGD->gdfIndex = GDF_15BIT_555RGB; 300 pGD->gdfBytesPP = 2; 301 } 302 303 /* Setup dot clock (internal pll, division rate) */ 304 DISP_WR_REG (0x0100, div); 305 /* L0 init */ 306 cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; 307 DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | 308 (pGD->winSizeY-1) | 309 cf); 310 DISP_WR_REG (0x0024, 0x00000000); 311 DISP_WR_REG (0x0028, 0x00000000); 312 DISP_WR_REG (0x002c, 0x00000000); 313 DISP_WR_REG (0x0110, 0x00000000); 314 DISP_WR_REG (0x0114, 0x00000000); 315 DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); 316 317 /* Display timing init */ 318 DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); 319 DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); 320 DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); 321 DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); 322 DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); 323 DISP_WR_REG (0x0018, 0x00000000); 324 DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); 325 /* Display enable, L0 layer */ 326 DISP_WR_REG (0x0100, 0x80010000 | div); 327 328 return pGD->frameAdrs; 329 } 330 #endif 331 332 void *video_hw_init (void) 333 { 334 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 335 336 printf ("Video: Fujitsu "); 337 338 memset (pGD, 0, sizeof (GraphicDevice)); 339 340 #if defined(CONFIG_VIDEO_CORALP) 341 if (card_init () == 0) { 342 return (NULL); 343 } 344 #else 345 /* Preliminary init of the onboard graphic controller, 346 retrieve base address */ 347 if ((pGD->frameAdrs = board_video_init ()) == 0) { 348 printf ("Controller not found!\n"); 349 return (NULL); 350 } else 351 printf("Lime\n"); 352 #endif 353 354 de_init (); 355 356 #if !defined(CONFIG_VIDEO_CORALP) 357 board_disp_init(); 358 #endif 359 360 #if (defined(CONFIG_LWMON5) || \ 361 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) 362 /* Lamp on */ 363 board_backlight_switch (1); 364 #endif 365 366 return pGD; 367 } 368 369 /* 370 * Set a RGB color in the LUT 371 */ 372 void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) 373 { 374 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 375 376 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); 377 } 378 379 /* 380 * Drawing engine Fill and BitBlt screen region 381 */ 382 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, 383 unsigned int dim_x, unsigned int dim_y, unsigned int color) 384 { 385 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 386 387 de_wait_slots (3); 388 DE_WR_REG (0x0480, color); 389 DE_WR_FIFO (0x09410000); 390 DE_WR_FIFO ((dst_y << 16) | dst_x); 391 DE_WR_FIFO ((dim_y << 16) | dim_x); 392 de_wait (); 393 } 394 395 void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, 396 unsigned int dst_x, unsigned int dst_y, unsigned int width, 397 unsigned int height) 398 { 399 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 400 unsigned int ctrl = 0x0d000000L; 401 402 if (src_x >= dst_x && src_y >= dst_y) 403 ctrl |= 0x00440000L; 404 else if (src_x >= dst_x && src_y <= dst_y) 405 ctrl |= 0x00460000L; 406 else if (src_x <= dst_x && src_y >= dst_y) 407 ctrl |= 0x00450000L; 408 else 409 ctrl |= 0x00470000L; 410 411 de_wait_slots (4); 412 DE_WR_FIFO (ctrl); 413 DE_WR_FIFO ((src_y << 16) | src_x); 414 DE_WR_FIFO ((dst_y << 16) | dst_x); 415 DE_WR_FIFO ((height << 16) | width); 416 de_wait (); /* sync */ 417 } 418