1 /* 2 * (C) Copyright 2007 3 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime 26 * PCI and video mode code was derived from smiLynxEM driver. 27 */ 28 29 #include <common.h> 30 31 #if defined(CONFIG_VIDEO_MB862xx) 32 33 #include <asm/io.h> 34 #include <pci.h> 35 #include <video_fb.h> 36 #include "videomodes.h" 37 #include <mb862xx.h> 38 39 #if defined(CONFIG_POST) 40 #include <post.h> 41 #endif 42 /* 43 * Graphic Device 44 */ 45 GraphicDevice mb862xx; 46 47 /* 48 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; 49 */ 50 #define VIDEO_MEM_SIZE 0x01FC0000 51 52 #if defined(CONFIG_PCI) 53 #if defined(CONFIG_VIDEO_CORALP) 54 55 static struct pci_device_id supported[] = { 56 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, 57 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, 58 { } 59 }; 60 61 /* Internal clock frequency divider table, index is mode number */ 62 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; 63 #endif 64 #endif 65 66 #if defined(CONFIG_VIDEO_CORALP) 67 #define rd_io in32r 68 #define wr_io out32r 69 #else 70 #define rd_io(addr) in_be32((volatile unsigned*)(addr)) 71 #define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) 72 #endif 73 74 #define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) 75 #define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) 76 #define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) 77 #define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) 78 #define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) 79 #define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) 80 81 #if defined(CONFIG_VIDEO_CORALP) 82 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) 83 #else 84 #define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) 85 #endif 86 87 #define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) 88 #define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) 89 #define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) 90 #define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) 91 #define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) 92 #define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) 93 #define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) 94 #define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) 95 96 static void gdc_sw_reset(void) 97 { 98 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 99 HOST_WR_REG (0x002c, 0x00000001); 100 udelay (500); 101 video_hw_init (); 102 } 103 104 105 static void de_wait(void) 106 { 107 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 108 int lc = 0x10000; 109 110 /* Sync with software writes to framebuffer, 111 try to reset if engine locked */ 112 while (DE_RD_REG (0x0400) & 0x00000131) 113 if (lc-- < 0) { 114 gdc_sw_reset (); 115 printf ("gdc reset done after drawing engine lock...\n"); 116 break; 117 } 118 } 119 120 static void de_wait_slots(int slots) 121 { 122 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 123 int lc = 0x10000; 124 125 /* Wait for free fifo slots */ 126 while (DE_RD_REG (0x0408) < slots) 127 if (lc-- < 0) { 128 gdc_sw_reset (); 129 printf ("gdc reset done after drawing engine lock...\n"); 130 break; 131 } 132 } 133 134 #if !defined(CONFIG_VIDEO_CORALP) 135 static void board_disp_init(void) 136 { 137 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 138 const gdc_regs *regs = board_get_regs (); 139 140 while (regs->index) { 141 DISP_WR_REG (regs->index, regs->value); 142 regs++; 143 } 144 } 145 #endif 146 147 /* 148 * Init drawing engine 149 */ 150 static void de_init (void) 151 { 152 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 153 int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; 154 155 pGD->dprBase = pGD->frameAdrs + 0x01ff0000; 156 157 /* Setup mode and fbbase, xres, fg, bg */ 158 de_wait_slots (2); 159 DE_WR_FIFO (0xf1010108); 160 DE_WR_FIFO (cf | 0x0300); 161 DE_WR_REG (0x0440, 0x0000); 162 DE_WR_REG (0x0444, pGD->winSizeX); 163 DE_WR_REG (0x0480, 0x0000); 164 DE_WR_REG (0x0484, 0x0000); 165 /* Reset clipping */ 166 DE_WR_REG (0x0454, 0x0000); 167 DE_WR_REG (0x0458, pGD->winSizeX); 168 DE_WR_REG (0x045c, 0x0000); 169 DE_WR_REG (0x0460, pGD->winSizeY); 170 171 /* Clear framebuffer using drawing engine */ 172 de_wait_slots (3); 173 DE_WR_FIFO (0x09410000); 174 DE_WR_FIFO (0x00000000); 175 DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); 176 /* sync with SW access to framebuffer */ 177 de_wait (); 178 } 179 180 #if defined(CONFIG_VIDEO_CORALP) 181 unsigned int pci_video_init(void) 182 { 183 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 184 pci_dev_t devbusfn; 185 186 if ((devbusfn = pci_find_devices(supported, 0)) < 0) 187 { 188 printf ("PCI video controller not found!\n"); 189 return 0; 190 } 191 192 /* PCI setup */ 193 pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); 194 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); 195 pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); 196 197 if (pGD->frameAdrs == 0) { 198 printf ("PCI config: failed to get base address\n"); 199 return 0; 200 } 201 202 pGD->pciBase = pGD->frameAdrs; 203 204 /* Setup clocks and memory mode for Coral-P Eval. Board */ 205 HOST_WR_REG (0x0038, 0x00090000); 206 udelay (200); 207 HOST_WR_REG (0xfffc, 0x11d7fa13); 208 udelay (100); 209 return pGD->frameAdrs; 210 } 211 212 unsigned int card_init (void) 213 { 214 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 215 unsigned int cf, videomode, div = 0; 216 unsigned long t1, hsync, vsync; 217 char *penv; 218 int tmp, i, bpp; 219 struct ctfb_res_modes *res_mode; 220 struct ctfb_res_modes var_mode; 221 222 memset (pGD, 0, sizeof (GraphicDevice)); 223 224 if (!pci_video_init ()) { 225 return 0; 226 } 227 228 printf ("CoralP\n"); 229 230 tmp = 0; 231 videomode = 0x310; 232 /* get video mode via environment */ 233 if ((penv = getenv ("videomode")) != NULL) { 234 /* deceide if it is a string */ 235 if (penv[0] <= '9') { 236 videomode = (int) simple_strtoul (penv, NULL, 16); 237 tmp = 1; 238 } 239 } else { 240 tmp = 1; 241 } 242 if (tmp) { 243 /* parameter are vesa modes */ 244 /* search params */ 245 for (i = 0; i < VESA_MODES_COUNT; i++) { 246 if (vesa_modes[i].vesanr == videomode) 247 break; 248 } 249 if (i == VESA_MODES_COUNT) { 250 printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); 251 i = 0; 252 } 253 res_mode = 254 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; 255 if (vesa_modes[i].resindex > 2) { 256 printf ("\tUnsupported resolution, switching to default\n"); 257 bpp = vesa_modes[1].bits_per_pixel; 258 div = fr_div[1]; 259 } 260 bpp = vesa_modes[i].bits_per_pixel; 261 div = fr_div[vesa_modes[i].resindex]; 262 } else { 263 264 res_mode = (struct ctfb_res_modes *) &var_mode; 265 bpp = video_get_params (res_mode, penv); 266 } 267 268 /* calculate hsync and vsync freq (info only) */ 269 t1 = (res_mode->left_margin + res_mode->xres + 270 res_mode->right_margin + res_mode->hsync_len) / 8; 271 t1 *= 8; 272 t1 *= res_mode->pixclock; 273 t1 /= 1000; 274 hsync = 1000000000L / t1; 275 t1 *= (res_mode->upper_margin + res_mode->yres + 276 res_mode->lower_margin + res_mode->vsync_len); 277 t1 /= 1000; 278 vsync = 1000000000L / t1; 279 280 /* fill in Graphic device struct */ 281 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 282 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); 283 printf ("\t%s\n", pGD->modeIdent); 284 pGD->winSizeX = res_mode->xres; 285 pGD->winSizeY = res_mode->yres; 286 pGD->memSize = VIDEO_MEM_SIZE; 287 288 switch (bpp) { 289 case 8: 290 pGD->gdfIndex = GDF__8BIT_INDEX; 291 pGD->gdfBytesPP = 1; 292 break; 293 case 15: 294 case 16: 295 pGD->gdfIndex = GDF_15BIT_555RGB; 296 pGD->gdfBytesPP = 2; 297 break; 298 default: 299 printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); 300 printf ("\tSwitching back to 15bpp\n"); 301 pGD->gdfIndex = GDF_15BIT_555RGB; 302 pGD->gdfBytesPP = 2; 303 } 304 305 /* Setup dot clock (internal pll, division rate) */ 306 DISP_WR_REG (0x0100, div); 307 /* L0 init */ 308 cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; 309 DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | 310 (pGD->winSizeY-1) | 311 cf); 312 DISP_WR_REG (0x0024, 0x00000000); 313 DISP_WR_REG (0x0028, 0x00000000); 314 DISP_WR_REG (0x002c, 0x00000000); 315 DISP_WR_REG (0x0110, 0x00000000); 316 DISP_WR_REG (0x0114, 0x00000000); 317 DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); 318 319 /* Display timing init */ 320 DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); 321 DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); 322 DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); 323 DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); 324 DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); 325 DISP_WR_REG (0x0018, 0x00000000); 326 DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); 327 /* Display enable, L0 layer */ 328 DISP_WR_REG (0x0100, 0x80010000 | div); 329 330 return pGD->frameAdrs; 331 } 332 #endif 333 334 void *video_hw_init (void) 335 { 336 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 337 338 printf ("Video: Fujitsu "); 339 340 memset (pGD, 0, sizeof (GraphicDevice)); 341 342 #if defined(CONFIG_VIDEO_CORALP) 343 if (card_init () == 0) { 344 return (NULL); 345 } 346 #else 347 /* Preliminary init of the onboard graphic controller, 348 retrieve base address */ 349 if ((pGD->frameAdrs = board_video_init ()) == 0) { 350 printf ("Controller not found!\n"); 351 return (NULL); 352 } else 353 printf("Lime\n"); 354 #endif 355 356 de_init (); 357 358 #if !defined(CONFIG_VIDEO_CORALP) 359 board_disp_init(); 360 #endif 361 362 #if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON) 363 /* Lamp on */ 364 board_backlight_switch (1); 365 #endif 366 367 return pGD; 368 } 369 370 /* 371 * Set a RGB color in the LUT 372 */ 373 void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) 374 { 375 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 376 377 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); 378 } 379 380 /* 381 * Drawing engine Fill and BitBlt screen region 382 */ 383 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, 384 unsigned int dim_x, unsigned int dim_y, unsigned int color) 385 { 386 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 387 388 de_wait_slots (3); 389 DE_WR_REG (0x0480, color); 390 DE_WR_FIFO (0x09410000); 391 DE_WR_FIFO ((dst_y << 16) | dst_x); 392 DE_WR_FIFO ((dim_y << 16) | dim_x); 393 de_wait (); 394 } 395 396 void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, 397 unsigned int dst_x, unsigned int dst_y, unsigned int width, 398 unsigned int height) 399 { 400 GraphicDevice *pGD = (GraphicDevice *)&mb862xx; 401 unsigned int ctrl = 0x0d000000L; 402 403 if (src_x >= dst_x && src_y >= dst_y) 404 ctrl |= 0x00440000L; 405 else if (src_x >= dst_x && src_y <= dst_y) 406 ctrl |= 0x00460000L; 407 else if (src_x <= dst_x && src_y >= dst_y) 408 ctrl |= 0x00450000L; 409 else 410 ctrl |= 0x00470000L; 411 412 de_wait_slots (4); 413 DE_WR_FIFO (ctrl); 414 DE_WR_FIFO ((src_y << 16) | src_x); 415 DE_WR_FIFO ((dst_y << 16) | dst_x); 416 DE_WR_FIFO ((height << 16) | width); 417 de_wait (); /* sync */ 418 } 419 #endif /* CONFIG_VIDEO_MB862xx */ 420