1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016-2018 ARM Ltd.
4 * Author: Liviu Dudau <liviu.dudau@foss.arm.com>
5 *
6 */
7 #define DEBUG
8 #include <common.h>
9 #include <video.h>
10 #include <dm.h>
11 #ifdef CONFIG_DISPLAY
12 #include <display.h>
13 #endif
14 #include <fdtdec.h>
15 #include <asm/io.h>
16 #include <os.h>
17 #include <fdt_support.h>
18 #include <clk.h>
19 #include <linux/sizes.h>
20
21 #define MALIDP_CORE_ID 0x0018
22 #define MALIDP_REG_BG_COLOR 0x0044
23 #define MALIDP_LAYER_LV1 0x0100
24 #define MALIDP_DC_STATUS 0xc000
25 #define MALIDP_DC_CONTROL 0xc010
26 #define MALIDP_DC_CFG_VALID 0xc014
27
28 /* offsets inside the modesetting register block */
29 #define MALIDP_H_INTERVALS 0x0000
30 #define MALIDP_V_INTERVALS 0x0004
31 #define MALIDP_SYNC_CONTROL 0x0008
32 #define MALIDP_HV_ACTIVESIZE 0x000c
33 #define MALIDP_OUTPUT_DEPTH 0x001c
34
35 /* offsets inside the layer register block */
36 #define MALIDP_LAYER_FORMAT 0x0000
37 #define MALIDP_LAYER_CONTROL 0x0004
38 #define MALIDP_LAYER_IN_SIZE 0x000c
39 #define MALIDP_LAYER_CMP_SIZE 0x0010
40 #define MALIDP_LAYER_STRIDE 0x0018
41 #define MALIDP_LAYER_PTR_LOW 0x0024
42 #define MALIDP_LAYER_PTR_HIGH 0x0028
43
44 /* offsets inside the IRQ control blocks */
45 #define MALIDP_REG_MASKIRQ 0x0008
46 #define MALIDP_REG_CLEARIRQ 0x000c
47
48 #define M1BITS 0x0001
49 #define M2BITS 0x0003
50 #define M4BITS 0x000f
51 #define M8BITS 0x00ff
52 #define M10BITS 0x03ff
53 #define M12BITS 0x0fff
54 #define M13BITS 0x1fff
55 #define M16BITS 0xffff
56 #define M17BITS 0x1ffff
57
58 #define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
59 #define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
60 #define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
61 #define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
62 #define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
63 #define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
64 #define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
65 #define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
66
67 #define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
68 #define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
69
70 #define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
71 #define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
72
73 #define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
74 #define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
75
76 #define MALIDP_FORMAT_ARGB8888 0x08
77 #define MALIDP_DEFAULT_BG_R 0x0
78 #define MALIDP_DEFAULT_BG_G 0x0
79 #define MALIDP_DEFAULT_BG_B 0x0
80
81 #define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
82
83 #define MALIDP500 0x500
84
85 DECLARE_GLOBAL_DATA_PTR;
86
87 struct malidp_priv {
88 phys_addr_t base_addr;
89 phys_addr_t dc_status_addr;
90 phys_addr_t dc_control_addr;
91 phys_addr_t cval_addr;
92 struct udevice *display; /* display device attached */
93 struct clk aclk;
94 struct clk pxlclk;
95 u16 modeset_regs_offset;
96 u8 config_bit_shift;
97 u8 clear_irq; /* offset for IRQ clear register */
98 };
99
100 static const struct video_ops malidp_ops = {
101 };
102
malidp_get_hwid(phys_addr_t base_addr)103 static int malidp_get_hwid(phys_addr_t base_addr)
104 {
105 int hwid;
106
107 /*
108 * reading from the old CORE_ID offset will always
109 * return 0x5000000 on DP500
110 */
111 hwid = readl(base_addr + MALIDP_CORE_ID);
112 if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
113 return hwid;
114 /* otherwise try the other gen CORE_ID offset */
115 hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
116
117 return hwid;
118 }
119
120 /*
121 * wait for config mode bit setup to be acted upon by the hardware
122 */
malidp_wait_configdone(struct malidp_priv * malidp)123 static int malidp_wait_configdone(struct malidp_priv *malidp)
124 {
125 u32 status, tries = 300;
126
127 while (tries--) {
128 status = readl(malidp->dc_status_addr);
129 if ((status >> malidp->config_bit_shift) & 1)
130 break;
131 udelay(500);
132 }
133
134 if (!tries)
135 return -ETIMEDOUT;
136
137 return 0;
138 }
139
140 /*
141 * signal the hardware to enter configuration mode
142 */
malidp_enter_config(struct malidp_priv * malidp)143 static int malidp_enter_config(struct malidp_priv *malidp)
144 {
145 setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
146 return malidp_wait_configdone(malidp);
147 }
148
149 /*
150 * signal the hardware to exit configuration mode
151 */
malidp_leave_config(struct malidp_priv * malidp)152 static int malidp_leave_config(struct malidp_priv *malidp)
153 {
154 clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
155 return malidp_wait_configdone(malidp);
156 }
157
malidp_setup_timings(struct malidp_priv * malidp,struct display_timing * timings)158 static void malidp_setup_timings(struct malidp_priv *malidp,
159 struct display_timing *timings)
160 {
161 u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
162 MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
163 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
164 MALIDP_SYNC_CONTROL);
165 val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
166 MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
167 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
168 MALIDP_H_INTERVALS);
169 val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
170 MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
171 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
172 MALIDP_V_INTERVALS);
173 val = MALIDP_H_ACTIVE(timings->hactive.typ) |
174 MALIDP_V_ACTIVE(timings->vactive.typ);
175 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
176 MALIDP_HV_ACTIVESIZE);
177 /* default output bit-depth per colour is 8 bits */
178 writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
179 MALIDP_OUTPUT_DEPTH);
180 }
181
malidp_setup_mode(struct malidp_priv * malidp,struct display_timing * timings)182 static int malidp_setup_mode(struct malidp_priv *malidp,
183 struct display_timing *timings)
184 {
185 int err;
186
187 if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
188 return -EIO;
189
190 malidp_setup_timings(malidp, timings);
191
192 err = display_enable(malidp->display, 8, timings);
193 if (err)
194 printf("display_enable failed with %d\n", err);
195
196 return err;
197 }
198
malidp_setup_layer(struct malidp_priv * malidp,struct display_timing * timings,u32 layer_offset,phys_addr_t fb_addr)199 static void malidp_setup_layer(struct malidp_priv *malidp,
200 struct display_timing *timings,
201 u32 layer_offset, phys_addr_t fb_addr)
202 {
203 u32 val;
204
205 /* setup the base layer's pixel format to A8R8G8B8 */
206 writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
207 MALIDP_LAYER_FORMAT);
208 /* setup layer composition size */
209 val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
210 MALIDP_CMP_H_SIZE(timings->hactive.typ);
211 writel(val, malidp->base_addr + layer_offset +
212 MALIDP_LAYER_CMP_SIZE);
213 /* setup layer input size */
214 val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
215 MALIDP_IN_H_SIZE(timings->hactive.typ);
216 writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
217 /* setup layer stride in bytes */
218 writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
219 MALIDP_LAYER_STRIDE);
220 /* set framebuffer address */
221 writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
222 MALIDP_LAYER_PTR_LOW);
223 writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
224 MALIDP_LAYER_PTR_HIGH);
225 /* enable layer */
226 setbits_le32(malidp->base_addr + layer_offset +
227 MALIDP_LAYER_CONTROL, 1);
228 }
229
malidp_set_configvalid(struct malidp_priv * malidp)230 static void malidp_set_configvalid(struct malidp_priv *malidp)
231 {
232 setbits_le32(malidp->cval_addr, 1);
233 }
234
malidp_update_timings_from_edid(struct udevice * dev,struct display_timing * timings)235 static int malidp_update_timings_from_edid(struct udevice *dev,
236 struct display_timing *timings)
237 {
238 #ifdef CONFIG_DISPLAY
239 struct malidp_priv *priv = dev_get_priv(dev);
240 struct udevice *disp_dev;
241 int err;
242
243 err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
244 if (err)
245 return err;
246
247 priv->display = disp_dev;
248
249 err = display_read_timing(disp_dev, timings);
250 if (err)
251 return err;
252
253 #endif
254 return 0;
255 }
256
malidp_probe(struct udevice * dev)257 static int malidp_probe(struct udevice *dev)
258 {
259 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
260 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
261 ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
262 struct malidp_priv *priv = dev_get_priv(dev);
263 struct display_timing timings;
264 phys_addr_t fb_base, fb_size;
265 const char *format;
266 u32 value;
267 int err;
268
269 if (!ofnode_valid(framebuffer))
270 return -EINVAL;
271
272 err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
273 if (err) {
274 dev_err(dev, "failed to get pixel clock\n");
275 return err;
276 }
277 err = clk_get_by_name(dev, "aclk", &priv->aclk);
278 if (err) {
279 dev_err(dev, "failed to get AXI clock\n");
280 goto fail_aclk;
281 }
282
283 err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
284 if (err) {
285 dev_err(dev, "failed to get any display timings\n");
286 goto fail_timings;
287 }
288
289 err = malidp_update_timings_from_edid(dev, &timings);
290 if (err) {
291 printf("malidp_update_timings_from_edid failed: %d\n", err);
292 goto fail_timings;
293 }
294
295 fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
296 if (fb_base != FDT_ADDR_T_NONE) {
297 uc_plat->base = fb_base;
298 uc_plat->size = fb_size;
299 } else {
300 printf("cannot get address size for framebuffer\n");
301 }
302
303 err = ofnode_read_u32(framebuffer, "width", &value);
304 if (err)
305 goto fail_timings;
306 uc_priv->xsize = (ushort)value;
307
308 err = ofnode_read_u32(framebuffer, "height", &value);
309 if (err)
310 goto fail_timings;
311 uc_priv->ysize = (ushort)value;
312
313 format = ofnode_read_string(framebuffer, "format");
314 if (!format) {
315 err = -EINVAL;
316 goto fail_timings;
317 } else if (!strncmp(format, "a8r8g8b8", 8)) {
318 uc_priv->bpix = VIDEO_BPP32;
319 }
320
321 uc_priv->rot = 0;
322 priv->base_addr = (phys_addr_t)dev_read_addr(dev);
323
324 clk_enable(&priv->pxlclk);
325 clk_enable(&priv->aclk);
326
327 value = malidp_get_hwid(priv->base_addr);
328 printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
329 (value >> 12) & 0xf, (value >> 8) & 0xf);
330
331 if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
332 /* DP500 is special */
333 priv->modeset_regs_offset = 0x28;
334 priv->dc_status_addr = priv->base_addr;
335 priv->dc_control_addr = priv->base_addr + 0xc;
336 priv->cval_addr = priv->base_addr + 0xf00;
337 priv->config_bit_shift = 17;
338 priv->clear_irq = 0;
339 } else {
340 priv->modeset_regs_offset = 0x30;
341 priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
342 priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
343 priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
344 priv->config_bit_shift = 16;
345 priv->clear_irq = MALIDP_REG_CLEARIRQ;
346 }
347
348 /* enter config mode */
349 err = malidp_enter_config(priv);
350 if (err)
351 return err;
352
353 /* disable interrupts */
354 writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
355 writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
356
357 err = malidp_setup_mode(priv, &timings);
358 if (err)
359 goto fail_timings;
360
361 malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
362 (phys_addr_t)uc_plat->base);
363
364 err = malidp_leave_config(priv);
365 if (err)
366 goto fail_timings;
367
368 malidp_set_configvalid(priv);
369
370 return 0;
371
372 fail_timings:
373 clk_free(&priv->aclk);
374 fail_aclk:
375 clk_free(&priv->pxlclk);
376
377 return err;
378 }
379
malidp_bind(struct udevice * dev)380 static int malidp_bind(struct udevice *dev)
381 {
382 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
383
384 /* choose max possible size: 2K x 2K, XRGB888 framebuffer */
385 uc_plat->size = 4 * 2048 * 2048;
386
387 return 0;
388 }
389
390 static const struct udevice_id malidp_ids[] = {
391 { .compatible = "arm,mali-dp500" },
392 { .compatible = "arm,mali-dp550" },
393 { .compatible = "arm,mali-dp650" },
394 { }
395 };
396
397 U_BOOT_DRIVER(mali_dp) = {
398 .name = "mali_dp",
399 .id = UCLASS_VIDEO,
400 .of_match = malidp_ids,
401 .bind = malidp_bind,
402 .probe = malidp_probe,
403 .priv_auto_alloc_size = sizeof(struct malidp_priv),
404 .ops = &malidp_ops,
405 };
406