1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * logicore_dp_tx_regif.h
4  *
5  * Register interface definition for XILINX LogiCore DisplayPort v6.1 TX
6  * (Source) based on Xilinx dp_v3_1 driver sources
7  *
8  * (C) Copyright 2016
9  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
10  */
11 
12 #ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__
13 #define __GDSYS_LOGICORE_DP_TX_REGIF_H__
14 
15 enum {
16 	/* link configuration field */
17 	REG_LINK_BW_SET =		0x000,
18 	REG_LANE_COUNT_SET =		0x004,
19 	REG_ENHANCED_FRAME_EN =		0x008,
20 	REG_TRAINING_PATTERN_SET =	0x00C,
21 	REG_LINK_QUAL_PATTERN_SET =	0x010,
22 	REG_SCRAMBLING_DISABLE =	0x014,
23 	REG_DOWNSPREAD_CTRL =		0x018,
24 	REG_SOFT_RESET =		0x01C,
25 };
26 
27 enum {
28 	/* core enables */
29 	REG_ENABLE =			0x080,
30 	REG_ENABLE_MAIN_STREAM =	0x084,
31 	REG_ENABLE_SEC_STREAM =		0x088,
32 	REG_FORCE_SCRAMBLER_RESET =	0x0C0,
33 	REG_MST_CONFIG =		0x0D0,
34 	REG_LINE_RESET_DISABLE =	0x0F0,
35 };
36 
37 enum {
38 	/* core ID */
39 	REG_VERSION =			0x0F8,
40 	REG_CORE_ID =			0x0FC,
41 };
42 
43 enum {
44 	/* AUX channel interface */
45 	REG_AUX_CMD =			0x100,
46 	REG_AUX_WRITE_FIFO =		0x104,
47 	REG_AUX_ADDRESS =		0x108,
48 	REG_AUX_CLK_DIVIDER =		0x10C,
49 	REG_USER_FIFO_OVERFLOW =	0x110,
50 	REG_INTERRUPT_SIG_STATE =	0x130,
51 	REG_AUX_REPLY_DATA =		0x134,
52 	REG_AUX_REPLY_CODE =		0x138,
53 	REG_AUX_REPLY_COUNT =		0x13C,
54 	REG_INTERRUPT_STATUS =		0x140,
55 	REG_INTERRUPT_MASK =		0x144,
56 	REG_REPLY_DATA_COUNT =		0x148,
57 	REG_REPLY_STATUS =		0x14C,
58 	REG_HPD_DURATION =		0x150,
59 };
60 
61 enum {
62 	/* main stream attributes for SST / MST STREAM1 */
63 	REG_STREAM1_MSA_START =		0x180,
64 	REG_MAIN_STREAM_HTOTAL =	0x180,
65 	REG_MAIN_STREAM_VTOTAL =	0x184,
66 	REG_MAIN_STREAM_POLARITY =	0x188,
67 	REG_MAIN_STREAM_HSWIDTH =	0x18C,
68 	REG_MAIN_STREAM_VSWIDTH =	0x190,
69 	REG_MAIN_STREAM_HRES =		0x194,
70 	REG_MAIN_STREAM_VRES =		0x198,
71 	REG_MAIN_STREAM_HSTART =	0x19C,
72 	REG_MAIN_STREAM_VSTART =	0x1A0,
73 	REG_MAIN_STREAM_MISC0 =		0x1A4,
74 	REG_MAIN_STREAM_MISC1 =		0x1A8,
75 	REG_M_VID =			0x1AC,
76 	REG_TU_SIZE =			0x1B0,
77 	REG_N_VID =			0x1B4,
78 	REG_USER_PIXEL_WIDTH =		0x1B8,
79 	REG_USER_DATA_COUNT_PER_LANE =	0x1BC,
80 	REG_MAIN_STREAM_INTERLACED =	0x1C0,
81 	REG_MIN_BYTES_PER_TU =		0x1C4,
82 	REG_FRAC_BYTES_PER_TU =		0x1C8,
83 	REG_INIT_WAIT =			0x1CC,
84 	REG_STREAM1 =			0x1D0,
85 	REG_STREAM2 =			0x1D4,
86 	REG_STREAM3 =			0x1D8,
87 	REG_STREAM4 =			0x1DC,
88 };
89 
90 enum {
91 	/* PHY configuration status */
92 	REG_PHY_CONFIG =		0x200,
93 	REG_PHY_VOLTAGE_DIFF_LANE_0 =	0x220,
94 	REG_PHY_VOLTAGE_DIFF_LANE_1 =	0x224,
95 	REG_PHY_VOLTAGE_DIFF_LANE_2 =	0x228,
96 	REG_PHY_VOLTAGE_DIFF_LANE_3 =	0x22C,
97 	REG_PHY_TRANSMIT_PRBS7 =	0x230,
98 	REG_PHY_CLOCK_SELECT =		0x234,
99 	REG_PHY_POWER_DOWN =		0x238,
100 	REG_PHY_PRECURSOR_LANE_0 =	0x23C,
101 	REG_PHY_PRECURSOR_LANE_1 =	0x240,
102 	REG_PHY_PRECURSOR_LANE_2 =	0x244,
103 	REG_PHY_PRECURSOR_LANE_3 =	0x248,
104 	REG_PHY_POSTCURSOR_LANE_0 =	0x24C,
105 	REG_PHY_POSTCURSOR_LANE_1 =	0x250,
106 	REG_PHY_POSTCURSOR_LANE_2 =	0x254,
107 	REG_PHY_POSTCURSOR_LANE_3 =	0x258,
108 	REG_PHY_STATUS =		0x280,
109 	REG_GT_DRP_COMMAND =		0x2A0,
110 	REG_GT_DRP_READ_DATA =		0x2A4,
111 	REG_GT_DRP_CHANNEL_STATUS =	0x2A8,
112 };
113 
114 enum {
115 	/* DisplayPort audio */
116 	REG_AUDIO_CONTROL =		0x300,
117 	REG_AUDIO_CHANNELS =		0x304,
118 	REG_AUDIO_INFO_DATA =		0x308,
119 	REG_AUDIO_MAUD =		0x328,
120 	REG_AUDIO_NAUD =		0x32C,
121 	REG_AUDIO_EXT_DATA =		0x330,
122 };
123 
124 enum {
125 	/* HDCP */
126 	REG_HDCP_ENABLE =		0x400,
127 };
128 
129 enum {
130 	/* main stream attributes for MST STREAM2, 3, and 4 */
131 	REG_STREAM2_MSA_START =		0x500,
132 	REG_STREAM3_MSA_START =		0x550,
133 	REG_STREAM4_MSA_START =		0x5A0,
134 
135 	REG_VC_PAYLOAD_BUFFER_ADDR =	0x800,
136 };
137 
138 enum {
139 	LINK_BW_SET_162GBPS = 0x06,
140 	LINK_BW_SET_270GBPS = 0x0A,
141 	LINK_BW_SET_540GBPS = 0x14,
142 };
143 
144 enum {
145 	LANE_COUNT_SET_1 = 0x1,
146 	LANE_COUNT_SET_2 = 0x2,
147 	LANE_COUNT_SET_4 = 0x4,
148 };
149 
150 enum {
151 	TRAINING_PATTERN_SET_OFF =	0x0,
152 	/* training pattern 1 used for clock recovery */
153 	TRAINING_PATTERN_SET_TP1 =	0x1,
154 	/* training pattern 2 used for channel equalization */
155 	TRAINING_PATTERN_SET_TP2 =	0x2,
156 	/*
157 	 * training pattern 3 used for channel equalization for cores with DP
158 	 * v1.2
159 	 */
160 	TRAINING_PATTERN_SET_TP3 =	0x3,
161 };
162 
163 enum {
164 	LINK_QUAL_PATTERN_SET_OFF =		0x0,
165 	/* D10.2 unscrambled test pattern transmitted */
166 	LINK_QUAL_PATTERN_SET_D102_TEST =	0x1,
167 	/* symbol error rate measurement pattern transmitted */
168 	LINK_QUAL_PATTERN_SET_SER_MES =		0x2,
169 	/* pseudo random bit sequence 7 transmitted */
170 	LINK_QUAL_PATTERN_SET_PRBS7 =		0x3,
171 };
172 
173 enum {
174 	SOFT_RESET_VIDEO_STREAM1_MASK =		0x00000001,
175 	SOFT_RESET_VIDEO_STREAM2_MASK =		0x00000002,
176 	SOFT_RESET_VIDEO_STREAM3_MASK =		0x00000004,
177 	SOFT_RESET_VIDEO_STREAM4_MASK =		0x00000008,
178 	SOFT_RESET_AUX_MASK =			0x00000080,
179 	SOFT_RESET_VIDEO_STREAM_ALL_MASK =	0x0000000F,
180 };
181 
182 enum {
183 	MST_CONFIG_MST_EN_MASK =	0x00000001,
184 };
185 
186 enum {
187 	LINE_RESET_DISABLE_MASK =	0x1,
188 };
189 
190 #define AUX_CMD_NBYTES_TRANSFER_MASK	0x0000000F
191 
192 #define AUX_CMD_SHIFT		8
193 #define AUX_CMD_MASK			0x00000F00
194 enum {
195 	AUX_CMD_I2C_WRITE =		0x0,
196 	AUX_CMD_I2C_READ =		0x1,
197 	AUX_CMD_I2C_WRITE_STATUS =	0x2,
198 	AUX_CMD_I2C_WRITE_MOT =		0x4,
199 	AUX_CMD_I2C_READ_MOT =		0x5,
200 	AUX_CMD_I2C_WRITE_STATUS_MOT =	0x6,
201 	AUX_CMD_WRITE =			0x8,
202 	AUX_CMD_READ =			0x9,
203 };
204 
205 #define AUX_CLK_DIVIDER_VAL_MASK		0x00FF
206 
207 #define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8
208 #define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00
209 
210 enum {
211 	INTERRUPT_SIG_STATE_HPD_STATE_MASK =		0x00000001,
212 	INTERRUPT_SIG_STATE_REQUEST_STATE_MASK =	0x00000002,
213 	INTERRUPT_SIG_STATE_REPLY_STATE_MASK =		0x00000004,
214 	INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK =	0x00000008,
215 };
216 
217 enum {
218 	AUX_REPLY_CODE_ACK =		0x0,
219 	AUX_REPLY_CODE_I2C_ACK =	0x0,
220 	AUX_REPLY_CODE_NACK =		0x1,
221 	AUX_REPLY_CODE_DEFER =		0x2,
222 	AUX_REPLY_CODE_I2C_NACK =	0x4,
223 	AUX_REPLY_CODE_I2C_DEFER =	0x8,
224 };
225 
226 enum {
227 	INTERRUPT_STATUS_HPD_IRQ_MASK =			0x00000001,
228 	INTERRUPT_STATUS_HPD_EVENT_MASK =		0x00000002,
229 	INTERRUPT_STATUS_REPLY_RECEIVED_MASK =		0x00000004,
230 	INTERRUPT_STATUS_REPLY_TIMEOUT_MASK =		0x00000008,
231 	INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK =	0x00000010,
232 	INTERRUPT_STATUS_EXT_PKT_TXD_MASK =		0x00000020,
233 };
234 
235 enum {
236 	INTERRUPT_MASK_HPD_IRQ_MASK =			0x00000001,
237 	INTERRUPT_MASK_HPD_EVENT_MASK =			0x00000002,
238 	INTERRUPT_MASK_REPLY_RECEIVED_MASK =		0x00000004,
239 	INTERRUPT_MASK_REPLY_TIMEOUT_MASK =		0x00000008,
240 	INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK =	0x00000010,
241 	INTERRUPT_MASK_EXT_PKT_TXD_MASK =		0x00000020,
242 };
243 
244 #define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4
245 #define REPLY_STATUS_REPLY_STATUS_STATE_MASK	0x00000FF0
246 enum {
247 	REPLY_STATUS_REPLY_RECEIVED_MASK =	0x00000001,
248 	REPLY_STATUS_REPLY_IN_PROGRESS_MASK =	0x00000002,
249 	REPLY_STATUS_REQUEST_IN_PROGRESS_MASK =	0x00000004,
250 	REPLY_STATUS_REPLY_ERROR_MASK =		0x00000008,
251 };
252 
253 #define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1
254 enum {
255 	MAIN_STREAMX_POLARITY_HSYNC_POL_MASK =	0x00000001,
256 	MAIN_STREAMX_POLARITY_VSYNC_POL_MASK =	0x00000002,
257 };
258 
259 enum {
260 	MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001,
261 };
262 
263 #define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1
264 #define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006
265 enum {
266 	MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB =	0x0,
267 	MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 =	0x1,
268 	MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 =	0x2,
269 };
270 
271 #define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3
272 #define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008
273 
274 #define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4
275 #define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010
276 
277 #define MAIN_STREAMX_MISC0_BDC_SHIFT 5
278 #define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0
279 enum {
280 	MAIN_STREAMX_MISC0_BDC_6BPC =	0x0,
281 	MAIN_STREAMX_MISC0_BDC_8BPC =	0x1,
282 	MAIN_STREAMX_MISC0_BDC_10BPC =	0x2,
283 	MAIN_STREAMX_MISC0_BDC_12BPC =	0x3,
284 	MAIN_STREAMX_MISC0_BDC_16BPC =	0x4,
285 };
286 
287 enum {
288 	PHY_CONFIG_PHY_RESET_ENABLE_MASK =		0x0000000,
289 	PHY_CONFIG_PHY_RESET_MASK =			0x0000001,
290 	PHY_CONFIG_GTTX_RESET_MASK =			0x0000002,
291 	PHY_CONFIG_GT_ALL_RESET_MASK =			0x0000003,
292 	PHY_CONFIG_TX_PHY_PMA_RESET_MASK =		0x0000100,
293 	PHY_CONFIG_TX_PHY_PCS_RESET_MASK =		0x0000200,
294 	PHY_CONFIG_TX_PHY_POLARITY_MASK =		0x0000800,
295 	PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK =		0x0001000,
296 	PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK =	0x0010000,
297 	PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK =		0x0020000,
298 	PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK =		0x0040000,
299 	PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK =		0x0080000,
300 	PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK =		0x0100000,
301 	PHY_CONFIG_TX_PHY_8B10BEN_MASK =		0x0200000,
302 };
303 
304 #define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13
305 #define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000
306 
307 enum {
308 	PHY_CLOCK_SELECT_162GBPS =	0x1,
309 	PHY_CLOCK_SELECT_270GBPS =	0x3,
310 	PHY_CLOCK_SELECT_540GBPS =	0x5,
311 };
312 
313 enum {
314 	VS_LEVEL_0	= 0x2,
315 	VS_LEVEL_1	= 0x5,
316 	VS_LEVEL_2	= 0x8,
317 	VS_LEVEL_3	= 0xF,
318 	VS_LEVEL_OFFSET	= 0x4,
319 };
320 
321 enum {
322 	PE_LEVEL_0 =	0x00,
323 	PE_LEVEL_1 =	0x0E,
324 	PE_LEVEL_2 =	0x14,
325 	PE_LEVEL_3 =	0x1B,
326 };
327 
328 enum {
329 	PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT =		2,
330 	PHY_STATUS_TX_ERROR_LANE_0_SHIFT =		18,
331 	PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT =	20,
332 	PHY_STATUS_TX_ERROR_LANE_1_SHIFT =		22,
333 	PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT =	16,
334 	PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT =	24,
335 	PHY_STATUS_TX_ERROR_LANE_2_SHIFT =		26,
336 	PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT =	28,
337 	PHY_STATUS_TX_ERROR_LANE_3_SHIFT =		30,
338 };
339 
340 enum {
341 	PHY_STATUS_RESET_LANE_0_DONE_MASK =		0x00000001,
342 	PHY_STATUS_RESET_LANE_1_DONE_MASK =		0x00000002,
343 	PHY_STATUS_RESET_LANE_2_3_DONE_MASK =		0x0000000C,
344 	PHY_STATUS_PLL_LANE0_1_LOCK_MASK =		0x00000010,
345 	PHY_STATUS_PLL_LANE2_3_LOCK_MASK =		0x00000020,
346 	PHY_STATUS_PLL_FABRIC_LOCK_MASK =		0x00000040,
347 	PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK =	0x00030000,
348 	PHY_STATUS_TX_ERROR_LANE_0_MASK =		0x000C0000,
349 	PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK =	0x00300000,
350 	PHY_STATUS_TX_ERROR_LANE_1_MASK =		0x00C00000,
351 	PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK =	0x03000000,
352 	PHY_STATUS_TX_ERROR_LANE_2_MASK =		0x0C000000,
353 	PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK =	0x30000000,
354 	PHY_STATUS_TX_ERROR_LANE_3_MASK =		0xC0000000,
355 };
356 
357 #define PHY_STATUS_LANE_0_READY_MASK \
358 	(PHY_STATUS_RESET_LANE_0_DONE_MASK | \
359 	PHY_STATUS_PLL_LANE0_1_LOCK_MASK)
360 #define PHY_STATUS_LANES_0_1_READY_MASK \
361 	(PHY_STATUS_LANE_0_READY_MASK | \
362 	PHY_STATUS_RESET_LANE_1_DONE_MASK)
363 /*
364  * PHY_STATUS_ALL_LANES_READY_MASK seems to be missing lanes 0 and 1 in
365  * Xilinx dp_v3_0 implementation
366  */
367 #define PHY_STATUS_ALL_LANES_READY_MASK \
368 	(PHY_STATUS_LANES_0_1_READY_MASK | \
369 	PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \
370 	PHY_STATUS_PLL_LANE2_3_LOCK_MASK)
371 
372 /**
373  * phy_status_lanes_ready_mask() - Generate phy status ready mask
374  * @lane_count: Number of lanes for which to generate a mask
375  *
376  * Return: The generated phy status ready mask
377  */
378 static inline u32 phy_status_lanes_ready_mask(u8 lane_count)
379 {
380 	if (lane_count > 2)
381 		return PHY_STATUS_ALL_LANES_READY_MASK;
382 
383 	if (lane_count == 2)
384 		return PHY_STATUS_LANES_0_1_READY_MASK;
385 
386 	return PHY_STATUS_LANE_0_READY_MASK;
387 }
388 
389 #define GT_DRP_COMMAND_DRP_ADDR_MASK	0x000F
390 #define GT_DRP_COMMAND_DRP_RW_CMD_MASK	0x0080
391 #define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16
392 #define GT_DRP_COMMAND_DRP_W_DATA_MASK	0xFF00
393 
394 #define HDCP_ENABLE_BYPASS_DISABLE_MASK	0x0001
395 
396 #endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */
397