1 /* 2 * Porting to u-boot: 3 * 4 * (C) Copyright 2010 5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de 6 * 7 * Linux IPU driver for MX51: 8 * 9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 /* #define DEBUG */ 15 16 #include <common.h> 17 #include <linux/types.h> 18 #include <asm/errno.h> 19 #include <asm/io.h> 20 #include <asm/arch/imx-regs.h> 21 #include <asm/arch/sys_proto.h> 22 #include "ipu.h" 23 #include "ipu_regs.h" 24 25 enum csc_type_t { 26 RGB2YUV = 0, 27 YUV2RGB, 28 RGB2RGB, 29 YUV2YUV, 30 CSC_NONE, 31 CSC_NUM 32 }; 33 34 struct dp_csc_param_t { 35 int mode; 36 const int (*coeff)[5][3]; 37 }; 38 39 #define SYNC_WAVE 0 40 41 /* DC display ID assignments */ 42 #define DC_DISP_ID_SYNC(di) (di) 43 #define DC_DISP_ID_SERIAL 2 44 #define DC_DISP_ID_ASYNC 3 45 46 int dmfc_type_setup; 47 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; 48 int g_di1_tvout; 49 50 extern struct clk *g_ipu_clk; 51 extern struct clk *g_ldb_clk; 52 extern struct clk *g_di_clk[2]; 53 extern struct clk *g_pixel_clk[2]; 54 55 extern unsigned char g_ipu_clk_enabled; 56 extern unsigned char g_dc_di_assignment[]; 57 58 void ipu_dmfc_init(int dmfc_type, int first) 59 { 60 u32 dmfc_wr_chan, dmfc_dp_chan; 61 62 if (first) { 63 if (dmfc_type_setup > dmfc_type) 64 dmfc_type = dmfc_type_setup; 65 else 66 dmfc_type_setup = dmfc_type; 67 68 /* disable DMFC-IC channel*/ 69 __raw_writel(0x2, DMFC_IC_CTRL); 70 } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) { 71 printf("DMFC high resolution has set, will not change\n"); 72 return; 73 } else 74 dmfc_type_setup = dmfc_type; 75 76 if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) { 77 /* 1 - segment 0~3; 78 * 5B - segement 4, 5; 79 * 5F - segement 6, 7; 80 * 1C, 2C and 6B, 6F unused; 81 */ 82 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n"); 83 dmfc_wr_chan = 0x00000088; 84 dmfc_dp_chan = 0x00009694; 85 dmfc_size_28 = 256 * 4; 86 dmfc_size_29 = 0; 87 dmfc_size_24 = 0; 88 dmfc_size_27 = 128 * 4; 89 dmfc_size_23 = 128 * 4; 90 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) { 91 /* 1 - segment 0, 1; 92 * 5B - segement 2~5; 93 * 5F - segement 6,7; 94 * 1C, 2C and 6B, 6F unused; 95 */ 96 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n"); 97 dmfc_wr_chan = 0x00000090; 98 dmfc_dp_chan = 0x0000968a; 99 dmfc_size_28 = 128 * 4; 100 dmfc_size_29 = 0; 101 dmfc_size_24 = 0; 102 dmfc_size_27 = 128 * 4; 103 dmfc_size_23 = 256 * 4; 104 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) { 105 /* 5B - segement 0~3; 106 * 5F - segement 4~7; 107 * 1, 1C, 2C and 6B, 6F unused; 108 */ 109 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n"); 110 dmfc_wr_chan = 0x00000000; 111 dmfc_dp_chan = 0x00008c88; 112 dmfc_size_28 = 0; 113 dmfc_size_29 = 0; 114 dmfc_size_24 = 0; 115 dmfc_size_27 = 256 * 4; 116 dmfc_size_23 = 256 * 4; 117 } else { 118 /* 1 - segment 0, 1; 119 * 5B - segement 4, 5; 120 * 5F - segement 6, 7; 121 * 1C, 2C and 6B, 6F unused; 122 */ 123 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n"); 124 dmfc_wr_chan = 0x00000090; 125 dmfc_dp_chan = 0x00009694; 126 dmfc_size_28 = 128 * 4; 127 dmfc_size_29 = 0; 128 dmfc_size_24 = 0; 129 dmfc_size_27 = 128 * 4; 130 dmfc_size_23 = 128 * 4; 131 } 132 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); 133 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); 134 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); 135 /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ 136 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); 137 } 138 139 void ipu_dmfc_set_wait4eot(int dma_chan, int width) 140 { 141 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); 142 143 if (width >= HIGH_RESOLUTION_WIDTH) { 144 if (dma_chan == 23) 145 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0); 146 else if (dma_chan == 28) 147 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0); 148 } 149 150 if (dma_chan == 23) { /*5B*/ 151 if (dmfc_size_23 / width > 3) 152 dmfc_gen1 |= 1UL << 20; 153 else 154 dmfc_gen1 &= ~(1UL << 20); 155 } else if (dma_chan == 24) { /*6B*/ 156 if (dmfc_size_24 / width > 1) 157 dmfc_gen1 |= 1UL << 22; 158 else 159 dmfc_gen1 &= ~(1UL << 22); 160 } else if (dma_chan == 27) { /*5F*/ 161 if (dmfc_size_27 / width > 2) 162 dmfc_gen1 |= 1UL << 21; 163 else 164 dmfc_gen1 &= ~(1UL << 21); 165 } else if (dma_chan == 28) { /*1*/ 166 if (dmfc_size_28 / width > 2) 167 dmfc_gen1 |= 1UL << 16; 168 else 169 dmfc_gen1 &= ~(1UL << 16); 170 } else if (dma_chan == 29) { /*6F*/ 171 if (dmfc_size_29 / width > 1) 172 dmfc_gen1 |= 1UL << 23; 173 else 174 dmfc_gen1 &= ~(1UL << 23); 175 } 176 177 __raw_writel(dmfc_gen1, DMFC_GENERAL1); 178 } 179 180 static void ipu_di_data_wave_config(int di, 181 int wave_gen, 182 int access_size, int component_size) 183 { 184 u32 reg; 185 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | 186 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); 187 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); 188 } 189 190 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, 191 int up, int down) 192 { 193 u32 reg; 194 195 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); 196 reg &= ~(0x3 << (di_pin * 2)); 197 reg |= set << (di_pin * 2); 198 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); 199 200 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); 201 } 202 203 static void ipu_di_sync_config(int di, int wave_gen, 204 int run_count, int run_src, 205 int offset_count, int offset_src, 206 int repeat_count, int cnt_clr_src, 207 int cnt_polarity_gen_en, 208 int cnt_polarity_clr_src, 209 int cnt_polarity_trigger_src, 210 int cnt_up, int cnt_down) 211 { 212 u32 reg; 213 214 if ((run_count >= 0x1000) || (offset_count >= 0x1000) || 215 (repeat_count >= 0x1000) || 216 (cnt_up >= 0x400) || (cnt_down >= 0x400)) { 217 printf("DI%d counters out of range.\n", di); 218 return; 219 } 220 221 reg = (run_count << 19) | (++run_src << 16) | 222 (offset_count << 3) | ++offset_src; 223 __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); 224 reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | 225 (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); 226 reg |= (cnt_down << 16) | cnt_up; 227 if (repeat_count == 0) { 228 /* Enable auto reload */ 229 reg |= 0x10000000; 230 } 231 __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); 232 reg = __raw_readl(DI_STP_REP(di, wave_gen)); 233 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); 234 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); 235 __raw_writel(reg, DI_STP_REP(di, wave_gen)); 236 } 237 238 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask) 239 { 240 int ptr = map * 3 + byte_num; 241 u32 reg; 242 243 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); 244 reg &= ~(0xFFFF << (16 * (ptr & 0x1))); 245 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); 246 __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); 247 248 reg = __raw_readl(DC_MAP_CONF_PTR(map)); 249 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); 250 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); 251 __raw_writel(reg, DC_MAP_CONF_PTR(map)); 252 } 253 254 static void ipu_dc_map_clear(int map) 255 { 256 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); 257 __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), 258 DC_MAP_CONF_PTR(map)); 259 } 260 261 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, 262 int wave, int glue, int sync) 263 { 264 u32 reg; 265 int stop = 1; 266 267 reg = sync; 268 reg |= (glue << 4); 269 reg |= (++wave << 11); 270 reg |= (++map << 15); 271 reg |= (operand << 20) & 0xFFF00000; 272 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); 273 274 reg = (operand >> 12); 275 reg |= opcode << 4; 276 reg |= (stop << 9); 277 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); 278 } 279 280 static void ipu_dc_link_event(int chan, int event, int addr, int priority) 281 { 282 u32 reg; 283 284 reg = __raw_readl(DC_RL_CH(chan, event)); 285 reg &= ~(0xFFFF << (16 * (event & 0x1))); 286 reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); 287 __raw_writel(reg, DC_RL_CH(chan, event)); 288 } 289 290 /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250; 291 * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.; 292 * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.; 293 */ 294 static const int rgb2ycbcr_coeff[5][3] = { 295 {0x4D, 0x96, 0x1D}, 296 {0x3D5, 0x3AB, 0x80}, 297 {0x80, 0x395, 0x3EB}, 298 {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ 299 {0x2, 0x2, 0x2}, /* S0, S1, S2 */ 300 }; 301 302 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); 303 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); 304 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); 305 */ 306 static const int ycbcr2rgb_coeff[5][3] = { 307 {0x095, 0x000, 0x0CC}, 308 {0x095, 0x3CE, 0x398}, 309 {0x095, 0x0FF, 0x000}, 310 {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ 311 {0x1, 0x1, 0x1}, /*S0,S1,S2 */ 312 }; 313 314 #define mask_a(a) ((u32)(a) & 0x3FF) 315 #define mask_b(b) ((u32)(b) & 0x3FFF) 316 317 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */ 318 static int rgb_to_yuv(int n, int red, int green, int blue) 319 { 320 int c; 321 c = red * rgb2ycbcr_coeff[n][0]; 322 c += green * rgb2ycbcr_coeff[n][1]; 323 c += blue * rgb2ycbcr_coeff[n][2]; 324 c /= 16; 325 c += rgb2ycbcr_coeff[3][n] * 4; 326 c += 8; 327 c /= 16; 328 if (c < 0) 329 c = 0; 330 if (c > 255) 331 c = 255; 332 return c; 333 } 334 335 /* 336 * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE 337 * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE 338 */ 339 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { 340 { 341 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, 342 {0, 0}, 343 {0, 0}, 344 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, 345 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} 346 }, 347 { 348 {0, 0}, 349 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, 350 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, 351 {0, 0}, 352 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} 353 }, 354 { 355 {0, 0}, 356 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, 357 {0, 0}, 358 {0, 0}, 359 {0, 0} 360 }, 361 { 362 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, 363 {0, 0}, 364 {0, 0}, 365 {0, 0}, 366 {0, 0} 367 }, 368 { 369 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, 370 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, 371 {0, 0}, 372 {0, 0}, 373 {0, 0} 374 } 375 }; 376 377 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; 378 static int color_key_4rgb = 1; 379 380 void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, 381 unsigned char srm_mode_update) 382 { 383 u32 reg; 384 const int (*coeff)[5][3]; 385 386 if (dp_csc_param.mode >= 0) { 387 reg = __raw_readl(DP_COM_CONF()); 388 reg &= ~DP_COM_CONF_CSC_DEF_MASK; 389 reg |= dp_csc_param.mode; 390 __raw_writel(reg, DP_COM_CONF()); 391 } 392 393 coeff = dp_csc_param.coeff; 394 395 if (coeff) { 396 __raw_writel(mask_a((*coeff)[0][0]) | 397 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0()); 398 __raw_writel(mask_a((*coeff)[0][2]) | 399 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1()); 400 __raw_writel(mask_a((*coeff)[1][1]) | 401 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2()); 402 __raw_writel(mask_a((*coeff)[2][0]) | 403 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3()); 404 __raw_writel(mask_a((*coeff)[2][2]) | 405 (mask_b((*coeff)[3][0]) << 16) | 406 ((*coeff)[4][0] << 30), DP_CSC_0()); 407 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | 408 (mask_b((*coeff)[3][2]) << 16) | 409 ((*coeff)[4][2] << 30), DP_CSC_1()); 410 } 411 412 if (srm_mode_update) { 413 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; 414 __raw_writel(reg, IPU_SRM_PRI2); 415 } 416 } 417 418 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, 419 uint32_t out_pixel_fmt) 420 { 421 int in_fmt, out_fmt; 422 int dp; 423 int partial = 0; 424 uint32_t reg; 425 426 if (channel == MEM_FG_SYNC) { 427 dp = DP_SYNC; 428 partial = 1; 429 } else if (channel == MEM_BG_SYNC) { 430 dp = DP_SYNC; 431 partial = 0; 432 } else if (channel == MEM_BG_ASYNC0) { 433 dp = DP_ASYNC0; 434 partial = 0; 435 } else { 436 return -EINVAL; 437 } 438 439 in_fmt = format_to_colorspace(in_pixel_fmt); 440 out_fmt = format_to_colorspace(out_pixel_fmt); 441 442 if (partial) { 443 if (in_fmt == RGB) { 444 if (out_fmt == RGB) 445 fg_csc_type = RGB2RGB; 446 else 447 fg_csc_type = RGB2YUV; 448 } else { 449 if (out_fmt == RGB) 450 fg_csc_type = YUV2RGB; 451 else 452 fg_csc_type = YUV2YUV; 453 } 454 } else { 455 if (in_fmt == RGB) { 456 if (out_fmt == RGB) 457 bg_csc_type = RGB2RGB; 458 else 459 bg_csc_type = RGB2YUV; 460 } else { 461 if (out_fmt == RGB) 462 bg_csc_type = YUV2RGB; 463 else 464 bg_csc_type = YUV2YUV; 465 } 466 } 467 468 /* Transform color key from rgb to yuv if CSC is enabled */ 469 reg = __raw_readl(DP_COM_CONF()); 470 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && 471 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || 472 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || 473 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || 474 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) { 475 int red, green, blue; 476 int y, u, v; 477 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) & 478 0xFFFFFFL; 479 480 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n", 481 color_key); 482 483 red = (color_key >> 16) & 0xFF; 484 green = (color_key >> 8) & 0xFF; 485 blue = color_key & 0xFF; 486 487 y = rgb_to_yuv(0, red, green, blue); 488 u = rgb_to_yuv(1, red, green, blue); 489 v = rgb_to_yuv(2, red, green, blue); 490 color_key = (y << 16) | (u << 8) | v; 491 492 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; 493 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); 494 color_key_4rgb = 0; 495 496 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n", 497 color_key); 498 } 499 500 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1); 501 502 return 0; 503 } 504 505 void ipu_dp_uninit(ipu_channel_t channel) 506 { 507 int dp; 508 int partial = 0; 509 510 if (channel == MEM_FG_SYNC) { 511 dp = DP_SYNC; 512 partial = 1; 513 } else if (channel == MEM_BG_SYNC) { 514 dp = DP_SYNC; 515 partial = 0; 516 } else if (channel == MEM_BG_ASYNC0) { 517 dp = DP_ASYNC0; 518 partial = 0; 519 } else { 520 return; 521 } 522 523 if (partial) 524 fg_csc_type = CSC_NONE; 525 else 526 bg_csc_type = CSC_NONE; 527 528 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0); 529 } 530 531 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced) 532 { 533 u32 reg = 0; 534 535 if ((dc_chan == 1) || (dc_chan == 5)) { 536 if (interlaced) { 537 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); 538 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); 539 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); 540 } else { 541 if (di) { 542 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); 543 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); 544 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 545 4, 1); 546 } else { 547 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); 548 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); 549 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 550 7, 1); 551 } 552 } 553 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); 554 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); 555 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); 556 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); 557 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); 558 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); 559 560 reg = 0x2; 561 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; 562 reg |= di << 2; 563 if (interlaced) 564 reg |= DC_WR_CH_CONF_FIELD_MODE; 565 } else if ((dc_chan == 8) || (dc_chan == 9)) { 566 /* async channels */ 567 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); 568 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); 569 570 reg = 0x3; 571 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; 572 } 573 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); 574 575 __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); 576 577 __raw_writel(0x00000084, DC_GEN); 578 } 579 580 void ipu_dc_uninit(int dc_chan) 581 { 582 if ((dc_chan == 1) || (dc_chan == 5)) { 583 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); 584 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); 585 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); 586 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); 587 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); 588 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); 589 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); 590 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); 591 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); 592 } else if ((dc_chan == 8) || (dc_chan == 9)) { 593 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); 594 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); 595 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); 596 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); 597 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); 598 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); 599 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); 600 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); 601 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); 602 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); 603 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); 604 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); 605 } 606 } 607 608 int ipu_chan_is_interlaced(ipu_channel_t channel) 609 { 610 if (channel == MEM_DC_SYNC) 611 return !!(__raw_readl(DC_WR_CH_CONF_1) & 612 DC_WR_CH_CONF_FIELD_MODE); 613 else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) 614 return !!(__raw_readl(DC_WR_CH_CONF_5) & 615 DC_WR_CH_CONF_FIELD_MODE); 616 return 0; 617 } 618 619 void ipu_dp_dc_enable(ipu_channel_t channel) 620 { 621 int di; 622 uint32_t reg; 623 uint32_t dc_chan; 624 625 if (channel == MEM_FG_SYNC) 626 dc_chan = 5; 627 if (channel == MEM_DC_SYNC) 628 dc_chan = 1; 629 else if (channel == MEM_BG_SYNC) 630 dc_chan = 5; 631 else 632 return; 633 634 if (channel == MEM_FG_SYNC) { 635 /* Enable FG channel */ 636 reg = __raw_readl(DP_COM_CONF()); 637 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF()); 638 639 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; 640 __raw_writel(reg, IPU_SRM_PRI2); 641 return; 642 } 643 644 di = g_dc_di_assignment[dc_chan]; 645 646 /* Make sure other DC sync channel is not assigned same DI */ 647 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); 648 if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { 649 reg &= ~DC_WR_CH_CONF_PROG_DI_ID; 650 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; 651 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); 652 } 653 654 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); 655 reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; 656 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); 657 658 clk_enable(g_pixel_clk[di]); 659 } 660 661 static unsigned char dc_swap; 662 663 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) 664 { 665 uint32_t reg; 666 uint32_t csc; 667 uint32_t dc_chan = 0; 668 int timeout = 50; 669 int irq = 0; 670 671 dc_swap = swap; 672 673 if (channel == MEM_DC_SYNC) { 674 dc_chan = 1; 675 irq = IPU_IRQ_DC_FC_1; 676 } else if (channel == MEM_BG_SYNC) { 677 dc_chan = 5; 678 irq = IPU_IRQ_DP_SF_END; 679 } else if (channel == MEM_FG_SYNC) { 680 /* Disable FG channel */ 681 dc_chan = 5; 682 683 reg = __raw_readl(DP_COM_CONF()); 684 csc = reg & DP_COM_CONF_CSC_DEF_MASK; 685 if (csc == DP_COM_CONF_CSC_DEF_FG) 686 reg &= ~DP_COM_CONF_CSC_DEF_MASK; 687 688 reg &= ~DP_COM_CONF_FG_EN; 689 __raw_writel(reg, DP_COM_CONF()); 690 691 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; 692 __raw_writel(reg, IPU_SRM_PRI2); 693 694 timeout = 50; 695 696 /* 697 * Wait for DC triple buffer to empty, 698 * this check is useful for tv overlay. 699 */ 700 if (g_dc_di_assignment[dc_chan] == 0) 701 while ((__raw_readl(DC_STAT) & 0x00000002) 702 != 0x00000002) { 703 udelay(2000); 704 timeout -= 2; 705 if (timeout <= 0) 706 break; 707 } 708 else if (g_dc_di_assignment[dc_chan] == 1) 709 while ((__raw_readl(DC_STAT) & 0x00000020) 710 != 0x00000020) { 711 udelay(2000); 712 timeout -= 2; 713 if (timeout <= 0) 714 break; 715 } 716 return; 717 } else { 718 return; 719 } 720 721 if (dc_swap) { 722 /* Swap DC channel 1 and 5 settings, and disable old dc chan */ 723 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); 724 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); 725 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; 726 reg ^= DC_WR_CH_CONF_PROG_DI_ID; 727 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); 728 } else { 729 /* Make sure that we leave at the irq starting edge */ 730 __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); 731 do { 732 reg = __raw_readl(IPUIRQ_2_STATREG(irq)); 733 } while (!(reg & IPUIRQ_2_MASK(irq))); 734 735 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); 736 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; 737 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); 738 739 reg = __raw_readl(IPU_DISP_GEN); 740 if (g_dc_di_assignment[dc_chan]) 741 reg &= ~DI1_COUNTER_RELEASE; 742 else 743 reg &= ~DI0_COUNTER_RELEASE; 744 __raw_writel(reg, IPU_DISP_GEN); 745 746 /* Clock is already off because it must be done quickly, but 747 we need to fix the ref count */ 748 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); 749 } 750 } 751 752 void ipu_init_dc_mappings(void) 753 { 754 /* IPU_PIX_FMT_RGB24 */ 755 ipu_dc_map_clear(0); 756 ipu_dc_map_config(0, 0, 7, 0xFF); 757 ipu_dc_map_config(0, 1, 15, 0xFF); 758 ipu_dc_map_config(0, 2, 23, 0xFF); 759 760 /* IPU_PIX_FMT_RGB666 */ 761 ipu_dc_map_clear(1); 762 ipu_dc_map_config(1, 0, 5, 0xFC); 763 ipu_dc_map_config(1, 1, 11, 0xFC); 764 ipu_dc_map_config(1, 2, 17, 0xFC); 765 766 /* IPU_PIX_FMT_YUV444 */ 767 ipu_dc_map_clear(2); 768 ipu_dc_map_config(2, 0, 15, 0xFF); 769 ipu_dc_map_config(2, 1, 23, 0xFF); 770 ipu_dc_map_config(2, 2, 7, 0xFF); 771 772 /* IPU_PIX_FMT_RGB565 */ 773 ipu_dc_map_clear(3); 774 ipu_dc_map_config(3, 0, 4, 0xF8); 775 ipu_dc_map_config(3, 1, 10, 0xFC); 776 ipu_dc_map_config(3, 2, 15, 0xF8); 777 778 /* IPU_PIX_FMT_LVDS666 */ 779 ipu_dc_map_clear(4); 780 ipu_dc_map_config(4, 0, 5, 0xFC); 781 ipu_dc_map_config(4, 1, 13, 0xFC); 782 ipu_dc_map_config(4, 2, 21, 0xFC); 783 } 784 785 int ipu_pixfmt_to_map(uint32_t fmt) 786 { 787 switch (fmt) { 788 case IPU_PIX_FMT_GENERIC: 789 case IPU_PIX_FMT_RGB24: 790 return 0; 791 case IPU_PIX_FMT_RGB666: 792 return 1; 793 case IPU_PIX_FMT_YUV444: 794 return 2; 795 case IPU_PIX_FMT_RGB565: 796 return 3; 797 case IPU_PIX_FMT_LVDS666: 798 return 4; 799 } 800 801 return -1; 802 } 803 804 /* 805 * This function is called to adapt synchronous LCD panel to IPU restriction. 806 */ 807 void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, 808 uint16_t width, uint16_t height, 809 uint16_t h_start_width, 810 uint16_t h_end_width, 811 uint16_t v_start_width, 812 uint16_t *v_end_width) 813 { 814 if (*v_end_width < 2) { 815 uint16_t total_width = width + h_start_width + h_end_width; 816 uint16_t total_height_old = height + v_start_width + 817 (*v_end_width); 818 uint16_t total_height_new = height + v_start_width + 2; 819 *v_end_width = 2; 820 *pixel_clk = (*pixel_clk) * total_width * total_height_new / 821 (total_width * total_height_old); 822 printf("WARNING: adapt panel end blank lines\n"); 823 } 824 } 825 826 /* 827 * This function is called to initialize a synchronous LCD panel. 828 * 829 * @param disp The DI the panel is attached to. 830 * 831 * @param pixel_clk Desired pixel clock frequency in Hz. 832 * 833 * @param pixel_fmt Input parameter for pixel format of buffer. 834 * Pixel format is a FOURCC ASCII code. 835 * 836 * @param width The width of panel in pixels. 837 * 838 * @param height The height of panel in pixels. 839 * 840 * @param hStartWidth The number of pixel clocks between the HSYNC 841 * signal pulse and the start of valid data. 842 * 843 * @param hSyncWidth The width of the HSYNC signal in units of pixel 844 * clocks. 845 * 846 * @param hEndWidth The number of pixel clocks between the end of 847 * valid data and the HSYNC signal for next line. 848 * 849 * @param vStartWidth The number of lines between the VSYNC 850 * signal pulse and the start of valid data. 851 * 852 * @param vSyncWidth The width of the VSYNC signal in units of lines 853 * 854 * @param vEndWidth The number of lines between the end of valid 855 * data and the VSYNC signal for next frame. 856 * 857 * @param sig Bitfield of signal polarities for LCD interface. 858 * 859 * @return This function returns 0 on success or negative error code on 860 * fail. 861 */ 862 863 int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, 864 uint16_t width, uint16_t height, 865 uint32_t pixel_fmt, 866 uint16_t h_start_width, uint16_t h_sync_width, 867 uint16_t h_end_width, uint16_t v_start_width, 868 uint16_t v_sync_width, uint16_t v_end_width, 869 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) 870 { 871 uint32_t reg; 872 uint32_t di_gen, vsync_cnt; 873 uint32_t div, rounded_pixel_clk; 874 uint32_t h_total, v_total; 875 int map; 876 struct clk *di_parent; 877 878 debug("panel size = %d x %d\n", width, height); 879 880 if ((v_sync_width == 0) || (h_sync_width == 0)) 881 return -EINVAL; 882 883 adapt_panel_to_ipu_restricitions(&pixel_clk, width, height, 884 h_start_width, h_end_width, 885 v_start_width, &v_end_width); 886 h_total = width + h_sync_width + h_start_width + h_end_width; 887 v_total = height + v_sync_width + v_start_width + v_end_width; 888 889 /* Init clocking */ 890 debug("pixel clk = %d\n", pixel_clk); 891 892 if (sig.ext_clk) { 893 if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ 894 /* 895 * Set the PLL to be an even multiple 896 * of the pixel clock. 897 */ 898 if ((clk_get_usecount(g_pixel_clk[0]) == 0) && 899 (clk_get_usecount(g_pixel_clk[1]) == 0)) { 900 di_parent = clk_get_parent(g_di_clk[disp]); 901 rounded_pixel_clk = 902 clk_round_rate(g_pixel_clk[disp], 903 pixel_clk); 904 div = clk_get_rate(di_parent) / 905 rounded_pixel_clk; 906 if (div % 2) 907 div++; 908 if (clk_get_rate(di_parent) != div * 909 rounded_pixel_clk) 910 clk_set_rate(di_parent, 911 div * rounded_pixel_clk); 912 udelay(10000); 913 clk_set_rate(g_di_clk[disp], 914 2 * rounded_pixel_clk); 915 udelay(10000); 916 } 917 } 918 clk_set_parent(g_pixel_clk[disp], g_ldb_clk); 919 } else { 920 if (clk_get_usecount(g_pixel_clk[disp]) != 0) 921 clk_set_parent(g_pixel_clk[disp], g_ipu_clk); 922 } 923 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); 924 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); 925 udelay(5000); 926 /* Get integer portion of divider */ 927 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / 928 rounded_pixel_clk; 929 930 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); 931 ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); 932 933 map = ipu_pixfmt_to_map(pixel_fmt); 934 if (map < 0) { 935 debug("IPU_DISP: No MAP\n"); 936 return -EINVAL; 937 } 938 939 di_gen = __raw_readl(DI_GENERAL(disp)); 940 941 if (sig.interlaced) { 942 /* Setup internal HSYNC waveform */ 943 ipu_di_sync_config( 944 disp, /* display */ 945 1, /* counter */ 946 h_total / 2 - 1,/* run count */ 947 DI_SYNC_CLK, /* run_resolution */ 948 0, /* offset */ 949 DI_SYNC_NONE, /* offset resolution */ 950 0, /* repeat count */ 951 DI_SYNC_NONE, /* CNT_CLR_SEL */ 952 0, /* CNT_POLARITY_GEN_EN */ 953 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 954 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 955 0, /* COUNT UP */ 956 0 /* COUNT DOWN */ 957 ); 958 959 /* Field 1 VSYNC waveform */ 960 ipu_di_sync_config( 961 disp, /* display */ 962 2, /* counter */ 963 h_total - 1, /* run count */ 964 DI_SYNC_CLK, /* run_resolution */ 965 0, /* offset */ 966 DI_SYNC_NONE, /* offset resolution */ 967 0, /* repeat count */ 968 DI_SYNC_NONE, /* CNT_CLR_SEL */ 969 0, /* CNT_POLARITY_GEN_EN */ 970 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 971 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 972 0, /* COUNT UP */ 973 4 /* COUNT DOWN */ 974 ); 975 976 /* Setup internal HSYNC waveform */ 977 ipu_di_sync_config( 978 disp, /* display */ 979 3, /* counter */ 980 v_total * 2 - 1,/* run count */ 981 DI_SYNC_INT_HSYNC, /* run_resolution */ 982 1, /* offset */ 983 DI_SYNC_INT_HSYNC, /* offset resolution */ 984 0, /* repeat count */ 985 DI_SYNC_NONE, /* CNT_CLR_SEL */ 986 0, /* CNT_POLARITY_GEN_EN */ 987 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 988 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 989 0, /* COUNT UP */ 990 4 /* COUNT DOWN */ 991 ); 992 993 /* Active Field ? */ 994 ipu_di_sync_config( 995 disp, /* display */ 996 4, /* counter */ 997 v_total / 2 - 1,/* run count */ 998 DI_SYNC_HSYNC, /* run_resolution */ 999 v_start_width, /* offset */ 1000 DI_SYNC_HSYNC, /* offset resolution */ 1001 2, /* repeat count */ 1002 DI_SYNC_VSYNC, /* CNT_CLR_SEL */ 1003 0, /* CNT_POLARITY_GEN_EN */ 1004 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1005 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1006 0, /* COUNT UP */ 1007 0 /* COUNT DOWN */ 1008 ); 1009 1010 /* Active Line */ 1011 ipu_di_sync_config( 1012 disp, /* display */ 1013 5, /* counter */ 1014 0, /* run count */ 1015 DI_SYNC_HSYNC, /* run_resolution */ 1016 0, /* offset */ 1017 DI_SYNC_NONE, /* offset resolution */ 1018 height / 2, /* repeat count */ 1019 4, /* CNT_CLR_SEL */ 1020 0, /* CNT_POLARITY_GEN_EN */ 1021 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1022 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1023 0, /* COUNT UP */ 1024 0 /* COUNT DOWN */ 1025 ); 1026 1027 /* Field 0 VSYNC waveform */ 1028 ipu_di_sync_config( 1029 disp, /* display */ 1030 6, /* counter */ 1031 v_total - 1, /* run count */ 1032 DI_SYNC_HSYNC, /* run_resolution */ 1033 0, /* offset */ 1034 DI_SYNC_NONE, /* offset resolution */ 1035 0, /* repeat count */ 1036 DI_SYNC_NONE, /* CNT_CLR_SEL */ 1037 0, /* CNT_POLARITY_GEN_EN */ 1038 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1039 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1040 0, /* COUNT UP */ 1041 0 /* COUNT DOWN */ 1042 ); 1043 1044 /* DC VSYNC waveform */ 1045 vsync_cnt = 7; 1046 ipu_di_sync_config( 1047 disp, /* display */ 1048 7, /* counter */ 1049 v_total / 2 - 1,/* run count */ 1050 DI_SYNC_HSYNC, /* run_resolution */ 1051 9, /* offset */ 1052 DI_SYNC_HSYNC, /* offset resolution */ 1053 2, /* repeat count */ 1054 DI_SYNC_VSYNC, /* CNT_CLR_SEL */ 1055 0, /* CNT_POLARITY_GEN_EN */ 1056 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1057 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1058 0, /* COUNT UP */ 1059 0 /* COUNT DOWN */ 1060 ); 1061 1062 /* active pixel waveform */ 1063 ipu_di_sync_config( 1064 disp, /* display */ 1065 8, /* counter */ 1066 0, /* run count */ 1067 DI_SYNC_CLK, /* run_resolution */ 1068 h_start_width, /* offset */ 1069 DI_SYNC_CLK, /* offset resolution */ 1070 width, /* repeat count */ 1071 5, /* CNT_CLR_SEL */ 1072 0, /* CNT_POLARITY_GEN_EN */ 1073 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1074 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1075 0, /* COUNT UP */ 1076 0 /* COUNT DOWN */ 1077 ); 1078 1079 ipu_di_sync_config( 1080 disp, /* display */ 1081 9, /* counter */ 1082 v_total - 1, /* run count */ 1083 DI_SYNC_INT_HSYNC,/* run_resolution */ 1084 v_total / 2, /* offset */ 1085 DI_SYNC_INT_HSYNC,/* offset resolution */ 1086 0, /* repeat count */ 1087 DI_SYNC_HSYNC, /* CNT_CLR_SEL */ 1088 0, /* CNT_POLARITY_GEN_EN */ 1089 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ 1090 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ 1091 0, /* COUNT UP */ 1092 4 /* COUNT DOWN */ 1093 ); 1094 1095 /* set gentime select and tag sel */ 1096 reg = __raw_readl(DI_SW_GEN1(disp, 9)); 1097 reg &= 0x1FFFFFFF; 1098 reg |= (3 - 1)<<29 | 0x00008000; 1099 __raw_writel(reg, DI_SW_GEN1(disp, 9)); 1100 1101 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); 1102 1103 /* set y_sel = 1 */ 1104 di_gen |= 0x10000000; 1105 di_gen |= DI_GEN_POLARITY_5; 1106 di_gen |= DI_GEN_POLARITY_8; 1107 } else { 1108 /* Setup internal HSYNC waveform */ 1109 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, 1110 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 1111 0, DI_SYNC_NONE, 1112 DI_SYNC_NONE, 0, 0); 1113 1114 /* Setup external (delayed) HSYNC waveform */ 1115 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, 1116 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, 1117 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, 1118 DI_SYNC_CLK, 0, h_sync_width * 2); 1119 /* Setup VSYNC waveform */ 1120 vsync_cnt = DI_SYNC_VSYNC; 1121 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, 1122 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, 1123 DI_SYNC_NONE, 1, DI_SYNC_NONE, 1124 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); 1125 __raw_writel(v_total - 1, DI_SCR_CONF(disp)); 1126 1127 /* Setup active data waveform to sync with DC */ 1128 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, 1129 v_sync_width + v_start_width, DI_SYNC_HSYNC, 1130 height, 1131 DI_SYNC_VSYNC, 0, DI_SYNC_NONE, 1132 DI_SYNC_NONE, 0, 0); 1133 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, 1134 h_sync_width + h_start_width, DI_SYNC_CLK, 1135 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 1136 0); 1137 1138 /* reset all unused counters */ 1139 __raw_writel(0, DI_SW_GEN0(disp, 6)); 1140 __raw_writel(0, DI_SW_GEN1(disp, 6)); 1141 __raw_writel(0, DI_SW_GEN0(disp, 7)); 1142 __raw_writel(0, DI_SW_GEN1(disp, 7)); 1143 __raw_writel(0, DI_SW_GEN0(disp, 8)); 1144 __raw_writel(0, DI_SW_GEN1(disp, 8)); 1145 __raw_writel(0, DI_SW_GEN0(disp, 9)); 1146 __raw_writel(0, DI_SW_GEN1(disp, 9)); 1147 1148 reg = __raw_readl(DI_STP_REP(disp, 6)); 1149 reg &= 0x0000FFFF; 1150 __raw_writel(reg, DI_STP_REP(disp, 6)); 1151 __raw_writel(0, DI_STP_REP(disp, 7)); 1152 __raw_writel(0, DI_STP_REP(disp, 9)); 1153 1154 /* Init template microcode */ 1155 if (disp) { 1156 ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); 1157 ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); 1158 ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); 1159 } else { 1160 ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); 1161 ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); 1162 ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); 1163 } 1164 1165 if (sig.Hsync_pol) 1166 di_gen |= DI_GEN_POLARITY_2; 1167 if (sig.Vsync_pol) 1168 di_gen |= DI_GEN_POLARITY_3; 1169 1170 if (!sig.clk_pol) 1171 di_gen |= DI_GEN_POL_CLK; 1172 1173 } 1174 1175 __raw_writel(di_gen, DI_GENERAL(disp)); 1176 1177 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 1178 0x00000002, DI_SYNC_AS_GEN(disp)); 1179 1180 reg = __raw_readl(DI_POL(disp)); 1181 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); 1182 if (sig.enable_pol) 1183 reg |= DI_POL_DRDY_POLARITY_15; 1184 if (sig.data_pol) 1185 reg |= DI_POL_DRDY_DATA_POLARITY; 1186 __raw_writel(reg, DI_POL(disp)); 1187 1188 __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); 1189 1190 return 0; 1191 } 1192 1193 /* 1194 * This function sets the foreground and background plane global alpha blending 1195 * modes. This function also sets the DP graphic plane according to the 1196 * parameter of IPUv3 DP channel. 1197 * 1198 * @param channel IPUv3 DP channel 1199 * 1200 * @param enable Boolean to enable or disable global alpha 1201 * blending. If disabled, local blending is used. 1202 * 1203 * @param alpha Global alpha value. 1204 * 1205 * @return Returns 0 on success or negative error code on fail 1206 */ 1207 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, 1208 uint8_t alpha) 1209 { 1210 uint32_t reg; 1211 1212 unsigned char bg_chan; 1213 1214 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || 1215 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || 1216 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) 1217 return -EINVAL; 1218 1219 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || 1220 channel == MEM_BG_ASYNC1) 1221 bg_chan = 1; 1222 else 1223 bg_chan = 0; 1224 1225 if (!g_ipu_clk_enabled) 1226 clk_enable(g_ipu_clk); 1227 1228 if (bg_chan) { 1229 reg = __raw_readl(DP_COM_CONF()); 1230 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF()); 1231 } else { 1232 reg = __raw_readl(DP_COM_CONF()); 1233 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF()); 1234 } 1235 1236 if (enable) { 1237 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL; 1238 __raw_writel(reg | ((uint32_t) alpha << 24), 1239 DP_GRAPH_WIND_CTRL()); 1240 1241 reg = __raw_readl(DP_COM_CONF()); 1242 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF()); 1243 } else { 1244 reg = __raw_readl(DP_COM_CONF()); 1245 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF()); 1246 } 1247 1248 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; 1249 __raw_writel(reg, IPU_SRM_PRI2); 1250 1251 if (!g_ipu_clk_enabled) 1252 clk_disable(g_ipu_clk); 1253 1254 return 0; 1255 } 1256 1257 /* 1258 * This function sets the transparent color key for SDC graphic plane. 1259 * 1260 * @param channel Input parameter for the logical channel ID. 1261 * 1262 * @param enable Boolean to enable or disable color key 1263 * 1264 * @param colorKey 24-bit RGB color for transparent color key. 1265 * 1266 * @return Returns 0 on success or negative error code on fail 1267 */ 1268 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, 1269 uint32_t color_key) 1270 { 1271 uint32_t reg; 1272 int y, u, v; 1273 int red, green, blue; 1274 1275 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || 1276 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || 1277 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) 1278 return -EINVAL; 1279 1280 if (!g_ipu_clk_enabled) 1281 clk_enable(g_ipu_clk); 1282 1283 color_key_4rgb = 1; 1284 /* Transform color key from rgb to yuv if CSC is enabled */ 1285 if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || 1286 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || 1287 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || 1288 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) { 1289 1290 debug("color key 0x%x need change to yuv fmt\n", color_key); 1291 1292 red = (color_key >> 16) & 0xFF; 1293 green = (color_key >> 8) & 0xFF; 1294 blue = color_key & 0xFF; 1295 1296 y = rgb_to_yuv(0, red, green, blue); 1297 u = rgb_to_yuv(1, red, green, blue); 1298 v = rgb_to_yuv(2, red, green, blue); 1299 color_key = (y << 16) | (u << 8) | v; 1300 1301 color_key_4rgb = 0; 1302 1303 debug("color key change to yuv fmt 0x%x\n", color_key); 1304 } 1305 1306 if (enable) { 1307 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; 1308 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); 1309 1310 reg = __raw_readl(DP_COM_CONF()); 1311 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF()); 1312 } else { 1313 reg = __raw_readl(DP_COM_CONF()); 1314 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF()); 1315 } 1316 1317 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; 1318 __raw_writel(reg, IPU_SRM_PRI2); 1319 1320 if (!g_ipu_clk_enabled) 1321 clk_disable(g_ipu_clk); 1322 1323 return 0; 1324 } 1325