1 /* 2 * Porting to u-boot: 3 * 4 * (C) Copyright 2010 5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de 6 * 7 * Linux IPU driver for MX51: 8 * 9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 /* #define DEBUG */ 15 #include <common.h> 16 #include <linux/types.h> 17 #include <linux/err.h> 18 #include <asm/io.h> 19 #include <asm/errno.h> 20 #include <asm/arch/imx-regs.h> 21 #include <asm/arch/crm_regs.h> 22 #include <div64.h> 23 #include "ipu.h" 24 #include "ipu_regs.h" 25 26 extern struct mxc_ccm_reg *mxc_ccm; 27 extern u32 *ipu_cpmem_base; 28 29 struct ipu_ch_param_word { 30 uint32_t data[5]; 31 uint32_t res[3]; 32 }; 33 34 struct ipu_ch_param { 35 struct ipu_ch_param_word word[2]; 36 }; 37 38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) 39 40 #define _param_word(base, w) \ 41 (((struct ipu_ch_param *)(base))->word[(w)].data) 42 43 #define ipu_ch_param_set_field(base, w, bit, size, v) { \ 44 int i = (bit) / 32; \ 45 int off = (bit) % 32; \ 46 _param_word(base, w)[i] |= (v) << off; \ 47 if (((bit) + (size) - 1) / 32 > i) { \ 48 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ 49 } \ 50 } 51 52 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \ 53 int i = (bit) / 32; \ 54 int off = (bit) % 32; \ 55 u32 mask = (1UL << size) - 1; \ 56 u32 temp = _param_word(base, w)[i]; \ 57 temp &= ~(mask << off); \ 58 _param_word(base, w)[i] = temp | (v) << off; \ 59 if (((bit) + (size) - 1) / 32 > i) { \ 60 temp = _param_word(base, w)[i + 1]; \ 61 temp &= ~(mask >> (32 - off)); \ 62 _param_word(base, w)[i + 1] = \ 63 temp | ((v) >> (off ? (32 - off) : 0)); \ 64 } \ 65 } 66 67 #define ipu_ch_param_read_field(base, w, bit, size) ({ \ 68 u32 temp2; \ 69 int i = (bit) / 32; \ 70 int off = (bit) % 32; \ 71 u32 mask = (1UL << size) - 1; \ 72 u32 temp1 = _param_word(base, w)[i]; \ 73 temp1 = mask & (temp1 >> off); \ 74 if (((bit)+(size) - 1) / 32 > i) { \ 75 temp2 = _param_word(base, w)[i + 1]; \ 76 temp2 &= mask >> (off ? (32 - off) : 0); \ 77 temp1 |= temp2 << (off ? (32 - off) : 0); \ 78 } \ 79 temp1; \ 80 }) 81 82 #define IPU_SW_RST_TOUT_USEC (10000) 83 84 void clk_enable(struct clk *clk) 85 { 86 if (clk) { 87 if (clk->usecount++ == 0) { 88 clk->enable(clk); 89 } 90 } 91 } 92 93 void clk_disable(struct clk *clk) 94 { 95 if (clk) { 96 if (!(--clk->usecount)) { 97 if (clk->disable) 98 clk->disable(clk); 99 } 100 } 101 } 102 103 int clk_get_usecount(struct clk *clk) 104 { 105 if (clk == NULL) 106 return 0; 107 108 return clk->usecount; 109 } 110 111 u32 clk_get_rate(struct clk *clk) 112 { 113 if (!clk) 114 return 0; 115 116 return clk->rate; 117 } 118 119 struct clk *clk_get_parent(struct clk *clk) 120 { 121 if (!clk) 122 return 0; 123 124 return clk->parent; 125 } 126 127 int clk_set_rate(struct clk *clk, unsigned long rate) 128 { 129 if (clk && clk->set_rate) 130 clk->set_rate(clk, rate); 131 return clk->rate; 132 } 133 134 long clk_round_rate(struct clk *clk, unsigned long rate) 135 { 136 if (clk == NULL || !clk->round_rate) 137 return 0; 138 139 return clk->round_rate(clk, rate); 140 } 141 142 int clk_set_parent(struct clk *clk, struct clk *parent) 143 { 144 clk->parent = parent; 145 if (clk->set_parent) 146 return clk->set_parent(clk, parent); 147 return 0; 148 } 149 150 static int clk_ipu_enable(struct clk *clk) 151 { 152 u32 reg; 153 154 reg = __raw_readl(clk->enable_reg); 155 reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; 156 __raw_writel(reg, clk->enable_reg); 157 158 #if defined(CONFIG_MX51) || defined(CONFIG_MX53) 159 /* Handshake with IPU when certain clock rates are changed. */ 160 reg = __raw_readl(&mxc_ccm->ccdr); 161 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; 162 __raw_writel(reg, &mxc_ccm->ccdr); 163 164 /* Handshake with IPU when LPM is entered as its enabled. */ 165 reg = __raw_readl(&mxc_ccm->clpcr); 166 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; 167 __raw_writel(reg, &mxc_ccm->clpcr); 168 #endif 169 return 0; 170 } 171 172 static void clk_ipu_disable(struct clk *clk) 173 { 174 u32 reg; 175 176 reg = __raw_readl(clk->enable_reg); 177 reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); 178 __raw_writel(reg, clk->enable_reg); 179 180 #if defined(CONFIG_MX51) || defined(CONFIG_MX53) 181 /* 182 * No handshake with IPU whe dividers are changed 183 * as its not enabled. 184 */ 185 reg = __raw_readl(&mxc_ccm->ccdr); 186 reg |= MXC_CCM_CCDR_IPU_HS_MASK; 187 __raw_writel(reg, &mxc_ccm->ccdr); 188 189 /* No handshake with IPU when LPM is entered as its not enabled. */ 190 reg = __raw_readl(&mxc_ccm->clpcr); 191 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; 192 __raw_writel(reg, &mxc_ccm->clpcr); 193 #endif 194 } 195 196 197 static struct clk ipu_clk = { 198 .name = "ipu_clk", 199 .rate = CONFIG_IPUV3_CLK, 200 #if defined(CONFIG_MX51) || defined(CONFIG_MX53) 201 .enable_reg = (u32 *)(CCM_BASE_ADDR + 202 offsetof(struct mxc_ccm_reg, CCGR5)), 203 .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET, 204 #else 205 .enable_reg = (u32 *)(CCM_BASE_ADDR + 206 offsetof(struct mxc_ccm_reg, CCGR3)), 207 .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET, 208 #endif 209 .enable = clk_ipu_enable, 210 .disable = clk_ipu_disable, 211 .usecount = 0, 212 }; 213 214 #if !defined CONFIG_SYS_LDB_CLOCK 215 #define CONFIG_SYS_LDB_CLOCK 65000000 216 #endif 217 218 static struct clk ldb_clk = { 219 .name = "ldb_clk", 220 .rate = CONFIG_SYS_LDB_CLOCK, 221 .usecount = 0, 222 }; 223 224 /* Globals */ 225 struct clk *g_ipu_clk; 226 struct clk *g_ldb_clk; 227 unsigned char g_ipu_clk_enabled; 228 struct clk *g_di_clk[2]; 229 struct clk *g_pixel_clk[2]; 230 unsigned char g_dc_di_assignment[10]; 231 uint32_t g_channel_init_mask; 232 uint32_t g_channel_enable_mask; 233 234 static int ipu_dc_use_count; 235 static int ipu_dp_use_count; 236 static int ipu_dmfc_use_count; 237 static int ipu_di_use_count[2]; 238 239 u32 *ipu_cpmem_base; 240 u32 *ipu_dc_tmpl_reg; 241 242 /* Static functions */ 243 244 static inline void ipu_ch_param_set_high_priority(uint32_t ch) 245 { 246 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1); 247 }; 248 249 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) 250 { 251 return ((uint32_t) ch >> (6 * type)) & 0x3F; 252 }; 253 254 /* Either DP BG or DP FG can be graphic window */ 255 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan) 256 { 257 return (dma_chan == 23 || dma_chan == 27); 258 } 259 260 static inline int ipu_is_dmfc_chan(uint32_t dma_chan) 261 { 262 return ((dma_chan >= 23) && (dma_chan <= 29)); 263 } 264 265 266 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum, 267 dma_addr_t phyaddr) 268 { 269 ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29, 270 phyaddr / 8); 271 }; 272 273 #define idma_is_valid(ch) (ch != NO_DMA) 274 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) 275 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) 276 277 static void ipu_pixel_clk_recalc(struct clk *clk) 278 { 279 u32 div; 280 u64 final_rate = (unsigned long long)clk->parent->rate * 16; 281 282 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); 283 debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n", 284 div, final_rate, clk->parent->rate); 285 286 clk->rate = 0; 287 if (div != 0) { 288 do_div(final_rate, div); 289 clk->rate = final_rate; 290 } 291 } 292 293 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, 294 unsigned long rate) 295 { 296 u64 div, final_rate; 297 u32 remainder; 298 u64 parent_rate = (unsigned long long)clk->parent->rate * 16; 299 300 /* 301 * Calculate divider 302 * Fractional part is 4 bits, 303 * so simply multiply by 2^4 to get fractional part. 304 */ 305 div = parent_rate; 306 remainder = do_div(div, rate); 307 /* Round the divider value */ 308 if (remainder > (rate / 2)) 309 div++; 310 if (div < 0x10) /* Min DI disp clock divider is 1 */ 311 div = 0x10; 312 if (div & ~0xFEF) 313 div &= 0xFF8; 314 else { 315 /* Round up divider if it gets us closer to desired pix clk */ 316 if ((div & 0xC) == 0xC) { 317 div += 0x10; 318 div &= ~0xF; 319 } 320 } 321 final_rate = parent_rate; 322 do_div(final_rate, div); 323 324 return final_rate; 325 } 326 327 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) 328 { 329 u64 div, parent_rate; 330 u32 remainder; 331 332 parent_rate = (unsigned long long)clk->parent->rate * 16; 333 div = parent_rate; 334 remainder = do_div(div, rate); 335 /* Round the divider value */ 336 if (remainder > (rate / 2)) 337 div++; 338 339 /* Round up divider if it gets us closer to desired pix clk */ 340 if ((div & 0xC) == 0xC) { 341 div += 0x10; 342 div &= ~0xF; 343 } 344 if (div > 0x1000) 345 debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div); 346 347 __raw_writel(div, DI_BS_CLKGEN0(clk->id)); 348 349 /* 350 * Setup pixel clock timing 351 * Down time is half of period 352 */ 353 __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); 354 355 clk->rate = (u64)(clk->parent->rate * 16) / div; 356 357 return 0; 358 } 359 360 static int ipu_pixel_clk_enable(struct clk *clk) 361 { 362 u32 disp_gen = __raw_readl(IPU_DISP_GEN); 363 disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; 364 __raw_writel(disp_gen, IPU_DISP_GEN); 365 366 return 0; 367 } 368 369 static void ipu_pixel_clk_disable(struct clk *clk) 370 { 371 u32 disp_gen = __raw_readl(IPU_DISP_GEN); 372 disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; 373 __raw_writel(disp_gen, IPU_DISP_GEN); 374 375 } 376 377 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) 378 { 379 u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); 380 381 if (parent == g_ipu_clk) 382 di_gen &= ~DI_GEN_DI_CLK_EXT; 383 else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk) 384 di_gen |= DI_GEN_DI_CLK_EXT; 385 else 386 return -EINVAL; 387 388 __raw_writel(di_gen, DI_GENERAL(clk->id)); 389 ipu_pixel_clk_recalc(clk); 390 return 0; 391 } 392 393 static struct clk pixel_clk[] = { 394 { 395 .name = "pixel_clk", 396 .id = 0, 397 .recalc = ipu_pixel_clk_recalc, 398 .set_rate = ipu_pixel_clk_set_rate, 399 .round_rate = ipu_pixel_clk_round_rate, 400 .set_parent = ipu_pixel_clk_set_parent, 401 .enable = ipu_pixel_clk_enable, 402 .disable = ipu_pixel_clk_disable, 403 .usecount = 0, 404 }, 405 { 406 .name = "pixel_clk", 407 .id = 1, 408 .recalc = ipu_pixel_clk_recalc, 409 .set_rate = ipu_pixel_clk_set_rate, 410 .round_rate = ipu_pixel_clk_round_rate, 411 .set_parent = ipu_pixel_clk_set_parent, 412 .enable = ipu_pixel_clk_enable, 413 .disable = ipu_pixel_clk_disable, 414 .usecount = 0, 415 }, 416 }; 417 418 /* 419 * This function resets IPU 420 */ 421 static void ipu_reset(void) 422 { 423 u32 *reg; 424 u32 value; 425 int timeout = IPU_SW_RST_TOUT_USEC; 426 427 reg = (u32 *)SRC_BASE_ADDR; 428 value = __raw_readl(reg); 429 value = value | SW_IPU_RST; 430 __raw_writel(value, reg); 431 432 while (__raw_readl(reg) & SW_IPU_RST) { 433 udelay(1); 434 if (!(timeout--)) { 435 printf("ipu software reset timeout\n"); 436 break; 437 } 438 }; 439 } 440 441 /* 442 * This function is called by the driver framework to initialize the IPU 443 * hardware. 444 * 445 * @param dev The device structure for the IPU passed in by the 446 * driver framework. 447 * 448 * @return Returns 0 on success or negative error code on error 449 */ 450 int ipu_probe(void) 451 { 452 unsigned long ipu_base; 453 #if defined CONFIG_MX51 454 u32 temp; 455 456 u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; 457 u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); 458 459 __raw_writel(0xF00, reg_hsc_mcd); 460 461 /* CSI mode reserved*/ 462 temp = __raw_readl(reg_hsc_mxt_conf); 463 __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); 464 465 temp = __raw_readl(reg_hsc_mxt_conf); 466 __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); 467 #endif 468 469 ipu_base = IPU_CTRL_BASE_ADDR; 470 ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); 471 ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); 472 473 g_pixel_clk[0] = &pixel_clk[0]; 474 g_pixel_clk[1] = &pixel_clk[1]; 475 476 g_ipu_clk = &ipu_clk; 477 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); 478 g_ldb_clk = &ldb_clk; 479 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); 480 ipu_reset(); 481 482 clk_set_parent(g_pixel_clk[0], g_ipu_clk); 483 clk_set_parent(g_pixel_clk[1], g_ipu_clk); 484 clk_enable(g_ipu_clk); 485 486 g_di_clk[0] = NULL; 487 g_di_clk[1] = NULL; 488 489 __raw_writel(0x807FFFFF, IPU_MEM_RST); 490 while (__raw_readl(IPU_MEM_RST) & 0x80000000) 491 ; 492 493 ipu_init_dc_mappings(); 494 495 __raw_writel(0, IPU_INT_CTRL(5)); 496 __raw_writel(0, IPU_INT_CTRL(6)); 497 __raw_writel(0, IPU_INT_CTRL(9)); 498 __raw_writel(0, IPU_INT_CTRL(10)); 499 500 /* DMFC Init */ 501 ipu_dmfc_init(DMFC_NORMAL, 1); 502 503 /* Set sync refresh channels as high priority */ 504 __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); 505 506 /* Set MCU_T to divide MCU access window into 2 */ 507 __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); 508 509 clk_disable(g_ipu_clk); 510 511 return 0; 512 } 513 514 void ipu_dump_registers(void) 515 { 516 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); 517 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); 518 debug("IDMAC_CHA_EN1 = \t0x%08X\n", 519 __raw_readl(IDMAC_CHA_EN(0))); 520 debug("IDMAC_CHA_EN2 = \t0x%08X\n", 521 __raw_readl(IDMAC_CHA_EN(32))); 522 debug("IDMAC_CHA_PRI1 = \t0x%08X\n", 523 __raw_readl(IDMAC_CHA_PRI(0))); 524 debug("IDMAC_CHA_PRI2 = \t0x%08X\n", 525 __raw_readl(IDMAC_CHA_PRI(32))); 526 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 527 __raw_readl(IPU_CHA_DB_MODE_SEL(0))); 528 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 529 __raw_readl(IPU_CHA_DB_MODE_SEL(32))); 530 debug("DMFC_WR_CHAN = \t0x%08X\n", 531 __raw_readl(DMFC_WR_CHAN)); 532 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n", 533 __raw_readl(DMFC_WR_CHAN_DEF)); 534 debug("DMFC_DP_CHAN = \t0x%08X\n", 535 __raw_readl(DMFC_DP_CHAN)); 536 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n", 537 __raw_readl(DMFC_DP_CHAN_DEF)); 538 debug("DMFC_IC_CTRL = \t0x%08X\n", 539 __raw_readl(DMFC_IC_CTRL)); 540 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n", 541 __raw_readl(IPU_FS_PROC_FLOW1)); 542 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n", 543 __raw_readl(IPU_FS_PROC_FLOW2)); 544 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n", 545 __raw_readl(IPU_FS_PROC_FLOW3)); 546 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n", 547 __raw_readl(IPU_FS_DISP_FLOW1)); 548 } 549 550 /* 551 * This function is called to initialize a logical IPU channel. 552 * 553 * @param channel Input parameter for the logical channel ID to init. 554 * 555 * @param params Input parameter containing union of channel 556 * initialization parameters. 557 * 558 * @return Returns 0 on success or negative error code on fail 559 */ 560 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) 561 { 562 int ret = 0; 563 uint32_t ipu_conf; 564 565 debug("init channel = %d\n", IPU_CHAN_ID(channel)); 566 567 if (g_ipu_clk_enabled == 0) { 568 g_ipu_clk_enabled = 1; 569 clk_enable(g_ipu_clk); 570 } 571 572 573 if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { 574 printf("Warning: channel already initialized %d\n", 575 IPU_CHAN_ID(channel)); 576 } 577 578 ipu_conf = __raw_readl(IPU_CONF); 579 580 switch (channel) { 581 case MEM_DC_SYNC: 582 if (params->mem_dc_sync.di > 1) { 583 ret = -EINVAL; 584 goto err; 585 } 586 587 g_dc_di_assignment[1] = params->mem_dc_sync.di; 588 ipu_dc_init(1, params->mem_dc_sync.di, 589 params->mem_dc_sync.interlaced); 590 ipu_di_use_count[params->mem_dc_sync.di]++; 591 ipu_dc_use_count++; 592 ipu_dmfc_use_count++; 593 break; 594 case MEM_BG_SYNC: 595 if (params->mem_dp_bg_sync.di > 1) { 596 ret = -EINVAL; 597 goto err; 598 } 599 600 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di; 601 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, 602 params->mem_dp_bg_sync.out_pixel_fmt); 603 ipu_dc_init(5, params->mem_dp_bg_sync.di, 604 params->mem_dp_bg_sync.interlaced); 605 ipu_di_use_count[params->mem_dp_bg_sync.di]++; 606 ipu_dc_use_count++; 607 ipu_dp_use_count++; 608 ipu_dmfc_use_count++; 609 break; 610 case MEM_FG_SYNC: 611 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, 612 params->mem_dp_fg_sync.out_pixel_fmt); 613 614 ipu_dc_use_count++; 615 ipu_dp_use_count++; 616 ipu_dmfc_use_count++; 617 break; 618 default: 619 printf("Missing channel initialization\n"); 620 break; 621 } 622 623 /* Enable IPU sub module */ 624 g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); 625 if (ipu_dc_use_count == 1) 626 ipu_conf |= IPU_CONF_DC_EN; 627 if (ipu_dp_use_count == 1) 628 ipu_conf |= IPU_CONF_DP_EN; 629 if (ipu_dmfc_use_count == 1) 630 ipu_conf |= IPU_CONF_DMFC_EN; 631 if (ipu_di_use_count[0] == 1) { 632 ipu_conf |= IPU_CONF_DI0_EN; 633 } 634 if (ipu_di_use_count[1] == 1) { 635 ipu_conf |= IPU_CONF_DI1_EN; 636 } 637 638 __raw_writel(ipu_conf, IPU_CONF); 639 640 err: 641 return ret; 642 } 643 644 /* 645 * This function is called to uninitialize a logical IPU channel. 646 * 647 * @param channel Input parameter for the logical channel ID to uninit. 648 */ 649 void ipu_uninit_channel(ipu_channel_t channel) 650 { 651 uint32_t reg; 652 uint32_t in_dma, out_dma = 0; 653 uint32_t ipu_conf; 654 655 if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { 656 debug("Channel already uninitialized %d\n", 657 IPU_CHAN_ID(channel)); 658 return; 659 } 660 661 /* 662 * Make sure channel is disabled 663 * Get input and output dma channels 664 */ 665 in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); 666 out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); 667 668 if (idma_is_set(IDMAC_CHA_EN, in_dma) || 669 idma_is_set(IDMAC_CHA_EN, out_dma)) { 670 printf( 671 "Channel %d is not disabled, disable first\n", 672 IPU_CHAN_ID(channel)); 673 return; 674 } 675 676 ipu_conf = __raw_readl(IPU_CONF); 677 678 /* Reset the double buffer */ 679 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); 680 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); 681 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); 682 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); 683 684 switch (channel) { 685 case MEM_DC_SYNC: 686 ipu_dc_uninit(1); 687 ipu_di_use_count[g_dc_di_assignment[1]]--; 688 ipu_dc_use_count--; 689 ipu_dmfc_use_count--; 690 break; 691 case MEM_BG_SYNC: 692 ipu_dp_uninit(channel); 693 ipu_dc_uninit(5); 694 ipu_di_use_count[g_dc_di_assignment[5]]--; 695 ipu_dc_use_count--; 696 ipu_dp_use_count--; 697 ipu_dmfc_use_count--; 698 break; 699 case MEM_FG_SYNC: 700 ipu_dp_uninit(channel); 701 ipu_dc_use_count--; 702 ipu_dp_use_count--; 703 ipu_dmfc_use_count--; 704 break; 705 default: 706 break; 707 } 708 709 g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); 710 711 if (ipu_dc_use_count == 0) 712 ipu_conf &= ~IPU_CONF_DC_EN; 713 if (ipu_dp_use_count == 0) 714 ipu_conf &= ~IPU_CONF_DP_EN; 715 if (ipu_dmfc_use_count == 0) 716 ipu_conf &= ~IPU_CONF_DMFC_EN; 717 if (ipu_di_use_count[0] == 0) { 718 ipu_conf &= ~IPU_CONF_DI0_EN; 719 } 720 if (ipu_di_use_count[1] == 0) { 721 ipu_conf &= ~IPU_CONF_DI1_EN; 722 } 723 724 __raw_writel(ipu_conf, IPU_CONF); 725 726 if (ipu_conf == 0) { 727 clk_disable(g_ipu_clk); 728 g_ipu_clk_enabled = 0; 729 } 730 731 } 732 733 static inline void ipu_ch_param_dump(int ch) 734 { 735 #ifdef DEBUG 736 struct ipu_ch_param *p = ipu_ch_param_addr(ch); 737 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, 738 p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], 739 p->word[0].data[3], p->word[0].data[4]); 740 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, 741 p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], 742 p->word[1].data[3], p->word[1].data[4]); 743 debug("PFS 0x%x, ", 744 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); 745 debug("BPP 0x%x, ", 746 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); 747 debug("NPB 0x%x\n", 748 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); 749 750 debug("FW %d, ", 751 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); 752 debug("FH %d, ", 753 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); 754 debug("Stride %d\n", 755 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); 756 757 debug("Width0 %d+1, ", 758 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); 759 debug("Width1 %d+1, ", 760 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); 761 debug("Width2 %d+1, ", 762 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); 763 debug("Width3 %d+1, ", 764 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); 765 debug("Offset0 %d, ", 766 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); 767 debug("Offset1 %d, ", 768 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); 769 debug("Offset2 %d, ", 770 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); 771 debug("Offset3 %d\n", 772 ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); 773 #endif 774 } 775 776 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p, 777 int red_width, int red_offset, 778 int green_width, int green_offset, 779 int blue_width, int blue_offset, 780 int alpha_width, int alpha_offset) 781 { 782 /* Setup red width and offset */ 783 ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1); 784 ipu_ch_param_set_field(p, 1, 128, 5, red_offset); 785 /* Setup green width and offset */ 786 ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1); 787 ipu_ch_param_set_field(p, 1, 133, 5, green_offset); 788 /* Setup blue width and offset */ 789 ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1); 790 ipu_ch_param_set_field(p, 1, 138, 5, blue_offset); 791 /* Setup alpha width and offset */ 792 ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1); 793 ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset); 794 } 795 796 static void ipu_ch_param_init(int ch, 797 uint32_t pixel_fmt, uint32_t width, 798 uint32_t height, uint32_t stride, 799 uint32_t u, uint32_t v, 800 uint32_t uv_stride, dma_addr_t addr0, 801 dma_addr_t addr1) 802 { 803 uint32_t u_offset = 0; 804 uint32_t v_offset = 0; 805 struct ipu_ch_param params; 806 807 memset(¶ms, 0, sizeof(params)); 808 809 ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); 810 811 if ((ch == 8) || (ch == 9) || (ch == 10)) { 812 ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1); 813 ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1); 814 } else { 815 ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); 816 ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); 817 } 818 819 ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); 820 ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); 821 822 switch (pixel_fmt) { 823 case IPU_PIX_FMT_GENERIC: 824 /*Represents 8-bit Generic data */ 825 ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ 826 ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ 827 ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ 828 829 break; 830 case IPU_PIX_FMT_GENERIC_32: 831 /*Represents 32-bit Generic data */ 832 break; 833 case IPU_PIX_FMT_RGB565: 834 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ 835 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 836 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ 837 838 ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16); 839 break; 840 case IPU_PIX_FMT_BGR24: 841 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ 842 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 843 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ 844 845 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); 846 break; 847 case IPU_PIX_FMT_RGB24: 848 case IPU_PIX_FMT_YUV444: 849 ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ 850 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 851 ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ 852 853 ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24); 854 break; 855 case IPU_PIX_FMT_BGRA32: 856 case IPU_PIX_FMT_BGR32: 857 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ 858 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 859 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ 860 861 ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); 862 break; 863 case IPU_PIX_FMT_RGBA32: 864 case IPU_PIX_FMT_RGB32: 865 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ 866 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 867 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ 868 869 ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); 870 break; 871 case IPU_PIX_FMT_ABGR32: 872 ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ 873 ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ 874 875 ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); 876 break; 877 case IPU_PIX_FMT_UYVY: 878 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ 879 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ 880 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ 881 break; 882 case IPU_PIX_FMT_YUYV: 883 ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ 884 ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ 885 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ 886 break; 887 case IPU_PIX_FMT_YUV420P2: 888 case IPU_PIX_FMT_YUV420P: 889 ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ 890 891 if (uv_stride < stride / 2) 892 uv_stride = stride / 2; 893 894 u_offset = stride * height; 895 v_offset = u_offset + (uv_stride * height / 2); 896 /* burst size */ 897 if ((ch == 8) || (ch == 9) || (ch == 10)) { 898 ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); 899 uv_stride = uv_stride*2; 900 } else { 901 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); 902 } 903 break; 904 case IPU_PIX_FMT_YVU422P: 905 /* BPP & pixel format */ 906 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ 907 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ 908 909 if (uv_stride < stride / 2) 910 uv_stride = stride / 2; 911 912 v_offset = (v == 0) ? stride * height : v; 913 u_offset = (u == 0) ? v_offset + v_offset / 2 : u; 914 break; 915 case IPU_PIX_FMT_YUV422P: 916 /* BPP & pixel format */ 917 ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ 918 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ 919 920 if (uv_stride < stride / 2) 921 uv_stride = stride / 2; 922 923 u_offset = (u == 0) ? stride * height : u; 924 v_offset = (v == 0) ? u_offset + u_offset / 2 : v; 925 break; 926 case IPU_PIX_FMT_NV12: 927 /* BPP & pixel format */ 928 ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ 929 ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ 930 uv_stride = stride; 931 u_offset = (u == 0) ? stride * height : u; 932 break; 933 default: 934 puts("mxc ipu: unimplemented pixel format\n"); 935 break; 936 } 937 938 939 if (uv_stride) 940 ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); 941 942 /* Get the uv offset from user when need cropping */ 943 if (u || v) { 944 u_offset = u; 945 v_offset = v; 946 } 947 948 /* UBO and VBO are 22-bit */ 949 if (u_offset/8 > 0x3fffff) 950 puts("The value of U offset exceeds IPU limitation\n"); 951 if (v_offset/8 > 0x3fffff) 952 puts("The value of V offset exceeds IPU limitation\n"); 953 954 ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); 955 ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); 956 957 debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); 958 memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); 959 }; 960 961 /* 962 * This function is called to initialize a buffer for logical IPU channel. 963 * 964 * @param channel Input parameter for the logical channel ID. 965 * 966 * @param type Input parameter which buffer to initialize. 967 * 968 * @param pixel_fmt Input parameter for pixel format of buffer. 969 * Pixel format is a FOURCC ASCII code. 970 * 971 * @param width Input parameter for width of buffer in pixels. 972 * 973 * @param height Input parameter for height of buffer in pixels. 974 * 975 * @param stride Input parameter for stride length of buffer 976 * in pixels. 977 * 978 * @param phyaddr_0 Input parameter buffer 0 physical address. 979 * 980 * @param phyaddr_1 Input parameter buffer 1 physical address. 981 * Setting this to a value other than NULL enables 982 * double buffering mode. 983 * 984 * @param u private u offset for additional cropping, 985 * zero if not used. 986 * 987 * @param v private v offset for additional cropping, 988 * zero if not used. 989 * 990 * @return Returns 0 on success or negative error code on fail 991 */ 992 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, 993 uint32_t pixel_fmt, 994 uint16_t width, uint16_t height, 995 uint32_t stride, 996 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, 997 uint32_t u, uint32_t v) 998 { 999 uint32_t reg; 1000 uint32_t dma_chan; 1001 1002 dma_chan = channel_2_dma(channel, type); 1003 if (!idma_is_valid(dma_chan)) 1004 return -EINVAL; 1005 1006 if (stride < width * bytes_per_pixel(pixel_fmt)) 1007 stride = width * bytes_per_pixel(pixel_fmt); 1008 1009 if (stride % 4) { 1010 printf( 1011 "Stride not 32-bit aligned, stride = %d\n", stride); 1012 return -EINVAL; 1013 } 1014 /* Build parameter memory data for DMA channel */ 1015 ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0, 1016 phyaddr_0, phyaddr_1); 1017 1018 if (ipu_is_dmfc_chan(dma_chan)) { 1019 ipu_dmfc_set_wait4eot(dma_chan, width); 1020 } 1021 1022 if (idma_is_set(IDMAC_CHA_PRI, dma_chan)) 1023 ipu_ch_param_set_high_priority(dma_chan); 1024 1025 ipu_ch_param_dump(dma_chan); 1026 1027 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); 1028 if (phyaddr_1) 1029 reg |= idma_mask(dma_chan); 1030 else 1031 reg &= ~idma_mask(dma_chan); 1032 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); 1033 1034 /* Reset to buffer 0 */ 1035 __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan)); 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * This function enables a logical channel. 1042 * 1043 * @param channel Input parameter for the logical channel ID. 1044 * 1045 * @return This function returns 0 on success or negative error code on 1046 * fail. 1047 */ 1048 int32_t ipu_enable_channel(ipu_channel_t channel) 1049 { 1050 uint32_t reg; 1051 uint32_t in_dma; 1052 uint32_t out_dma; 1053 1054 if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) { 1055 printf("Warning: channel already enabled %d\n", 1056 IPU_CHAN_ID(channel)); 1057 } 1058 1059 /* Get input and output dma channels */ 1060 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); 1061 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); 1062 1063 if (idma_is_valid(in_dma)) { 1064 reg = __raw_readl(IDMAC_CHA_EN(in_dma)); 1065 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); 1066 } 1067 if (idma_is_valid(out_dma)) { 1068 reg = __raw_readl(IDMAC_CHA_EN(out_dma)); 1069 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); 1070 } 1071 1072 if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || 1073 (channel == MEM_FG_SYNC)) 1074 ipu_dp_dc_enable(channel); 1075 1076 g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * This function clear buffer ready for a logical channel. 1083 * 1084 * @param channel Input parameter for the logical channel ID. 1085 * 1086 * @param type Input parameter which buffer to clear. 1087 * 1088 * @param bufNum Input parameter for which buffer number clear 1089 * ready state. 1090 * 1091 */ 1092 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, 1093 uint32_t bufNum) 1094 { 1095 uint32_t dma_ch = channel_2_dma(channel, type); 1096 1097 if (!idma_is_valid(dma_ch)) 1098 return; 1099 1100 __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */ 1101 if (bufNum == 0) { 1102 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) { 1103 __raw_writel(idma_mask(dma_ch), 1104 IPU_CHA_BUF0_RDY(dma_ch)); 1105 } 1106 } else { 1107 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) { 1108 __raw_writel(idma_mask(dma_ch), 1109 IPU_CHA_BUF1_RDY(dma_ch)); 1110 } 1111 } 1112 __raw_writel(0x0, IPU_GPR); /* write one to set */ 1113 } 1114 1115 /* 1116 * This function disables a logical channel. 1117 * 1118 * @param channel Input parameter for the logical channel ID. 1119 * 1120 * @param wait_for_stop Flag to set whether to wait for channel end 1121 * of frame or return immediately. 1122 * 1123 * @return This function returns 0 on success or negative error code on 1124 * fail. 1125 */ 1126 int32_t ipu_disable_channel(ipu_channel_t channel) 1127 { 1128 uint32_t reg; 1129 uint32_t in_dma; 1130 uint32_t out_dma; 1131 1132 if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) { 1133 debug("Channel already disabled %d\n", 1134 IPU_CHAN_ID(channel)); 1135 return 0; 1136 } 1137 1138 /* Get input and output dma channels */ 1139 out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); 1140 in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); 1141 1142 if ((idma_is_valid(in_dma) && 1143 !idma_is_set(IDMAC_CHA_EN, in_dma)) 1144 && (idma_is_valid(out_dma) && 1145 !idma_is_set(IDMAC_CHA_EN, out_dma))) 1146 return -EINVAL; 1147 1148 if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || 1149 (channel == MEM_DC_SYNC)) { 1150 ipu_dp_dc_disable(channel, 0); 1151 } 1152 1153 /* Disable DMA channel(s) */ 1154 if (idma_is_valid(in_dma)) { 1155 reg = __raw_readl(IDMAC_CHA_EN(in_dma)); 1156 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); 1157 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma)); 1158 } 1159 if (idma_is_valid(out_dma)) { 1160 reg = __raw_readl(IDMAC_CHA_EN(out_dma)); 1161 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); 1162 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma)); 1163 } 1164 1165 g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel)); 1166 1167 /* Set channel buffers NOT to be ready */ 1168 if (idma_is_valid(in_dma)) { 1169 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0); 1170 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1); 1171 } 1172 if (idma_is_valid(out_dma)) { 1173 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0); 1174 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1); 1175 } 1176 1177 return 0; 1178 } 1179 1180 uint32_t bytes_per_pixel(uint32_t fmt) 1181 { 1182 switch (fmt) { 1183 case IPU_PIX_FMT_GENERIC: /*generic data */ 1184 case IPU_PIX_FMT_RGB332: 1185 case IPU_PIX_FMT_YUV420P: 1186 case IPU_PIX_FMT_YUV422P: 1187 return 1; 1188 break; 1189 case IPU_PIX_FMT_RGB565: 1190 case IPU_PIX_FMT_YUYV: 1191 case IPU_PIX_FMT_UYVY: 1192 return 2; 1193 break; 1194 case IPU_PIX_FMT_BGR24: 1195 case IPU_PIX_FMT_RGB24: 1196 return 3; 1197 break; 1198 case IPU_PIX_FMT_GENERIC_32: /*generic data */ 1199 case IPU_PIX_FMT_BGR32: 1200 case IPU_PIX_FMT_BGRA32: 1201 case IPU_PIX_FMT_RGB32: 1202 case IPU_PIX_FMT_RGBA32: 1203 case IPU_PIX_FMT_ABGR32: 1204 return 4; 1205 break; 1206 default: 1207 return 1; 1208 break; 1209 } 1210 return 0; 1211 } 1212 1213 ipu_color_space_t format_to_colorspace(uint32_t fmt) 1214 { 1215 switch (fmt) { 1216 case IPU_PIX_FMT_RGB666: 1217 case IPU_PIX_FMT_RGB565: 1218 case IPU_PIX_FMT_BGR24: 1219 case IPU_PIX_FMT_RGB24: 1220 case IPU_PIX_FMT_BGR32: 1221 case IPU_PIX_FMT_BGRA32: 1222 case IPU_PIX_FMT_RGB32: 1223 case IPU_PIX_FMT_RGBA32: 1224 case IPU_PIX_FMT_ABGR32: 1225 case IPU_PIX_FMT_LVDS666: 1226 case IPU_PIX_FMT_LVDS888: 1227 return RGB; 1228 break; 1229 1230 default: 1231 return YCbCr; 1232 break; 1233 } 1234 return RGB; 1235 } 1236 1237 /* should be removed when clk framework is availiable */ 1238 int ipu_set_ldb_clock(int rate) 1239 { 1240 ldb_clk.rate = rate; 1241 1242 return 0; 1243 } 1244