1 /* 2 * Porting to u-boot: 3 * 4 * (C) Copyright 2010 5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de 6 * 7 * Linux IPU driver for MX51: 8 * 9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #ifndef __ASM_ARCH_IPU_H__ 15 #define __ASM_ARCH_IPU_H__ 16 17 #include <linux/types.h> 18 #include <ipu_pixfmt.h> 19 20 #define IDMA_CHAN_INVALID 0xFF 21 #define HIGH_RESOLUTION_WIDTH 1024 22 23 struct clk { 24 const char *name; 25 int id; 26 /* Source clock this clk depends on */ 27 struct clk *parent; 28 /* Secondary clock to enable/disable with this clock */ 29 struct clk *secondary; 30 /* Current clock rate */ 31 unsigned long rate; 32 /* Reference count of clock enable/disable */ 33 __s8 usecount; 34 /* Register bit position for clock's enable/disable control. */ 35 u8 enable_shift; 36 /* Register address for clock's enable/disable control. */ 37 void *enable_reg; 38 u32 flags; 39 /* 40 * Function ptr to recalculate the clock's rate based on parent 41 * clock's rate 42 */ 43 void (*recalc) (struct clk *); 44 /* 45 * Function ptr to set the clock to a new rate. The rate must match a 46 * supported rate returned from round_rate. Leave blank if clock is not 47 * programmable 48 */ 49 int (*set_rate) (struct clk *, unsigned long); 50 /* 51 * Function ptr to round the requested clock rate to the nearest 52 * supported rate that is less than or equal to the requested rate. 53 */ 54 unsigned long (*round_rate) (struct clk *, unsigned long); 55 /* 56 * Function ptr to enable the clock. Leave blank if clock can not 57 * be gated. 58 */ 59 int (*enable) (struct clk *); 60 /* 61 * Function ptr to disable the clock. Leave blank if clock can not 62 * be gated. 63 */ 64 void (*disable) (struct clk *); 65 /* Function ptr to set the parent clock of the clock. */ 66 int (*set_parent) (struct clk *, struct clk *); 67 }; 68 69 /* 70 * Enumeration of Synchronous (Memory-less) panel types 71 */ 72 typedef enum { 73 IPU_PANEL_SHARP_TFT, 74 IPU_PANEL_TFT, 75 } ipu_panel_t; 76 77 /* 78 * IPU Driver channels definitions. 79 * Note these are different from IDMA channels 80 */ 81 #define IPU_MAX_CH 32 82 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ 83 ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) 84 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) 85 #define IPU_CHAN_ID(ch) (ch >> 24) 86 #define IPU_CHAN_ALT(ch) (ch & 0x02000000) 87 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) 88 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) 89 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) 90 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) 91 #define NO_DMA 0x3F 92 #define ALT 1 93 94 /* 95 * Enumeration of IPU logical channels. An IPU logical channel is defined as a 96 * combination of an input (memory to IPU), output (IPU to memory), and/or 97 * secondary input IDMA channels and in some cases an Image Converter task. 98 * Some channels consist of only an input or output. 99 */ 100 typedef enum { 101 CHAN_NONE = -1, 102 103 MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), 104 MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), 105 MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), 106 MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), 107 108 MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), 109 MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), 110 MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), 111 MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), 112 113 DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), 114 DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), 115 116 } ipu_channel_t; 117 118 /* 119 * Enumeration of types of buffers for a logical channel. 120 */ 121 typedef enum { 122 IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */ 123 IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */ 124 IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */ 125 IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */ 126 IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, 127 IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, 128 } ipu_buffer_t; 129 130 #define IPU_PANEL_SERIAL 1 131 #define IPU_PANEL_PARALLEL 2 132 133 struct ipu_channel { 134 u8 video_in_dma; 135 u8 alpha_in_dma; 136 u8 graph_in_dma; 137 u8 out_dma; 138 }; 139 140 enum ipu_dmfc_type { 141 DMFC_NORMAL = 0, 142 DMFC_HIGH_RESOLUTION_DC, 143 DMFC_HIGH_RESOLUTION_DP, 144 DMFC_HIGH_RESOLUTION_ONLY_DP, 145 }; 146 147 148 /* 149 * Union of initialization parameters for a logical channel. 150 */ 151 typedef union { 152 struct { 153 uint32_t di; 154 unsigned char interlaced; 155 } mem_dc_sync; 156 struct { 157 uint32_t temp; 158 } mem_sdc_fg; 159 struct { 160 uint32_t di; 161 unsigned char interlaced; 162 uint32_t in_pixel_fmt; 163 uint32_t out_pixel_fmt; 164 unsigned char alpha_chan_en; 165 } mem_dp_bg_sync; 166 struct { 167 uint32_t temp; 168 } mem_sdc_bg; 169 struct { 170 uint32_t di; 171 unsigned char interlaced; 172 uint32_t in_pixel_fmt; 173 uint32_t out_pixel_fmt; 174 unsigned char alpha_chan_en; 175 } mem_dp_fg_sync; 176 } ipu_channel_params_t; 177 178 /* 179 * Bitfield of Display Interface signal polarities. 180 */ 181 typedef struct { 182 unsigned datamask_en:1; 183 unsigned ext_clk:1; 184 unsigned interlaced:1; 185 unsigned odd_field_first:1; 186 unsigned clksel_en:1; 187 unsigned clkidle_en:1; 188 unsigned data_pol:1; /* true = inverted */ 189 unsigned clk_pol:1; /* true = rising edge */ 190 unsigned enable_pol:1; 191 unsigned Hsync_pol:1; /* true = active high */ 192 unsigned Vsync_pol:1; 193 } ipu_di_signal_cfg_t; 194 195 typedef enum { 196 RGB, 197 YCbCr, 198 YUV 199 } ipu_color_space_t; 200 201 /* Common IPU API */ 202 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); 203 void ipu_uninit_channel(ipu_channel_t channel); 204 205 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, 206 uint32_t pixel_fmt, 207 uint16_t width, uint16_t height, 208 uint32_t stride, 209 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, 210 uint32_t u_offset, uint32_t v_offset); 211 212 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, 213 uint32_t bufNum, dma_addr_t phyaddr); 214 215 int32_t ipu_is_channel_busy(ipu_channel_t channel); 216 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, 217 uint32_t bufNum); 218 int32_t ipu_enable_channel(ipu_channel_t channel); 219 int32_t ipu_disable_channel(ipu_channel_t channel); 220 221 int32_t ipu_init_sync_panel(int disp, 222 uint32_t pixel_clk, 223 uint16_t width, uint16_t height, 224 uint32_t pixel_fmt, 225 uint16_t h_start_width, uint16_t h_sync_width, 226 uint16_t h_end_width, uint16_t v_start_width, 227 uint16_t v_sync_width, uint16_t v_end_width, 228 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); 229 230 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, 231 uint8_t alpha); 232 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, 233 uint32_t colorKey); 234 235 uint32_t bytes_per_pixel(uint32_t fmt); 236 237 void clk_enable(struct clk *clk); 238 void clk_disable(struct clk *clk); 239 u32 clk_get_rate(struct clk *clk); 240 int clk_set_rate(struct clk *clk, unsigned long rate); 241 long clk_round_rate(struct clk *clk, unsigned long rate); 242 int clk_set_parent(struct clk *clk, struct clk *parent); 243 int clk_get_usecount(struct clk *clk); 244 struct clk *clk_get_parent(struct clk *clk); 245 246 void ipu_dump_registers(void); 247 int ipu_probe(void); 248 249 void ipu_dmfc_init(int dmfc_type, int first); 250 void ipu_init_dc_mappings(void); 251 void ipu_dmfc_set_wait4eot(int dma_chan, int width); 252 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced); 253 void ipu_dc_uninit(int dc_chan); 254 void ipu_dp_dc_enable(ipu_channel_t channel); 255 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, 256 uint32_t out_pixel_fmt); 257 void ipu_dp_uninit(ipu_channel_t channel); 258 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap); 259 ipu_color_space_t format_to_colorspace(uint32_t fmt); 260 261 #endif 262