1 /* 2 * Porting to u-boot: 3 * 4 * (C) Copyright 2010 5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de 6 * 7 * Linux IPU driver for MX51: 8 * 9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __ASM_ARCH_IPU_H__ 31 #define __ASM_ARCH_IPU_H__ 32 33 #include <linux/types.h> 34 #include <ipu_pixfmt.h> 35 36 #define IDMA_CHAN_INVALID 0xFF 37 #define HIGH_RESOLUTION_WIDTH 1024 38 39 struct clk { 40 const char *name; 41 int id; 42 /* Source clock this clk depends on */ 43 struct clk *parent; 44 /* Secondary clock to enable/disable with this clock */ 45 struct clk *secondary; 46 /* Current clock rate */ 47 unsigned long rate; 48 /* Reference count of clock enable/disable */ 49 __s8 usecount; 50 /* Register bit position for clock's enable/disable control. */ 51 u8 enable_shift; 52 /* Register address for clock's enable/disable control. */ 53 void *enable_reg; 54 u32 flags; 55 /* 56 * Function ptr to recalculate the clock's rate based on parent 57 * clock's rate 58 */ 59 void (*recalc) (struct clk *); 60 /* 61 * Function ptr to set the clock to a new rate. The rate must match a 62 * supported rate returned from round_rate. Leave blank if clock is not 63 * programmable 64 */ 65 int (*set_rate) (struct clk *, unsigned long); 66 /* 67 * Function ptr to round the requested clock rate to the nearest 68 * supported rate that is less than or equal to the requested rate. 69 */ 70 unsigned long (*round_rate) (struct clk *, unsigned long); 71 /* 72 * Function ptr to enable the clock. Leave blank if clock can not 73 * be gated. 74 */ 75 int (*enable) (struct clk *); 76 /* 77 * Function ptr to disable the clock. Leave blank if clock can not 78 * be gated. 79 */ 80 void (*disable) (struct clk *); 81 /* Function ptr to set the parent clock of the clock. */ 82 int (*set_parent) (struct clk *, struct clk *); 83 }; 84 85 /* 86 * Enumeration of Synchronous (Memory-less) panel types 87 */ 88 typedef enum { 89 IPU_PANEL_SHARP_TFT, 90 IPU_PANEL_TFT, 91 } ipu_panel_t; 92 93 /* 94 * IPU Driver channels definitions. 95 * Note these are different from IDMA channels 96 */ 97 #define IPU_MAX_CH 32 98 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ 99 ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) 100 #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) 101 #define IPU_CHAN_ID(ch) (ch >> 24) 102 #define IPU_CHAN_ALT(ch) (ch & 0x02000000) 103 #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) 104 #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) 105 #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) 106 #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) 107 #define NO_DMA 0x3F 108 #define ALT 1 109 110 /* 111 * Enumeration of IPU logical channels. An IPU logical channel is defined as a 112 * combination of an input (memory to IPU), output (IPU to memory), and/or 113 * secondary input IDMA channels and in some cases an Image Converter task. 114 * Some channels consist of only an input or output. 115 */ 116 typedef enum { 117 CHAN_NONE = -1, 118 119 MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), 120 MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), 121 MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), 122 MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), 123 124 MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), 125 MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), 126 MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), 127 MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), 128 129 DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), 130 DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), 131 132 } ipu_channel_t; 133 134 /* 135 * Enumeration of types of buffers for a logical channel. 136 */ 137 typedef enum { 138 IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */ 139 IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */ 140 IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */ 141 IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */ 142 IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, 143 IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, 144 } ipu_buffer_t; 145 146 #define IPU_PANEL_SERIAL 1 147 #define IPU_PANEL_PARALLEL 2 148 149 struct ipu_channel { 150 u8 video_in_dma; 151 u8 alpha_in_dma; 152 u8 graph_in_dma; 153 u8 out_dma; 154 }; 155 156 enum ipu_dmfc_type { 157 DMFC_NORMAL = 0, 158 DMFC_HIGH_RESOLUTION_DC, 159 DMFC_HIGH_RESOLUTION_DP, 160 DMFC_HIGH_RESOLUTION_ONLY_DP, 161 }; 162 163 164 /* 165 * Union of initialization parameters for a logical channel. 166 */ 167 typedef union { 168 struct { 169 uint32_t di; 170 unsigned char interlaced; 171 } mem_dc_sync; 172 struct { 173 uint32_t temp; 174 } mem_sdc_fg; 175 struct { 176 uint32_t di; 177 unsigned char interlaced; 178 uint32_t in_pixel_fmt; 179 uint32_t out_pixel_fmt; 180 unsigned char alpha_chan_en; 181 } mem_dp_bg_sync; 182 struct { 183 uint32_t temp; 184 } mem_sdc_bg; 185 struct { 186 uint32_t di; 187 unsigned char interlaced; 188 uint32_t in_pixel_fmt; 189 uint32_t out_pixel_fmt; 190 unsigned char alpha_chan_en; 191 } mem_dp_fg_sync; 192 } ipu_channel_params_t; 193 194 /* 195 * Bitfield of Display Interface signal polarities. 196 */ 197 typedef struct { 198 unsigned datamask_en:1; 199 unsigned ext_clk:1; 200 unsigned interlaced:1; 201 unsigned odd_field_first:1; 202 unsigned clksel_en:1; 203 unsigned clkidle_en:1; 204 unsigned data_pol:1; /* true = inverted */ 205 unsigned clk_pol:1; /* true = rising edge */ 206 unsigned enable_pol:1; 207 unsigned Hsync_pol:1; /* true = active high */ 208 unsigned Vsync_pol:1; 209 } ipu_di_signal_cfg_t; 210 211 typedef enum { 212 RGB, 213 YCbCr, 214 YUV 215 } ipu_color_space_t; 216 217 /* Common IPU API */ 218 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); 219 void ipu_uninit_channel(ipu_channel_t channel); 220 221 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, 222 uint32_t pixel_fmt, 223 uint16_t width, uint16_t height, 224 uint32_t stride, 225 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, 226 uint32_t u_offset, uint32_t v_offset); 227 228 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, 229 uint32_t bufNum, dma_addr_t phyaddr); 230 231 int32_t ipu_is_channel_busy(ipu_channel_t channel); 232 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, 233 uint32_t bufNum); 234 int32_t ipu_enable_channel(ipu_channel_t channel); 235 int32_t ipu_disable_channel(ipu_channel_t channel); 236 237 int32_t ipu_init_sync_panel(int disp, 238 uint32_t pixel_clk, 239 uint16_t width, uint16_t height, 240 uint32_t pixel_fmt, 241 uint16_t h_start_width, uint16_t h_sync_width, 242 uint16_t h_end_width, uint16_t v_start_width, 243 uint16_t v_sync_width, uint16_t v_end_width, 244 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); 245 246 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, 247 uint8_t alpha); 248 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, 249 uint32_t colorKey); 250 251 uint32_t bytes_per_pixel(uint32_t fmt); 252 253 void clk_enable(struct clk *clk); 254 void clk_disable(struct clk *clk); 255 u32 clk_get_rate(struct clk *clk); 256 int clk_set_rate(struct clk *clk, unsigned long rate); 257 long clk_round_rate(struct clk *clk, unsigned long rate); 258 int clk_set_parent(struct clk *clk, struct clk *parent); 259 int clk_get_usecount(struct clk *clk); 260 struct clk *clk_get_parent(struct clk *clk); 261 262 void ipu_dump_registers(void); 263 int ipu_probe(void); 264 265 void ipu_dmfc_init(int dmfc_type, int first); 266 void ipu_init_dc_mappings(void); 267 void ipu_dmfc_set_wait4eot(int dma_chan, int width); 268 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced); 269 void ipu_dc_uninit(int dc_chan); 270 void ipu_dp_dc_enable(ipu_channel_t channel); 271 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, 272 uint32_t out_pixel_fmt); 273 void ipu_dp_uninit(ipu_channel_t channel); 274 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap); 275 ipu_color_space_t format_to_colorspace(uint32_t fmt); 276 277 #endif 278