1 /* 2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: York Sun <yorksun@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * FSL DIU Framebuffer driver 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <asm/io.h> 14 15 #include "videomodes.h" 16 #include <video_fb.h> 17 #include <fsl_diu_fb.h> 18 #include <linux/list.h> 19 #include <linux/fb.h> 20 21 /* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */ 22 static struct fb_videomode fsl_diu_mode_800_480 = { 23 .name = "800x480-60", 24 .refresh = 60, 25 .xres = 800, 26 .yres = 480, 27 .pixclock = 31250, 28 .left_margin = 86, 29 .right_margin = 42, 30 .upper_margin = 33, 31 .lower_margin = 10, 32 .hsync_len = 128, 33 .vsync_len = 2, 34 .sync = 0, 35 .vmode = FB_VMODE_NONINTERLACED 36 }; 37 38 /* For the SHARP LQ084S3LG01, used on the P1022DS board */ 39 static struct fb_videomode fsl_diu_mode_800_600 = { 40 .name = "800x600-60", 41 .refresh = 60, 42 .xres = 800, 43 .yres = 600, 44 .pixclock = 25000, 45 .left_margin = 88, 46 .right_margin = 40, 47 .upper_margin = 23, 48 .lower_margin = 1, 49 .hsync_len = 128, 50 .vsync_len = 4, 51 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 52 .vmode = FB_VMODE_NONINTERLACED 53 }; 54 55 /* 56 * These parameters give default parameters 57 * for video output 1024x768, 58 * FIXME - change timing to proper amounts 59 * hsync 31.5kHz, vsync 60Hz 60 */ 61 static struct fb_videomode fsl_diu_mode_1024_768 = { 62 .name = "1024x768-60", 63 .refresh = 60, 64 .xres = 1024, 65 .yres = 768, 66 .pixclock = 15385, 67 .left_margin = 160, 68 .right_margin = 24, 69 .upper_margin = 29, 70 .lower_margin = 3, 71 .hsync_len = 136, 72 .vsync_len = 6, 73 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 74 .vmode = FB_VMODE_NONINTERLACED 75 }; 76 77 static struct fb_videomode fsl_diu_mode_1280_1024 = { 78 .name = "1280x1024-60", 79 .refresh = 60, 80 .xres = 1280, 81 .yres = 1024, 82 .pixclock = 9375, 83 .left_margin = 38, 84 .right_margin = 128, 85 .upper_margin = 2, 86 .lower_margin = 7, 87 .hsync_len = 216, 88 .vsync_len = 37, 89 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 90 .vmode = FB_VMODE_NONINTERLACED 91 }; 92 93 static struct fb_videomode fsl_diu_mode_1280_720 = { 94 .name = "1280x720-60", 95 .refresh = 60, 96 .xres = 1280, 97 .yres = 720, 98 .pixclock = 13426, 99 .left_margin = 192, 100 .right_margin = 64, 101 .upper_margin = 22, 102 .lower_margin = 1, 103 .hsync_len = 136, 104 .vsync_len = 3, 105 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 106 .vmode = FB_VMODE_NONINTERLACED 107 }; 108 109 static struct fb_videomode fsl_diu_mode_1920_1080 = { 110 .name = "1920x1080-60", 111 .refresh = 60, 112 .xres = 1920, 113 .yres = 1080, 114 .pixclock = 5787, 115 .left_margin = 328, 116 .right_margin = 120, 117 .upper_margin = 34, 118 .lower_margin = 1, 119 .hsync_len = 208, 120 .vsync_len = 3, 121 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 122 .vmode = FB_VMODE_NONINTERLACED 123 }; 124 125 /* 126 * These are the fields of area descriptor(in DDR memory) for every plane 127 */ 128 struct diu_ad { 129 /* Word 0(32-bit) in DDR memory */ 130 __le32 pix_fmt; /* hard coding pixel format */ 131 /* Word 1(32-bit) in DDR memory */ 132 __le32 addr; 133 /* Word 2(32-bit) in DDR memory */ 134 __le32 src_size_g_alpha; 135 /* Word 3(32-bit) in DDR memory */ 136 __le32 aoi_size; 137 /* Word 4(32-bit) in DDR memory */ 138 __le32 offset_xyi; 139 /* Word 5(32-bit) in DDR memory */ 140 __le32 offset_xyd; 141 /* Word 6(32-bit) in DDR memory */ 142 __le32 ckmax_r:8; 143 __le32 ckmax_g:8; 144 __le32 ckmax_b:8; 145 __le32 res9:8; 146 /* Word 7(32-bit) in DDR memory */ 147 __le32 ckmin_r:8; 148 __le32 ckmin_g:8; 149 __le32 ckmin_b:8; 150 __le32 res10:8; 151 /* Word 8(32-bit) in DDR memory */ 152 __le32 next_ad; 153 /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */ 154 __le32 res[3]; 155 } __attribute__ ((packed)); 156 157 /* 158 * DIU register map 159 */ 160 struct diu { 161 __be32 desc[3]; 162 __be32 gamma; 163 __be32 pallete; 164 __be32 cursor; 165 __be32 curs_pos; 166 __be32 diu_mode; 167 __be32 bgnd; 168 __be32 bgnd_wb; 169 __be32 disp_size; 170 __be32 wb_size; 171 __be32 wb_mem_addr; 172 __be32 hsyn_para; 173 __be32 vsyn_para; 174 __be32 syn_pol; 175 __be32 thresholds; 176 __be32 int_status; 177 __be32 int_mask; 178 __be32 colorbar[8]; 179 __be32 filling; 180 __be32 plut; 181 } __attribute__ ((packed)); 182 183 struct diu_addr { 184 void *vaddr; /* Virtual address */ 185 u32 paddr; /* 32-bit physical address */ 186 unsigned int offset; /* Alignment offset */ 187 }; 188 189 static struct fb_info info; 190 191 /* 192 * Align to 64-bit(8-byte), 32-byte, etc. 193 */ 194 static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) 195 { 196 u32 offset, ssize; 197 u32 mask; 198 199 ssize = size + bytes_align; 200 buf->vaddr = malloc(ssize); 201 if (!buf->vaddr) 202 return -1; 203 204 memset(buf->vaddr, 0, ssize); 205 mask = bytes_align - 1; 206 offset = (u32)buf->vaddr & mask; 207 if (offset) { 208 buf->offset = bytes_align - offset; 209 buf->vaddr += offset; 210 } else 211 buf->offset = 0; 212 213 buf->paddr = virt_to_phys(buf->vaddr); 214 return 0; 215 } 216 217 /* 218 * Allocate a framebuffer and an Area Descriptor that points to it. Both 219 * are created in the same memory block. The Area Descriptor is updated to 220 * point to the framebuffer memory. Memory is aligned as needed. 221 */ 222 static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres, 223 unsigned int depth, char **fb) 224 { 225 unsigned long size = xres * yres * depth; 226 struct diu_addr addr; 227 struct diu_ad *ad; 228 size_t ad_size = roundup(sizeof(struct diu_ad), 32); 229 230 /* 231 * Allocate a memory block that holds the Area Descriptor and the 232 * frame buffer right behind it. To keep the code simple, everything 233 * is aligned on a 32-byte address. 234 */ 235 if (allocate_buf(&addr, ad_size + size, 32) < 0) 236 return NULL; 237 238 ad = addr.vaddr; 239 ad->addr = cpu_to_le32(addr.paddr + ad_size); 240 ad->aoi_size = cpu_to_le32((yres << 16) | xres); 241 ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres); 242 ad->offset_xyi = 0; 243 ad->offset_xyd = 0; 244 245 if (fb) 246 *fb = addr.vaddr + ad_size; 247 248 return ad; 249 } 250 251 int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) 252 { 253 struct fb_videomode *fsl_diu_mode_db; 254 struct diu_ad *ad; 255 struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR; 256 u8 *gamma_table_base; 257 unsigned int i, j; 258 struct diu_addr gamma; 259 struct diu_addr cursor; 260 261 /* Convert the X,Y resolution pair into a single number */ 262 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) 263 264 switch (RESOLUTION(xres, yres)) { 265 case RESOLUTION(800, 480): 266 fsl_diu_mode_db = &fsl_diu_mode_800_480; 267 break; 268 case RESOLUTION(800, 600): 269 fsl_diu_mode_db = &fsl_diu_mode_800_600; 270 break; 271 case RESOLUTION(1024, 768): 272 fsl_diu_mode_db = &fsl_diu_mode_1024_768; 273 break; 274 case RESOLUTION(1280, 1024): 275 fsl_diu_mode_db = &fsl_diu_mode_1280_1024; 276 break; 277 case RESOLUTION(1280, 720): 278 fsl_diu_mode_db = &fsl_diu_mode_1280_720; 279 break; 280 case RESOLUTION(1920, 1080): 281 fsl_diu_mode_db = &fsl_diu_mode_1920_1080; 282 break; 283 default: 284 printf("DIU: Unsupported resolution %ux%u\n", xres, yres); 285 return -1; 286 } 287 288 /* read mode info */ 289 info.var.xres = fsl_diu_mode_db->xres; 290 info.var.yres = fsl_diu_mode_db->yres; 291 info.var.bits_per_pixel = 32; 292 info.var.pixclock = fsl_diu_mode_db->pixclock; 293 info.var.left_margin = fsl_diu_mode_db->left_margin; 294 info.var.right_margin = fsl_diu_mode_db->right_margin; 295 info.var.upper_margin = fsl_diu_mode_db->upper_margin; 296 info.var.lower_margin = fsl_diu_mode_db->lower_margin; 297 info.var.hsync_len = fsl_diu_mode_db->hsync_len; 298 info.var.vsync_len = fsl_diu_mode_db->vsync_len; 299 info.var.sync = fsl_diu_mode_db->sync; 300 info.var.vmode = fsl_diu_mode_db->vmode; 301 info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; 302 303 /* Memory allocation for framebuffer */ 304 info.screen_size = 305 info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); 306 ad = allocate_fb(info.var.xres, info.var.yres, 307 info.var.bits_per_pixel / 8, &info.screen_base); 308 if (!ad) { 309 printf("DIU: Out of memory\n"); 310 return -1; 311 } 312 313 ad->pix_fmt = pixel_format; 314 315 /* Disable chroma keying function */ 316 ad->ckmax_r = 0; 317 ad->ckmax_g = 0; 318 ad->ckmax_b = 0; 319 320 ad->ckmin_r = 255; 321 ad->ckmin_g = 255; 322 ad->ckmin_b = 255; 323 324 /* Initialize the gamma table */ 325 if (allocate_buf(&gamma, 256 * 3, 32) < 0) { 326 printf("DIU: Out of memory\n"); 327 return -1; 328 } 329 gamma_table_base = gamma.vaddr; 330 for (i = 0; i <= 2; i++) 331 for (j = 0; j < 256; j++) 332 *gamma_table_base++ = j; 333 334 if (gamma_fix == 1) { /* fix the gamma */ 335 gamma_table_base = gamma.vaddr; 336 for (i = 0; i < 256 * 3; i++) { 337 gamma_table_base[i] = (gamma_table_base[i] << 2) 338 | ((gamma_table_base[i] >> 6) & 0x03); 339 } 340 } 341 342 /* Initialize the cursor */ 343 if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) { 344 printf("DIU: Can't alloc cursor data\n"); 345 return -1; 346 } 347 348 /* Program DIU registers */ 349 out_be32(&hw->diu_mode, 0); /* Temporarily disable the DIU */ 350 351 out_be32(&hw->gamma, gamma.paddr); 352 out_be32(&hw->cursor, cursor.paddr); 353 out_be32(&hw->bgnd, 0x007F7F7F); 354 out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres); 355 out_be32(&hw->hsyn_para, info.var.left_margin << 22 | 356 info.var.hsync_len << 11 | 357 info.var.right_margin); 358 359 out_be32(&hw->vsyn_para, info.var.upper_margin << 22 | 360 info.var.vsync_len << 11 | 361 info.var.lower_margin); 362 363 /* Pixel Clock configuration */ 364 diu_set_pixel_clock(info.var.pixclock); 365 366 /* Set the frame buffers */ 367 out_be32(&hw->desc[0], virt_to_phys(ad)); 368 out_be32(&hw->desc[1], 0); 369 out_be32(&hw->desc[2], 0); 370 371 /* Enable the DIU, set display to all three planes */ 372 out_be32(&hw->diu_mode, 1); 373 374 return 0; 375 } 376 377 void *video_hw_init(void) 378 { 379 static GraphicDevice ctfb; 380 const char *options; 381 unsigned int depth = 0, freq = 0; 382 383 if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, 384 &options)) 385 return NULL; 386 387 /* Find the monitor port, which is a required option */ 388 if (!options) 389 return NULL; 390 if (strncmp(options, "monitor=", 8) != 0) 391 return NULL; 392 393 if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0) 394 return NULL; 395 396 /* fill in Graphic device struct */ 397 sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", 398 ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq); 399 400 ctfb.frameAdrs = (unsigned int)info.screen_base; 401 ctfb.plnSizeX = ctfb.winSizeX; 402 ctfb.plnSizeY = ctfb.winSizeY; 403 404 ctfb.gdfBytesPP = 4; 405 ctfb.gdfIndex = GDF_32BIT_X888RGB; 406 407 ctfb.isaBase = 0; 408 ctfb.pciBase = 0; 409 ctfb.memSize = info.screen_size; 410 411 /* Cursor Start Address */ 412 ctfb.dprBase = 0; 413 ctfb.vprBase = 0; 414 ctfb.cprBase = 0; 415 416 return &ctfb; 417 } 418