xref: /openbmc/u-boot/drivers/video/fsl_diu_fb.c (revision 4d91a6ec)
1 /*
2  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
3  * Authors: York Sun <yorksun@freescale.com>
4  *          Timur Tabi <timur@freescale.com>
5  *
6  * FSL DIU Framebuffer driver
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #include <common.h>
28 #include <malloc.h>
29 #include <asm/io.h>
30 
31 #include "videomodes.h"
32 #include <video_fb.h>
33 #include <fsl_diu_fb.h>
34 #include <linux/list.h>
35 #include <linux/fb.h>
36 
37 /* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
38 static struct fb_videomode fsl_diu_mode_800_480 = {
39 	.name		= "800x480-60",
40 	.refresh	= 60,
41 	.xres		= 800,
42 	.yres		= 480,
43 	.pixclock	= 31250,
44 	.left_margin	= 86,
45 	.right_margin	= 42,
46 	.upper_margin	= 33,
47 	.lower_margin	= 10,
48 	.hsync_len	= 128,
49 	.vsync_len	= 2,
50 	.sync		= 0,
51 	.vmode		= FB_VMODE_NONINTERLACED
52 };
53 
54 /* For the SHARP LQ084S3LG01, used on the P1022DS board */
55 static struct fb_videomode fsl_diu_mode_800_600 = {
56 	.name		= "800x600-60",
57 	.refresh	= 60,
58 	.xres		= 800,
59 	.yres		= 600,
60 	.pixclock	= 25000,
61 	.left_margin	= 88,
62 	.right_margin	= 40,
63 	.upper_margin	= 23,
64 	.lower_margin	= 1,
65 	.hsync_len	= 128,
66 	.vsync_len	= 4,
67 	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
68 	.vmode		= FB_VMODE_NONINTERLACED
69 };
70 
71 /*
72  * These parameters give default parameters
73  * for video output 1024x768,
74  * FIXME - change timing to proper amounts
75  * hsync 31.5kHz, vsync 60Hz
76  */
77 static struct fb_videomode fsl_diu_mode_1024_768 = {
78 	.name		= "1024x768-60",
79 	.refresh	= 60,
80 	.xres		= 1024,
81 	.yres		= 768,
82 	.pixclock	= 15385,
83 	.left_margin	= 160,
84 	.right_margin	= 24,
85 	.upper_margin	= 29,
86 	.lower_margin	= 3,
87 	.hsync_len	= 136,
88 	.vsync_len	= 6,
89 	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
90 	.vmode		= FB_VMODE_NONINTERLACED
91 };
92 
93 static struct fb_videomode fsl_diu_mode_1280_1024 = {
94 	.name		= "1280x1024-60",
95 	.refresh	= 60,
96 	.xres		= 1280,
97 	.yres		= 1024,
98 	.pixclock	= 9375,
99 	.left_margin	= 38,
100 	.right_margin	= 128,
101 	.upper_margin	= 2,
102 	.lower_margin	= 7,
103 	.hsync_len	= 216,
104 	.vsync_len	= 37,
105 	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
106 	.vmode		= FB_VMODE_NONINTERLACED
107 };
108 
109 /*
110  * These are the fields of area descriptor(in DDR memory) for every plane
111  */
112 struct diu_ad {
113 	/* Word 0(32-bit) in DDR memory */
114 	__le32 pix_fmt; /* hard coding pixel format */
115 	/* Word 1(32-bit) in DDR memory */
116 	__le32 addr;
117 	/* Word 2(32-bit) in DDR memory */
118 	__le32 src_size_g_alpha;
119 	/* Word 3(32-bit) in DDR memory */
120 	__le32 aoi_size;
121 	/* Word 4(32-bit) in DDR memory */
122 	__le32 offset_xyi;
123 	/* Word 5(32-bit) in DDR memory */
124 	__le32 offset_xyd;
125 	/* Word 6(32-bit) in DDR memory */
126 	__le32 ckmax_r:8;
127 	__le32 ckmax_g:8;
128 	__le32 ckmax_b:8;
129 	__le32 res9:8;
130 	/* Word 7(32-bit) in DDR memory */
131 	__le32 ckmin_r:8;
132 	__le32 ckmin_g:8;
133 	__le32 ckmin_b:8;
134 	__le32 res10:8;
135 	/* Word 8(32-bit) in DDR memory */
136 	__le32 next_ad;
137 	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
138 	__le32 res[3];
139 } __attribute__ ((packed));
140 
141 /*
142  * DIU register map
143  */
144 struct diu {
145 	__be32 desc[3];
146 	__be32 gamma;
147 	__be32 pallete;
148 	__be32 cursor;
149 	__be32 curs_pos;
150 	__be32 diu_mode;
151 	__be32 bgnd;
152 	__be32 bgnd_wb;
153 	__be32 disp_size;
154 	__be32 wb_size;
155 	__be32 wb_mem_addr;
156 	__be32 hsyn_para;
157 	__be32 vsyn_para;
158 	__be32 syn_pol;
159 	__be32 thresholds;
160 	__be32 int_status;
161 	__be32 int_mask;
162 	__be32 colorbar[8];
163 	__be32 filling;
164 	__be32 plut;
165 } __attribute__ ((packed));
166 
167 struct diu_addr {
168 	void *vaddr;		/* Virtual address */
169 	u32 paddr;		/* 32-bit physical address */
170 	unsigned int offset;	/* Alignment offset */
171 };
172 
173 static struct fb_info info;
174 
175 /*
176  * Align to 64-bit(8-byte), 32-byte, etc.
177  */
178 static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
179 {
180 	u32 offset, ssize;
181 	u32 mask;
182 
183 	ssize = size + bytes_align;
184 	buf->vaddr = malloc(ssize);
185 	if (!buf->vaddr)
186 		return -1;
187 
188 	memset(buf->vaddr, 0, ssize);
189 	mask = bytes_align - 1;
190 	offset = (u32)buf->vaddr & mask;
191 	if (offset) {
192 		buf->offset = bytes_align - offset;
193 		buf->vaddr += offset;
194 	} else
195 		buf->offset = 0;
196 
197 	buf->paddr = virt_to_phys(buf->vaddr);
198 	return 0;
199 }
200 
201 /*
202  * Allocate a framebuffer and an Area Descriptor that points to it.  Both
203  * are created in the same memory block.  The Area Descriptor is updated to
204  * point to the framebuffer memory. Memory is aligned as needed.
205  */
206 static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres,
207 				  unsigned int depth, char **fb)
208 {
209 	unsigned long size = xres * yres * depth;
210 	struct diu_addr addr;
211 	struct diu_ad *ad;
212 	size_t ad_size = roundup(sizeof(struct diu_ad), 32);
213 
214 	/*
215 	 * Allocate a memory block that holds the Area Descriptor and the
216 	 * frame buffer right behind it.  To keep the code simple, everything
217 	 * is aligned on a 32-byte address.
218 	 */
219 	if (allocate_buf(&addr, ad_size + size, 32) < 0)
220 		return NULL;
221 
222 	ad = addr.vaddr;
223 	ad->addr = cpu_to_le32(addr.paddr + ad_size);
224 	ad->aoi_size = cpu_to_le32((yres << 16) | xres);
225 	ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres);
226 	ad->offset_xyi = 0;
227 	ad->offset_xyd = 0;
228 
229 	if (fb)
230 		*fb = addr.vaddr + ad_size;
231 
232 	return ad;
233 }
234 
235 int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix)
236 {
237 	struct fb_videomode *fsl_diu_mode_db;
238 	struct diu_ad *ad;
239 	struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR;
240 	u8 *gamma_table_base;
241 	unsigned int i, j;
242 	struct diu_ad *dummy_ad;
243 	struct diu_addr gamma;
244 	struct diu_addr cursor;
245 
246 /* Convert the X,Y resolution pair into a single number */
247 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
248 
249 	switch (RESOLUTION(xres, yres)) {
250 	case RESOLUTION(800, 480):
251 		fsl_diu_mode_db = &fsl_diu_mode_800_480;
252 		break;
253 	case RESOLUTION(800, 600):
254 		fsl_diu_mode_db = &fsl_diu_mode_800_600;
255 	case RESOLUTION(1024, 768):
256 		fsl_diu_mode_db = &fsl_diu_mode_1024_768;
257 	case RESOLUTION(1280, 1024):
258 		fsl_diu_mode_db = &fsl_diu_mode_1280_1024;
259 		break;
260 	default:
261 		printf("DIU:   Unsupported resolution %ux%u\n", xres, yres);
262 		return -1;
263 	}
264 
265 	/* The AD struct for the dummy framebuffer and the FB itself */
266 	dummy_ad = allocate_fb(2, 4, 4, NULL);
267 	if (!dummy_ad) {
268 		printf("DIU:   Out of memory\n");
269 		return -1;
270 	}
271 	dummy_ad->pix_fmt = 0x88883316;
272 
273 	/* read mode info */
274 	info.var.xres = fsl_diu_mode_db->xres;
275 	info.var.yres = fsl_diu_mode_db->yres;
276 	info.var.bits_per_pixel = 32;
277 	info.var.pixclock = fsl_diu_mode_db->pixclock;
278 	info.var.left_margin = fsl_diu_mode_db->left_margin;
279 	info.var.right_margin = fsl_diu_mode_db->right_margin;
280 	info.var.upper_margin = fsl_diu_mode_db->upper_margin;
281 	info.var.lower_margin = fsl_diu_mode_db->lower_margin;
282 	info.var.hsync_len = fsl_diu_mode_db->hsync_len;
283 	info.var.vsync_len = fsl_diu_mode_db->vsync_len;
284 	info.var.sync = fsl_diu_mode_db->sync;
285 	info.var.vmode = fsl_diu_mode_db->vmode;
286 	info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
287 
288 	/* Memory allocation for framebuffer */
289 	info.screen_size =
290 		info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
291 	ad = allocate_fb(info.var.xres, info.var.yres,
292 			 info.var.bits_per_pixel / 8, &info.screen_base);
293 	if (!ad) {
294 		printf("DIU:   Out of memory\n");
295 		return -1;
296 	}
297 
298 	ad->pix_fmt = pixel_format;
299 
300 	/* Disable chroma keying function */
301 	ad->ckmax_r = 0;
302 	ad->ckmax_g = 0;
303 	ad->ckmax_b = 0;
304 
305 	ad->ckmin_r = 255;
306 	ad->ckmin_g = 255;
307 	ad->ckmin_b = 255;
308 
309 	/* Initialize the gamma table */
310 	if (allocate_buf(&gamma, 256 * 3, 32) < 0) {
311 		printf("DIU:   Out of memory\n");
312 		return -1;
313 	}
314 	gamma_table_base = gamma.vaddr;
315 	for (i = 0; i <= 2; i++)
316 		for (j = 0; j < 256; j++)
317 			*gamma_table_base++ = j;
318 
319 	if (gamma_fix == 1) {	/* fix the gamma */
320 		gamma_table_base = gamma.vaddr;
321 		for (i = 0; i < 256 * 3; i++) {
322 			gamma_table_base[i] = (gamma_table_base[i] << 2)
323 				| ((gamma_table_base[i] >> 6) & 0x03);
324 		}
325 	}
326 
327 	/* Initialize the cursor */
328 	if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) {
329 		printf("DIU:   Can't alloc cursor data\n");
330 		return -1;
331 	}
332 
333 	/* Program DIU registers */
334 	out_be32(&hw->diu_mode, 0);	/* Temporarily disable the DIU */
335 
336 	out_be32(&hw->gamma, gamma.paddr);
337 	out_be32(&hw->cursor, cursor.paddr);
338 	out_be32(&hw->bgnd, 0x007F7F7F);
339 	out_be32(&hw->bgnd_wb, 0);
340 	out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres);
341 	out_be32(&hw->wb_size, 0);
342 	out_be32(&hw->wb_mem_addr, 0);
343 	out_be32(&hw->hsyn_para, info.var.left_margin << 22 |
344 			info.var.hsync_len << 11 |
345 			info.var.right_margin);
346 
347 	out_be32(&hw->vsyn_para, info.var.upper_margin << 22 |
348 			info.var.vsync_len << 11 |
349 			info.var.lower_margin);
350 
351 	out_be32(&hw->syn_pol, 0);
352 	out_be32(&hw->thresholds, 0x00037800);
353 	out_be32(&hw->int_status, 0);
354 	out_be32(&hw->int_mask, 0);
355 	out_be32(&hw->plut, 0x01F5F666);
356 	/* Pixel Clock configuration */
357 	diu_set_pixel_clock(info.var.pixclock);
358 
359 	/* Set the frame buffers */
360 	out_be32(&hw->desc[0], virt_to_phys(ad));
361 	out_be32(&hw->desc[1], virt_to_phys(dummy_ad));
362 	out_be32(&hw->desc[2], virt_to_phys(dummy_ad));
363 
364 	/* Enable the DIU, set display to all three planes */
365 	out_be32(&hw->diu_mode, 1);
366 
367 	return 0;
368 }
369 
370 void *video_hw_init(void)
371 {
372 	static GraphicDevice ctfb;
373 	const char *options;
374 	unsigned int depth = 0, freq = 0;
375 
376 	if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
377 				  &options))
378 		return NULL;
379 
380 	/* Find the monitor port, which is a required option */
381 	if (!options)
382 		return NULL;
383 	if (strncmp(options, "monitor=", 8) != 0)
384 		return NULL;
385 
386 	if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0)
387 		return NULL;
388 
389 	/* fill in Graphic device struct */
390 	sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
391 		ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq);
392 
393 	ctfb.frameAdrs = (unsigned int)info.screen_base;
394 	ctfb.plnSizeX = ctfb.winSizeX;
395 	ctfb.plnSizeY = ctfb.winSizeY;
396 
397 	ctfb.gdfBytesPP = 4;
398 	ctfb.gdfIndex = GDF_32BIT_X888RGB;
399 
400 	ctfb.isaBase = 0;
401 	ctfb.pciBase = 0;
402 	ctfb.memSize = info.screen_size;
403 
404 	/* Cursor Start Address */
405 	ctfb.dprBase = 0;
406 	ctfb.vprBase = 0;
407 	ctfb.cprBase = 0;
408 
409 	return &ctfb;
410 }
411