1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * Author: InKi Dae <inki.dae@samsung.com> 5 * Author: Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/dsim.h> 12 #include <asm/arch/mipi_dsim.h> 13 #include <asm/arch/power.h> 14 #include <asm/arch/cpu.h> 15 16 #include "exynos_mipi_dsi_lowlevel.h" 17 #include "exynos_mipi_dsi_common.h" 18 19 void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) 20 { 21 unsigned int reg; 22 23 struct exynos_mipi_dsim *mipi_dsim = 24 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 25 26 reg = readl(&mipi_dsim->swrst); 27 28 reg |= DSIM_FUNCRST; 29 30 writel(reg, &mipi_dsim->swrst); 31 } 32 33 void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) 34 { 35 unsigned int reg = 0; 36 37 struct exynos_mipi_dsim *mipi_dsim = 38 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 39 40 reg = readl(&mipi_dsim->swrst); 41 42 reg |= DSIM_SWRST; 43 reg |= DSIM_FUNCRST; 44 45 writel(reg, &mipi_dsim->swrst); 46 } 47 48 void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim) 49 { 50 struct exynos_mipi_dsim *mipi_dsim = 51 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 52 unsigned int reg = readl(&mipi_dsim->intsrc); 53 54 reg |= INTSRC_SWRST_RELEASE; 55 56 writel(reg, &mipi_dsim->intsrc); 57 } 58 59 void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, 60 unsigned int mode, unsigned int mask) 61 { 62 struct exynos_mipi_dsim *mipi_dsim = 63 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 64 unsigned int reg = readl(&mipi_dsim->intmsk); 65 66 if (mask) 67 reg |= mode; 68 else 69 reg &= ~mode; 70 71 writel(reg, &mipi_dsim->intmsk); 72 } 73 74 void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, 75 unsigned int cfg) 76 { 77 unsigned int reg; 78 struct exynos_mipi_dsim *mipi_dsim = 79 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 80 81 reg = readl(&mipi_dsim->fifoctrl); 82 83 writel(reg & ~(cfg), &mipi_dsim->fifoctrl); 84 udelay(10 * 1000); 85 reg |= cfg; 86 87 writel(reg, &mipi_dsim->fifoctrl); 88 } 89 90 /* 91 * this function set PLL P, M and S value in D-PHY 92 */ 93 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, 94 unsigned int value) 95 { 96 struct exynos_mipi_dsim *mipi_dsim = 97 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 98 99 writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr); 100 } 101 102 void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, 103 unsigned int width_resol, unsigned int height_resol) 104 { 105 unsigned int reg; 106 struct exynos_mipi_dsim *mipi_dsim = 107 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 108 109 /* standby should be set after configuration so set to not ready*/ 110 reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); 111 writel(reg, &mipi_dsim->mdresol); 112 113 /* reset resolution */ 114 reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff)); 115 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); 116 117 reg |= DSIM_MAIN_STAND_BY; 118 writel(reg, &mipi_dsim->mdresol); 119 } 120 121 void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, 122 unsigned int cmd_allow, unsigned int vfront, unsigned int vback) 123 { 124 unsigned int reg; 125 struct exynos_mipi_dsim *mipi_dsim = 126 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 127 128 reg = (readl(&mipi_dsim->mvporch)) & 129 ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) | 130 (DSIM_MAIN_VBP_MASK)); 131 132 reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | 133 ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) | 134 ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT); 135 136 writel(reg, &mipi_dsim->mvporch); 137 } 138 139 void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, 140 unsigned int front, unsigned int back) 141 { 142 unsigned int reg; 143 struct exynos_mipi_dsim *mipi_dsim = 144 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 145 146 reg = (readl(&mipi_dsim->mhporch)) & 147 ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK)); 148 149 reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); 150 151 writel(reg, &mipi_dsim->mhporch); 152 } 153 154 void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, 155 unsigned int vert, unsigned int hori) 156 { 157 unsigned int reg; 158 struct exynos_mipi_dsim *mipi_dsim = 159 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 160 161 reg = (readl(&mipi_dsim->msync)) & 162 ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK)); 163 164 reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | 165 (hori << DSIM_MAIN_HSA_SHIFT); 166 167 writel(reg, &mipi_dsim->msync); 168 } 169 170 void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, 171 unsigned int vert, unsigned int hori) 172 { 173 unsigned int reg; 174 struct exynos_mipi_dsim *mipi_dsim = 175 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 176 177 reg = (readl(&mipi_dsim->sdresol)) & 178 ~(DSIM_SUB_STANDY_MASK); 179 180 writel(reg, &mipi_dsim->sdresol); 181 182 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); 183 reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | 184 ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT); 185 writel(reg, &mipi_dsim->sdresol); 186 187 /* DSIM STANDBY */ 188 reg |= (1 << DSIM_SUB_STANDY_SHIFT); 189 writel(reg, &mipi_dsim->sdresol); 190 } 191 192 void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim) 193 { 194 struct mipi_dsim_config *dsim_config = dsim->dsim_config; 195 struct exynos_mipi_dsim *mipi_dsim = 196 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 197 unsigned int cfg = (readl(&mipi_dsim->config)) & 198 ~((1 << DSIM_EOT_PACKET_SHIFT) | 199 (0x1f << DSIM_HSA_MODE_SHIFT) | 200 (0x3 << DSIM_NUM_OF_DATALANE_SHIFT)); 201 202 cfg |= (dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) | 203 (dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) | 204 (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) | 205 (dsim_config->hse << DSIM_HSE_MODE_SHIFT) | 206 (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) | 207 (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) | 208 (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) | 209 (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT); 210 211 writel(cfg, &mipi_dsim->config); 212 } 213 214 void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, 215 struct mipi_dsim_config *dsim_config) 216 { 217 struct exynos_mipi_dsim *mipi_dsim = 218 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 219 220 u32 reg = (readl(&mipi_dsim->config)) & 221 ~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT) 222 | (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT) 223 | (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT)); 224 225 if (dsim_config->e_interface == DSIM_VIDEO) 226 reg |= (1 << DSIM_VIDEO_MODE_SHIFT); 227 else if (dsim_config->e_interface == DSIM_COMMAND) 228 reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT); 229 else { 230 printf("unknown lcd type.\n"); 231 return; 232 } 233 234 /* main lcd */ 235 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT 236 | ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT 237 | ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT; 238 239 writel(reg, &mipi_dsim->config); 240 } 241 242 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, 243 unsigned int lane, unsigned int enable) 244 { 245 unsigned int reg; 246 struct exynos_mipi_dsim *mipi_dsim = 247 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 248 249 reg = readl(&mipi_dsim->config); 250 251 if (enable) 252 reg |= DSIM_LANE_ENx(lane); 253 else 254 reg &= ~DSIM_LANE_ENx(lane); 255 256 writel(reg, &mipi_dsim->config); 257 } 258 259 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, 260 unsigned int count) 261 { 262 unsigned int cfg; 263 struct exynos_mipi_dsim *mipi_dsim = 264 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 265 266 /* get the data lane number. */ 267 cfg = DSIM_NUM_OF_DATA_LANE(count); 268 269 writel(cfg, &mipi_dsim->config); 270 } 271 272 void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, 273 unsigned int enable, unsigned int afc_code) 274 { 275 struct exynos_mipi_dsim *mipi_dsim = 276 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 277 unsigned int reg = readl(&mipi_dsim->phyacchr); 278 279 reg = 0; 280 281 if (enable) { 282 reg |= DSIM_AFC_EN; 283 reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT); 284 reg |= DSIM_AFC_CTL(afc_code); 285 } else 286 reg &= ~DSIM_AFC_EN; 287 288 writel(reg, &mipi_dsim->phyacchr); 289 } 290 291 void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, 292 unsigned int enable) 293 { 294 struct exynos_mipi_dsim *mipi_dsim = 295 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 296 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 297 ~(DSIM_PLL_BYPASS_EXTERNAL); 298 299 reg |= enable << DSIM_PLL_BYPASS_SHIFT; 300 301 writel(reg, &mipi_dsim->clkctrl); 302 } 303 304 void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, 305 unsigned int freq_band) 306 { 307 struct exynos_mipi_dsim *mipi_dsim = 308 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 309 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 310 ~(0x1f << DSIM_FREQ_BAND_SHIFT); 311 312 reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); 313 314 writel(reg, &mipi_dsim->pllctrl); 315 } 316 317 void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, 318 unsigned int pre_divider, unsigned int main_divider, 319 unsigned int scaler) 320 { 321 struct exynos_mipi_dsim *mipi_dsim = 322 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 323 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 324 ~(0x7ffff << 1); 325 326 reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) | 327 ((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) | 328 ((scaler & 0x7) << DSIM_SCALER_SHIFT); 329 330 writel(reg, &mipi_dsim->pllctrl); 331 } 332 333 void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, 334 unsigned int lock_time) 335 { 336 struct exynos_mipi_dsim *mipi_dsim = 337 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 338 339 writel(lock_time, &mipi_dsim->plltmr); 340 } 341 342 void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, 343 unsigned int enable) 344 { 345 struct exynos_mipi_dsim *mipi_dsim = 346 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 347 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 348 ~(0x1 << DSIM_PLL_EN_SHIFT); 349 350 reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); 351 352 writel(reg, &mipi_dsim->pllctrl); 353 } 354 355 void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, 356 unsigned int src) 357 { 358 struct exynos_mipi_dsim *mipi_dsim = 359 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 360 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 361 ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT); 362 363 reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; 364 365 writel(reg, &mipi_dsim->clkctrl); 366 } 367 368 void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, 369 unsigned int enable) 370 { 371 struct exynos_mipi_dsim *mipi_dsim = 372 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 373 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 374 ~(1 << DSIM_BYTE_CLKEN_SHIFT); 375 376 reg |= enable << DSIM_BYTE_CLKEN_SHIFT; 377 378 writel(reg, &mipi_dsim->clkctrl); 379 } 380 381 void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, 382 unsigned int enable, unsigned int prs_val) 383 { 384 struct exynos_mipi_dsim *mipi_dsim = 385 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 386 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 387 ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff)); 388 389 reg |= enable << DSIM_ESC_CLKEN_SHIFT; 390 if (enable) 391 reg |= prs_val; 392 393 writel(reg, &mipi_dsim->clkctrl); 394 } 395 396 void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, 397 unsigned int lane_sel, unsigned int enable) 398 { 399 struct exynos_mipi_dsim *mipi_dsim = 400 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 401 unsigned int reg = readl(&mipi_dsim->clkctrl); 402 403 if (enable) 404 reg |= DSIM_LANE_ESC_CLKEN(lane_sel); 405 else 406 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); 407 408 writel(reg, &mipi_dsim->clkctrl); 409 } 410 411 void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, 412 unsigned int enable) 413 { 414 struct exynos_mipi_dsim *mipi_dsim = 415 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 416 unsigned int reg = (readl(&mipi_dsim->escmode)) & 417 ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT); 418 419 reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); 420 421 writel(reg, &mipi_dsim->escmode); 422 } 423 424 unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) 425 { 426 struct exynos_mipi_dsim *mipi_dsim = 427 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 428 unsigned int reg = readl(&mipi_dsim->status); 429 430 /** 431 * check clock and data lane states. 432 * if MIPI-DSI controller was enabled at bootloader then 433 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK. 434 * so it should be checked for two case. 435 */ 436 if ((reg & DSIM_STOP_STATE_DAT(0xf)) && 437 ((reg & DSIM_STOP_STATE_CLK) || 438 (reg & DSIM_TX_READY_HS_CLK))) 439 return 1; 440 else 441 return 0; 442 } 443 444 void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, 445 unsigned int cnt_val) 446 { 447 struct exynos_mipi_dsim *mipi_dsim = 448 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 449 unsigned int reg = (readl(&mipi_dsim->escmode)) & 450 ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT); 451 452 reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); 453 454 writel(reg, &mipi_dsim->escmode); 455 } 456 457 void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, 458 unsigned int timeout) 459 { 460 struct exynos_mipi_dsim *mipi_dsim = 461 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 462 unsigned int reg = (readl(&mipi_dsim->timeout)) & 463 ~(0xff << DSIM_BTA_TOUT_SHIFT); 464 465 reg |= (timeout << DSIM_BTA_TOUT_SHIFT); 466 467 writel(reg, &mipi_dsim->timeout); 468 } 469 470 void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, 471 unsigned int timeout) 472 { 473 struct exynos_mipi_dsim *mipi_dsim = 474 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 475 unsigned int reg = (readl(&mipi_dsim->timeout)) & 476 ~(0xffff << DSIM_LPDR_TOUT_SHIFT); 477 478 reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); 479 480 writel(reg, &mipi_dsim->timeout); 481 } 482 483 void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, 484 unsigned int lp) 485 { 486 struct exynos_mipi_dsim *mipi_dsim = 487 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 488 unsigned int reg = readl(&mipi_dsim->escmode); 489 490 reg &= ~DSIM_CMD_LPDT_LP; 491 492 if (lp) 493 reg |= DSIM_CMD_LPDT_LP; 494 495 writel(reg, &mipi_dsim->escmode); 496 } 497 498 void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, 499 unsigned int lp) 500 { 501 struct exynos_mipi_dsim *mipi_dsim = 502 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 503 unsigned int reg = readl(&mipi_dsim->escmode); 504 505 reg &= ~DSIM_TX_LPDT_LP; 506 507 if (lp) 508 reg |= DSIM_TX_LPDT_LP; 509 510 writel(reg, &mipi_dsim->escmode); 511 } 512 513 void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, 514 unsigned int enable) 515 { 516 struct exynos_mipi_dsim *mipi_dsim = 517 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 518 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & 519 ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT); 520 521 reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; 522 523 writel(reg, &mipi_dsim->clkctrl); 524 } 525 526 void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, 527 unsigned int swap_en) 528 { 529 struct exynos_mipi_dsim *mipi_dsim = 530 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 531 unsigned int reg = readl(&mipi_dsim->phyacchr1); 532 533 reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT); 534 reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT; 535 536 writel(reg, &mipi_dsim->phyacchr1); 537 } 538 539 void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, 540 unsigned int hs_zero) 541 { 542 struct exynos_mipi_dsim *mipi_dsim = 543 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 544 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 545 ~(0xf << DSIM_ZEROCTRL_SHIFT); 546 547 reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT); 548 549 writel(reg, &mipi_dsim->pllctrl); 550 } 551 552 void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) 553 { 554 struct exynos_mipi_dsim *mipi_dsim = 555 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 556 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & 557 ~(0x7 << DSIM_PRECTRL_SHIFT); 558 559 reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT); 560 561 writel(reg, &mipi_dsim->pllctrl); 562 } 563 564 void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim) 565 { 566 struct exynos_mipi_dsim *mipi_dsim = 567 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 568 unsigned int reg = readl(&mipi_dsim->intsrc); 569 570 reg |= INTSRC_PLL_STABLE; 571 572 writel(reg, &mipi_dsim->intsrc); 573 } 574 575 void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim) 576 { 577 struct exynos_mipi_dsim *mipi_dsim = 578 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 579 580 writel(0xffffffff, &mipi_dsim->intsrc); 581 } 582 583 unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) 584 { 585 unsigned int reg; 586 struct exynos_mipi_dsim *mipi_dsim = 587 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 588 589 reg = readl(&mipi_dsim->status); 590 591 return reg & DSIM_PLL_STABLE ? 1 : 0; 592 } 593 594 unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) 595 { 596 struct exynos_mipi_dsim *mipi_dsim = 597 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 598 599 return readl(&mipi_dsim->fifoctrl) & ~(0x1f); 600 } 601 602 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, 603 unsigned int di, const unsigned char data0, const unsigned char data1) 604 { 605 struct exynos_mipi_dsim *mipi_dsim = 606 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 607 unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) | 608 DSIM_PKTHDR_DI(di)); 609 610 writel(reg, &mipi_dsim->pkthdr); 611 } 612 613 unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device 614 *dsim) 615 { 616 struct exynos_mipi_dsim *mipi_dsim = 617 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 618 unsigned int reg = readl(&mipi_dsim->intsrc); 619 620 return (reg & INTSRC_FRAME_DONE) ? 1 : 0; 621 } 622 623 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) 624 { 625 struct exynos_mipi_dsim *mipi_dsim = 626 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 627 unsigned int reg = readl(&mipi_dsim->intsrc); 628 629 writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc); 630 } 631 632 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, 633 unsigned int tx_data) 634 { 635 struct exynos_mipi_dsim *mipi_dsim = 636 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); 637 638 writel(tx_data, &mipi_dsim->payload); 639 } 640