1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * Author: Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <common.h> 12 #include <display.h> 13 #include <fdtdec.h> 14 #include <libfdt.h> 15 #include <malloc.h> 16 #include <video_bridge.h> 17 #include <linux/compat.h> 18 #include <linux/err.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/dp_info.h> 22 #include <asm/arch/dp.h> 23 #include <asm/arch/pinmux.h> 24 #include <asm/arch/power.h> 25 26 #include "exynos_dp_lowlevel.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 static void exynos_dp_disp_info(struct edp_disp_info *disp_info) 31 { 32 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + 33 disp_info->h_back_porch + disp_info->h_front_porch; 34 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + 35 disp_info->v_back_porch + disp_info->v_front_porch; 36 37 return; 38 } 39 40 static int exynos_dp_init_dp(struct exynos_dp *regs) 41 { 42 int ret; 43 exynos_dp_reset(regs); 44 45 /* SW defined function Normal operation */ 46 exynos_dp_enable_sw_func(regs, DP_ENABLE); 47 48 ret = exynos_dp_init_analog_func(regs); 49 if (ret != EXYNOS_DP_SUCCESS) 50 return ret; 51 52 exynos_dp_init_hpd(regs); 53 exynos_dp_init_aux(regs); 54 55 return ret; 56 } 57 58 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) 59 { 60 int i; 61 unsigned char sum = 0; 62 63 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 64 sum = sum + edid_data[i]; 65 66 return sum; 67 } 68 69 static unsigned int exynos_dp_read_edid(struct exynos_dp *regs) 70 { 71 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 72 unsigned int extend_block = 0; 73 unsigned char sum; 74 unsigned char test_vector; 75 int retval; 76 77 /* 78 * EDID device address is 0x50. 79 * However, if necessary, you must have set upper address 80 * into E-EDID in I2C device, 0x30. 81 */ 82 83 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 84 exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR, 85 EDID_EXTENSION_FLAG, &extend_block); 86 87 if (extend_block > 0) { 88 printf("DP EDID data includes a single extension!\n"); 89 90 /* Read EDID data */ 91 retval = exynos_dp_read_bytes_from_i2c(regs, 92 I2C_EDID_DEVICE_ADDR, 93 EDID_HEADER_PATTERN, 94 EDID_BLOCK_LENGTH, 95 &edid[EDID_HEADER_PATTERN]); 96 if (retval != 0) { 97 printf("DP EDID Read failed!\n"); 98 return -1; 99 } 100 sum = exynos_dp_calc_edid_check_sum(edid); 101 if (sum != 0) { 102 printf("DP EDID bad checksum!\n"); 103 return -1; 104 } 105 106 /* Read additional EDID data */ 107 retval = exynos_dp_read_bytes_from_i2c(regs, 108 I2C_EDID_DEVICE_ADDR, 109 EDID_BLOCK_LENGTH, 110 EDID_BLOCK_LENGTH, 111 &edid[EDID_BLOCK_LENGTH]); 112 if (retval != 0) { 113 printf("DP EDID Read failed!\n"); 114 return -1; 115 } 116 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); 117 if (sum != 0) { 118 printf("DP EDID bad checksum!\n"); 119 return -1; 120 } 121 122 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, 123 &test_vector); 124 if (test_vector & DPCD_TEST_EDID_READ) { 125 exynos_dp_write_byte_to_dpcd(regs, 126 DPCD_TEST_EDID_CHECKSUM, 127 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 128 exynos_dp_write_byte_to_dpcd(regs, 129 DPCD_TEST_RESPONSE, 130 DPCD_TEST_EDID_CHECKSUM_WRITE); 131 } 132 } else { 133 debug("DP EDID data does not include any extensions.\n"); 134 135 /* Read EDID data */ 136 retval = exynos_dp_read_bytes_from_i2c(regs, 137 I2C_EDID_DEVICE_ADDR, 138 EDID_HEADER_PATTERN, 139 EDID_BLOCK_LENGTH, 140 &edid[EDID_HEADER_PATTERN]); 141 142 if (retval != 0) { 143 printf("DP EDID Read failed!\n"); 144 return -1; 145 } 146 sum = exynos_dp_calc_edid_check_sum(edid); 147 if (sum != 0) { 148 printf("DP EDID bad checksum!\n"); 149 return -1; 150 } 151 152 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, 153 &test_vector); 154 if (test_vector & DPCD_TEST_EDID_READ) { 155 exynos_dp_write_byte_to_dpcd(regs, 156 DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 157 exynos_dp_write_byte_to_dpcd(regs, 158 DPCD_TEST_RESPONSE, 159 DPCD_TEST_EDID_CHECKSUM_WRITE); 160 } 161 } 162 163 debug("DP EDID Read success!\n"); 164 165 return 0; 166 } 167 168 static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs, 169 struct exynos_dp_priv *priv) 170 { 171 unsigned char buf[12]; 172 unsigned int ret; 173 unsigned char temp; 174 unsigned char retry_cnt; 175 unsigned char dpcd_rev[16]; 176 unsigned char lane_bw[16]; 177 unsigned char lane_cnt[16]; 178 179 memset(dpcd_rev, 0, 16); 180 memset(lane_bw, 0, 16); 181 memset(lane_cnt, 0, 16); 182 memset(buf, 0, 12); 183 184 retry_cnt = 5; 185 while (retry_cnt) { 186 /* Read DPCD 0x0000-0x000b */ 187 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12, 188 buf); 189 if (ret != EXYNOS_DP_SUCCESS) { 190 if (retry_cnt == 0) { 191 printf("DP read_byte_from_dpcd() failed\n"); 192 return ret; 193 } 194 retry_cnt--; 195 } else 196 break; 197 } 198 199 /* */ 200 temp = buf[DPCD_DPCD_REV]; 201 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) 202 priv->dpcd_rev = temp; 203 else { 204 printf("DP Wrong DPCD Rev : %x\n", temp); 205 return -ENODEV; 206 } 207 208 temp = buf[DPCD_MAX_LINK_RATE]; 209 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) 210 priv->lane_bw = temp; 211 else { 212 printf("DP Wrong MAX LINK RATE : %x\n", temp); 213 return -EINVAL; 214 } 215 216 /* Refer VESA Display Port Standard Ver1.1a Page 120 */ 217 if (priv->dpcd_rev == DP_DPCD_REV_11) { 218 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; 219 if (buf[DPCD_MAX_LANE_COUNT] & 0x80) 220 priv->dpcd_efc = 1; 221 else 222 priv->dpcd_efc = 0; 223 } else { 224 temp = buf[DPCD_MAX_LANE_COUNT]; 225 priv->dpcd_efc = 0; 226 } 227 228 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || 229 temp == DP_LANE_CNT_4) { 230 priv->lane_cnt = temp; 231 } else { 232 printf("DP Wrong MAX LANE COUNT : %x\n", temp); 233 return -EINVAL; 234 } 235 236 ret = exynos_dp_read_edid(regs); 237 if (ret != EXYNOS_DP_SUCCESS) { 238 printf("DP exynos_dp_read_edid() failed\n"); 239 return -EINVAL; 240 } 241 242 return ret; 243 } 244 245 static void exynos_dp_init_training(struct exynos_dp *regs) 246 { 247 /* 248 * MACRO_RST must be applied after the PLL_LOCK to avoid 249 * the DP inter pair skew issue for at least 10 us 250 */ 251 exynos_dp_reset_macro(regs); 252 253 /* All DP analog module power up */ 254 exynos_dp_set_analog_power_down(regs, POWER_ALL, 0); 255 } 256 257 static unsigned int exynos_dp_link_start(struct exynos_dp *regs, 258 struct exynos_dp_priv *priv) 259 { 260 unsigned char buf[5]; 261 unsigned int ret = 0; 262 263 debug("DP: %s was called\n", __func__); 264 265 priv->lt_info.lt_status = DP_LT_CR; 266 priv->lt_info.ep_loop = 0; 267 priv->lt_info.cr_loop[0] = 0; 268 priv->lt_info.cr_loop[1] = 0; 269 priv->lt_info.cr_loop[2] = 0; 270 priv->lt_info.cr_loop[3] = 0; 271 272 /* Set sink to D0 (Sink Not Ready) mode. */ 273 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE, 274 DPCD_SET_POWER_STATE_D0); 275 if (ret != EXYNOS_DP_SUCCESS) { 276 printf("DP write_dpcd_byte failed\n"); 277 return ret; 278 } 279 280 /* Set link rate and count as you want to establish */ 281 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); 282 exynos_dp_set_lane_count(regs, priv->lane_cnt); 283 284 /* Setup RX configuration */ 285 buf[0] = priv->lane_bw; 286 buf[1] = priv->lane_cnt; 287 288 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf); 289 if (ret != EXYNOS_DP_SUCCESS) { 290 printf("DP write_dpcd_byte failed\n"); 291 return ret; 292 } 293 294 exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0, 295 priv->lane_cnt); 296 297 /* Set training pattern 1 */ 298 exynos_dp_set_training_pattern(regs, TRAINING_PTN1); 299 300 /* Set RX training pattern */ 301 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; 302 303 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 304 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 305 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 306 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 307 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 308 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 309 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 310 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 311 312 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 313 5, buf); 314 if (ret != EXYNOS_DP_SUCCESS) { 315 printf("DP write_dpcd_byte failed\n"); 316 return ret; 317 } 318 319 return ret; 320 } 321 322 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs) 323 { 324 unsigned int ret = EXYNOS_DP_SUCCESS; 325 326 exynos_dp_set_training_pattern(regs, DP_NONE); 327 328 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 329 DPCD_TRAINING_PATTERN_DISABLED); 330 if (ret != EXYNOS_DP_SUCCESS) { 331 printf("DP request_link_training_req failed\n"); 332 return -EAGAIN; 333 } 334 335 return ret; 336 } 337 338 static unsigned int exynos_dp_enable_rx_to_enhanced_mode( 339 struct exynos_dp *regs, unsigned char enable) 340 { 341 unsigned char data; 342 unsigned int ret = EXYNOS_DP_SUCCESS; 343 344 ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET, 345 &data); 346 if (ret != EXYNOS_DP_SUCCESS) { 347 printf("DP read_from_dpcd failed\n"); 348 return -EAGAIN; 349 } 350 351 if (enable) 352 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); 353 else 354 data = DPCD_LN_COUNT_SET(data); 355 356 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data); 357 if (ret != EXYNOS_DP_SUCCESS) { 358 printf("DP write_to_dpcd failed\n"); 359 return -EAGAIN; 360 361 } 362 363 return ret; 364 } 365 366 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs, 367 unsigned char enhance_mode) 368 { 369 unsigned int ret = EXYNOS_DP_SUCCESS; 370 371 ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode); 372 if (ret != EXYNOS_DP_SUCCESS) { 373 printf("DP rx_enhance_mode failed\n"); 374 return -EAGAIN; 375 } 376 377 exynos_dp_enable_enhanced_mode(regs, enhance_mode); 378 379 return ret; 380 } 381 382 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs, 383 struct exynos_dp_priv *priv, 384 unsigned char *status) 385 { 386 unsigned int ret, i; 387 unsigned char buf[2]; 388 unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; 389 unsigned char shift_val[DP_LANE_CNT_4] = {0,}; 390 391 shift_val[0] = 0; 392 shift_val[1] = 4; 393 shift_val[2] = 0; 394 shift_val[3] = 4; 395 396 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2, 397 buf); 398 if (ret != EXYNOS_DP_SUCCESS) { 399 printf("DP read lane status failed\n"); 400 return ret; 401 } 402 403 for (i = 0; i < priv->lane_cnt; i++) { 404 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; 405 if (lane_stat[0] != lane_stat[i]) { 406 printf("Wrong lane status\n"); 407 return -EINVAL; 408 } 409 } 410 411 *status = lane_stat[0]; 412 413 return ret; 414 } 415 416 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs, 417 unsigned char lane_num, unsigned char *sw, unsigned char *em) 418 { 419 unsigned int ret = EXYNOS_DP_SUCCESS; 420 unsigned char buf; 421 unsigned int dpcd_addr; 422 unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; 423 424 /* lane_num value is used as array index, so this range 0 ~ 3 */ 425 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); 426 427 ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf); 428 if (ret != EXYNOS_DP_SUCCESS) { 429 printf("DP read adjust request failed\n"); 430 return -EAGAIN; 431 } 432 433 *sw = ((buf >> shift_val[lane_num]) & 0x03); 434 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; 435 436 return ret; 437 } 438 439 static int exynos_dp_equalizer_err_link(struct exynos_dp *regs, 440 struct exynos_dp_priv *priv) 441 { 442 int ret; 443 444 ret = exynos_dp_training_pattern_dis(regs); 445 if (ret != EXYNOS_DP_SUCCESS) { 446 printf("DP training_pattern_disable() failed\n"); 447 priv->lt_info.lt_status = DP_LT_FAIL; 448 } 449 450 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); 451 if (ret != EXYNOS_DP_SUCCESS) { 452 printf("DP set_enhanced_mode() failed\n"); 453 priv->lt_info.lt_status = DP_LT_FAIL; 454 } 455 456 return ret; 457 } 458 459 static int exynos_dp_reduce_link_rate(struct exynos_dp *regs, 460 struct exynos_dp_priv *priv) 461 { 462 int ret; 463 464 if (priv->lane_bw == DP_LANE_BW_2_70) { 465 priv->lane_bw = DP_LANE_BW_1_62; 466 printf("DP Change lane bw to 1.62Gbps\n"); 467 priv->lt_info.lt_status = DP_LT_START; 468 ret = EXYNOS_DP_SUCCESS; 469 } else { 470 ret = exynos_dp_training_pattern_dis(regs); 471 if (ret != EXYNOS_DP_SUCCESS) 472 printf("DP training_patter_disable() failed\n"); 473 474 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); 475 if (ret != EXYNOS_DP_SUCCESS) 476 printf("DP set_enhanced_mode() failed\n"); 477 478 priv->lt_info.lt_status = DP_LT_FAIL; 479 } 480 481 return ret; 482 } 483 484 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs, 485 struct exynos_dp_priv *priv) 486 { 487 unsigned int ret = EXYNOS_DP_SUCCESS; 488 unsigned char lane_stat; 489 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; 490 unsigned int i; 491 unsigned char adj_req_sw; 492 unsigned char adj_req_em; 493 unsigned char buf[5]; 494 495 debug("DP: %s was called\n", __func__); 496 mdelay(1); 497 498 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); 499 if (ret != EXYNOS_DP_SUCCESS) { 500 printf("DP read lane status failed\n"); 501 priv->lt_info.lt_status = DP_LT_FAIL; 502 return ret; 503 } 504 505 if (lane_stat & DP_LANE_STAT_CR_DONE) { 506 debug("DP clock Recovery training succeed\n"); 507 exynos_dp_set_training_pattern(regs, TRAINING_PTN2); 508 509 for (i = 0; i < priv->lane_cnt; i++) { 510 ret = exynos_dp_read_dpcd_adj_req(regs, i, 511 &adj_req_sw, &adj_req_em); 512 if (ret != EXYNOS_DP_SUCCESS) { 513 priv->lt_info.lt_status = DP_LT_FAIL; 514 return ret; 515 } 516 517 lt_ctl_val[i] = 0; 518 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 519 520 if ((adj_req_sw == VOLTAGE_LEVEL_3) 521 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 522 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | 523 MAX_PRE_EMPHASIS_REACH_3; 524 } 525 exynos_dp_set_lanex_pre_emphasis(regs, 526 lt_ctl_val[i], i); 527 } 528 529 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; 530 buf[1] = lt_ctl_val[0]; 531 buf[2] = lt_ctl_val[1]; 532 buf[3] = lt_ctl_val[2]; 533 buf[4] = lt_ctl_val[3]; 534 535 ret = exynos_dp_write_bytes_to_dpcd(regs, 536 DPCD_TRAINING_PATTERN_SET, 5, buf); 537 if (ret != EXYNOS_DP_SUCCESS) { 538 printf("DP write training pattern1 failed\n"); 539 priv->lt_info.lt_status = DP_LT_FAIL; 540 return ret; 541 } else 542 priv->lt_info.lt_status = DP_LT_ET; 543 } else { 544 for (i = 0; i < priv->lane_cnt; i++) { 545 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis( 546 regs, i); 547 ret = exynos_dp_read_dpcd_adj_req(regs, i, 548 &adj_req_sw, &adj_req_em); 549 if (ret != EXYNOS_DP_SUCCESS) { 550 printf("DP read adj req failed\n"); 551 priv->lt_info.lt_status = DP_LT_FAIL; 552 return ret; 553 } 554 555 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 556 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) 557 ret = exynos_dp_reduce_link_rate(regs, 558 priv); 559 560 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == 561 adj_req_sw) && 562 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == 563 adj_req_em)) { 564 priv->lt_info.cr_loop[i]++; 565 if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP) 566 ret = exynos_dp_reduce_link_rate( 567 regs, priv); 568 } 569 570 lt_ctl_val[i] = 0; 571 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 572 573 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 574 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 575 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | 576 MAX_PRE_EMPHASIS_REACH_3; 577 } 578 exynos_dp_set_lanex_pre_emphasis(regs, 579 lt_ctl_val[i], i); 580 } 581 582 ret = exynos_dp_write_bytes_to_dpcd(regs, 583 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); 584 if (ret != EXYNOS_DP_SUCCESS) { 585 printf("DP write training pattern2 failed\n"); 586 priv->lt_info.lt_status = DP_LT_FAIL; 587 return ret; 588 } 589 } 590 591 return ret; 592 } 593 594 static unsigned int exynos_dp_process_equalizer_training( 595 struct exynos_dp *regs, struct exynos_dp_priv *priv) 596 { 597 unsigned int ret = EXYNOS_DP_SUCCESS; 598 unsigned char lane_stat, adj_req_sw, adj_req_em, i; 599 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; 600 unsigned char interlane_aligned = 0; 601 unsigned char f_bw; 602 unsigned char f_lane_cnt; 603 unsigned char sink_stat; 604 605 mdelay(1); 606 607 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); 608 if (ret != EXYNOS_DP_SUCCESS) { 609 printf("DP read lane status failed\n"); 610 priv->lt_info.lt_status = DP_LT_FAIL; 611 return ret; 612 } 613 614 debug("DP lane stat : %x\n", lane_stat); 615 616 if (lane_stat & DP_LANE_STAT_CR_DONE) { 617 ret = exynos_dp_read_byte_from_dpcd(regs, 618 DPCD_LN_ALIGN_UPDATED, 619 &sink_stat); 620 if (ret != EXYNOS_DP_SUCCESS) { 621 priv->lt_info.lt_status = DP_LT_FAIL; 622 623 return ret; 624 } 625 626 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); 627 628 for (i = 0; i < priv->lane_cnt; i++) { 629 ret = exynos_dp_read_dpcd_adj_req(regs, i, 630 &adj_req_sw, &adj_req_em); 631 if (ret != EXYNOS_DP_SUCCESS) { 632 printf("DP read adj req 1 failed\n"); 633 priv->lt_info.lt_status = DP_LT_FAIL; 634 635 return ret; 636 } 637 638 lt_ctl_val[i] = 0; 639 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 640 641 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 642 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 643 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; 644 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; 645 } 646 } 647 648 if (((lane_stat&DP_LANE_STAT_CE_DONE) && 649 (lane_stat&DP_LANE_STAT_SYM_LOCK)) 650 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { 651 debug("DP Equalizer training succeed\n"); 652 653 f_bw = exynos_dp_get_link_bandwidth(regs); 654 f_lane_cnt = exynos_dp_get_lane_count(regs); 655 656 debug("DP final BandWidth : %x\n", f_bw); 657 debug("DP final Lane Count : %x\n", f_lane_cnt); 658 659 priv->lt_info.lt_status = DP_LT_FINISHED; 660 661 exynos_dp_equalizer_err_link(regs, priv); 662 663 } else { 664 priv->lt_info.ep_loop++; 665 666 if (priv->lt_info.ep_loop > MAX_EQ_LOOP) { 667 if (priv->lane_bw == DP_LANE_BW_2_70) { 668 ret = exynos_dp_reduce_link_rate( 669 regs, priv); 670 } else { 671 priv->lt_info.lt_status = 672 DP_LT_FAIL; 673 exynos_dp_equalizer_err_link(regs, 674 priv); 675 } 676 } else { 677 for (i = 0; i < priv->lane_cnt; i++) 678 exynos_dp_set_lanex_pre_emphasis( 679 regs, lt_ctl_val[i], i); 680 681 ret = exynos_dp_write_bytes_to_dpcd(regs, 682 DPCD_TRAINING_LANE0_SET, 683 4, lt_ctl_val); 684 if (ret != EXYNOS_DP_SUCCESS) { 685 printf("DP set lt pattern failed\n"); 686 priv->lt_info.lt_status = 687 DP_LT_FAIL; 688 exynos_dp_equalizer_err_link(regs, 689 priv); 690 } 691 } 692 } 693 } else if (priv->lane_bw == DP_LANE_BW_2_70) { 694 ret = exynos_dp_reduce_link_rate(regs, priv); 695 } else { 696 priv->lt_info.lt_status = DP_LT_FAIL; 697 exynos_dp_equalizer_err_link(regs, priv); 698 } 699 700 return ret; 701 } 702 703 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs, 704 struct exynos_dp_priv *priv) 705 { 706 unsigned int ret = 0; 707 int training_finished; 708 709 /* Turn off unnecessary lane */ 710 if (priv->lane_cnt == 1) 711 exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1); 712 713 training_finished = 0; 714 715 priv->lt_info.lt_status = DP_LT_START; 716 717 /* Process here */ 718 while (!training_finished) { 719 switch (priv->lt_info.lt_status) { 720 case DP_LT_START: 721 ret = exynos_dp_link_start(regs, priv); 722 if (ret != EXYNOS_DP_SUCCESS) { 723 printf("DP LT:link start failed\n"); 724 return ret; 725 } 726 break; 727 case DP_LT_CR: 728 ret = exynos_dp_process_clock_recovery(regs, 729 priv); 730 if (ret != EXYNOS_DP_SUCCESS) { 731 printf("DP LT:clock recovery failed\n"); 732 return ret; 733 } 734 break; 735 case DP_LT_ET: 736 ret = exynos_dp_process_equalizer_training(regs, 737 priv); 738 if (ret != EXYNOS_DP_SUCCESS) { 739 printf("DP LT:equalizer training failed\n"); 740 return ret; 741 } 742 break; 743 case DP_LT_FINISHED: 744 training_finished = 1; 745 break; 746 case DP_LT_FAIL: 747 return -1; 748 } 749 } 750 751 return ret; 752 } 753 754 static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs, 755 struct exynos_dp_priv *priv) 756 { 757 unsigned int ret; 758 759 exynos_dp_init_training(regs); 760 761 ret = exynos_dp_sw_link_training(regs, priv); 762 if (ret != EXYNOS_DP_SUCCESS) 763 printf("DP dp_sw_link_training() failed\n"); 764 765 return ret; 766 } 767 768 static void exynos_dp_enable_scramble(struct exynos_dp *regs, 769 unsigned int enable) 770 { 771 unsigned char data; 772 773 if (enable) { 774 exynos_dp_enable_scrambling(regs, DP_ENABLE); 775 776 exynos_dp_read_byte_from_dpcd(regs, 777 DPCD_TRAINING_PATTERN_SET, &data); 778 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 779 (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); 780 } else { 781 exynos_dp_enable_scrambling(regs, DP_DISABLE); 782 exynos_dp_read_byte_from_dpcd(regs, 783 DPCD_TRAINING_PATTERN_SET, &data); 784 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 785 (u8)(data | DPCD_SCRAMBLING_DISABLED)); 786 } 787 } 788 789 static unsigned int exynos_dp_config_video(struct exynos_dp *regs, 790 struct exynos_dp_priv *priv) 791 { 792 unsigned int ret = 0; 793 unsigned int retry_cnt; 794 795 mdelay(1); 796 797 if (priv->video_info.master_mode) { 798 printf("DP does not support master mode\n"); 799 return -ENODEV; 800 } else { 801 /* debug slave */ 802 exynos_dp_config_video_slave_mode(regs, 803 &priv->video_info); 804 } 805 806 exynos_dp_set_video_color_format(regs, &priv->video_info); 807 808 if (priv->video_info.bist_mode) { 809 if (exynos_dp_config_video_bist(regs, priv) != 0) 810 return -1; 811 } 812 813 ret = exynos_dp_get_pll_lock_status(regs); 814 if (ret != PLL_LOCKED) { 815 printf("DP PLL is not locked yet\n"); 816 return -EIO; 817 } 818 819 if (priv->video_info.master_mode == 0) { 820 retry_cnt = 10; 821 while (retry_cnt) { 822 ret = exynos_dp_is_slave_video_stream_clock_on(regs); 823 if (ret != EXYNOS_DP_SUCCESS) { 824 if (retry_cnt == 0) { 825 printf("DP stream_clock_on failed\n"); 826 return ret; 827 } 828 retry_cnt--; 829 mdelay(1); 830 } else 831 break; 832 } 833 } 834 835 /* Set to use the register calculated M/N video */ 836 exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0); 837 838 /* For video bist, Video timing must be generated by register */ 839 exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE); 840 841 /* Enable video bist */ 842 if (priv->video_info.bist_pattern != COLOR_RAMP && 843 priv->video_info.bist_pattern != BALCK_WHITE_V_LINES && 844 priv->video_info.bist_pattern != COLOR_SQUARE) 845 exynos_dp_enable_video_bist(regs, 846 priv->video_info.bist_mode); 847 else 848 exynos_dp_enable_video_bist(regs, DP_DISABLE); 849 850 /* Disable video mute */ 851 exynos_dp_enable_video_mute(regs, DP_DISABLE); 852 853 /* Configure video Master or Slave mode */ 854 exynos_dp_enable_video_master(regs, 855 priv->video_info.master_mode); 856 857 /* Enable video */ 858 exynos_dp_start_video(regs); 859 860 if (priv->video_info.master_mode == 0) { 861 retry_cnt = 100; 862 while (retry_cnt) { 863 ret = exynos_dp_is_video_stream_on(regs); 864 if (ret != EXYNOS_DP_SUCCESS) { 865 if (retry_cnt == 0) { 866 printf("DP Timeout of video stream\n"); 867 return ret; 868 } 869 retry_cnt--; 870 mdelay(5); 871 } else 872 break; 873 } 874 } 875 876 return ret; 877 } 878 879 static int exynos_dp_ofdata_to_platdata(struct udevice *dev) 880 { 881 struct exynos_dp_priv *priv = dev_get_priv(dev); 882 const void *blob = gd->fdt_blob; 883 unsigned int node = dev_of_offset(dev); 884 fdt_addr_t addr; 885 886 addr = devfdt_get_addr(dev); 887 if (addr == FDT_ADDR_T_NONE) { 888 debug("Can't get the DP base address\n"); 889 return -EINVAL; 890 } 891 priv->regs = (struct exynos_dp *)addr; 892 priv->disp_info.h_res = fdtdec_get_int(blob, node, 893 "samsung,h-res", 0); 894 priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, 895 "samsung,h-sync-width", 0); 896 priv->disp_info.h_back_porch = fdtdec_get_int(blob, node, 897 "samsung,h-back-porch", 0); 898 priv->disp_info.h_front_porch = fdtdec_get_int(blob, node, 899 "samsung,h-front-porch", 0); 900 priv->disp_info.v_res = fdtdec_get_int(blob, node, 901 "samsung,v-res", 0); 902 priv->disp_info.v_sync_width = fdtdec_get_int(blob, node, 903 "samsung,v-sync-width", 0); 904 priv->disp_info.v_back_porch = fdtdec_get_int(blob, node, 905 "samsung,v-back-porch", 0); 906 priv->disp_info.v_front_porch = fdtdec_get_int(blob, node, 907 "samsung,v-front-porch", 0); 908 priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node, 909 "samsung,v-sync-rate", 0); 910 911 priv->lt_info.lt_status = fdtdec_get_int(blob, node, 912 "samsung,lt-status", 0); 913 914 priv->video_info.master_mode = fdtdec_get_int(blob, node, 915 "samsung,master-mode", 0); 916 priv->video_info.bist_mode = fdtdec_get_int(blob, node, 917 "samsung,bist-mode", 0); 918 priv->video_info.bist_pattern = fdtdec_get_int(blob, node, 919 "samsung,bist-pattern", 0); 920 priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node, 921 "samsung,h-sync-polarity", 0); 922 priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node, 923 "samsung,v-sync-polarity", 0); 924 priv->video_info.interlaced = fdtdec_get_int(blob, node, 925 "samsung,interlaced", 0); 926 priv->video_info.color_space = fdtdec_get_int(blob, node, 927 "samsung,color-space", 0); 928 priv->video_info.dynamic_range = fdtdec_get_int(blob, node, 929 "samsung,dynamic-range", 0); 930 priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, 931 "samsung,ycbcr-coeff", 0); 932 priv->video_info.color_depth = fdtdec_get_int(blob, node, 933 "samsung,color-depth", 0); 934 return 0; 935 } 936 937 static int exynos_dp_bridge_init(struct udevice *dev) 938 { 939 const int max_tries = 10; 940 int num_tries; 941 int ret; 942 943 debug("%s\n", __func__); 944 ret = video_bridge_attach(dev); 945 if (ret) { 946 debug("video bridge init failed: %d\n", ret); 947 return ret; 948 } 949 950 /* 951 * We need to wait for 90ms after bringing up the bridge since there 952 * is a phantom "high" on the HPD chip during its bootup. The phantom 953 * high comes within 7ms of de-asserting PD and persists for at least 954 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The 955 * phantom high makes it hard for us to know when the NXP chip is up. 956 */ 957 mdelay(90); 958 959 for (num_tries = 0; num_tries < max_tries; num_tries++) { 960 /* Check HPD. If it's high, or we don't have it, all is well */ 961 ret = video_bridge_check_attached(dev); 962 if (!ret || ret == -ENOENT) 963 return 0; 964 965 debug("%s: eDP bridge failed to come up; try %d of %d\n", 966 __func__, num_tries, max_tries); 967 } 968 969 /* Immediately go into bridge reset if the hp line is not high */ 970 return -EIO; 971 } 972 973 static int exynos_dp_bridge_setup(const void *blob) 974 { 975 const int max_tries = 2; 976 int num_tries; 977 struct udevice *dev; 978 int ret; 979 980 /* Configure I2C registers for Parade bridge */ 981 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 982 if (ret) { 983 debug("video bridge init failed: %d\n", ret); 984 return ret; 985 } 986 987 if (strncmp(dev->driver->name, "parade", 6)) { 988 /* Mux HPHPD to the special hotplug detect mode */ 989 exynos_pinmux_config(PERIPH_ID_DPHPD, 0); 990 } 991 992 for (num_tries = 0; num_tries < max_tries; num_tries++) { 993 ret = exynos_dp_bridge_init(dev); 994 if (!ret) 995 return 0; 996 if (num_tries == max_tries - 1) 997 break; 998 999 /* 1000 * If we're here, the bridge chip failed to initialise. 1001 * Power down the bridge in an attempt to reset. 1002 */ 1003 video_bridge_set_active(dev, false); 1004 1005 /* 1006 * Arbitrarily wait 300ms here with DP_N low. Don't know for 1007 * sure how long we should wait, but we're being paranoid. 1008 */ 1009 mdelay(300); 1010 } 1011 1012 return ret; 1013 } 1014 int exynos_dp_enable(struct udevice *dev, int panel_bpp, 1015 const struct display_timing *timing) 1016 { 1017 struct exynos_dp_priv *priv = dev_get_priv(dev); 1018 struct exynos_dp *regs = priv->regs; 1019 unsigned int ret; 1020 1021 debug("%s: start\n", __func__); 1022 exynos_dp_disp_info(&priv->disp_info); 1023 1024 ret = exynos_dp_bridge_setup(gd->fdt_blob); 1025 if (ret && ret != -ENODEV) 1026 printf("LCD bridge failed to enable: %d\n", ret); 1027 1028 exynos_dp_phy_ctrl(1); 1029 1030 ret = exynos_dp_init_dp(regs); 1031 if (ret != EXYNOS_DP_SUCCESS) { 1032 printf("DP exynos_dp_init_dp() failed\n"); 1033 return ret; 1034 } 1035 1036 ret = exynos_dp_handle_edid(regs, priv); 1037 if (ret != EXYNOS_DP_SUCCESS) { 1038 printf("EDP handle_edid fail\n"); 1039 return ret; 1040 } 1041 1042 ret = exynos_dp_set_link_train(regs, priv); 1043 if (ret != EXYNOS_DP_SUCCESS) { 1044 printf("DP link training fail\n"); 1045 return ret; 1046 } 1047 1048 exynos_dp_enable_scramble(regs, DP_ENABLE); 1049 exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE); 1050 exynos_dp_enable_enhanced_mode(regs, DP_ENABLE); 1051 1052 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); 1053 exynos_dp_set_lane_count(regs, priv->lane_cnt); 1054 1055 exynos_dp_init_video(regs); 1056 ret = exynos_dp_config_video(regs, priv); 1057 if (ret != EXYNOS_DP_SUCCESS) { 1058 printf("Exynos DP init failed\n"); 1059 return ret; 1060 } 1061 1062 debug("Exynos DP init done\n"); 1063 1064 return ret; 1065 } 1066 1067 1068 static const struct dm_display_ops exynos_dp_ops = { 1069 .enable = exynos_dp_enable, 1070 }; 1071 1072 static const struct udevice_id exynos_dp_ids[] = { 1073 { .compatible = "samsung,exynos5-dp" }, 1074 { } 1075 }; 1076 1077 U_BOOT_DRIVER(exynos_dp) = { 1078 .name = "exynos_dp", 1079 .id = UCLASS_DISPLAY, 1080 .of_match = exynos_dp_ids, 1081 .ops = &exynos_dp_ops, 1082 .ofdata_to_platdata = exynos_dp_ofdata_to_platdata, 1083 .priv_auto_alloc_size = sizeof(struct exynos_dp_priv), 1084 }; 1085