1 /* 2 * Porting to u-boot: 3 * 4 * (C) Copyright 2011 5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 6 * 7 * Copyright (C) 2008-2009 MontaVista Software Inc. 8 * Copyright (C) 2008-2009 Texas Instruments Inc 9 * 10 * Based on the LCD driver for TI Avalanche processors written by 11 * Ajay Singh and Shalom Hai. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option)any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <malloc.h> 30 #include <video_fb.h> 31 #include <linux/list.h> 32 #include <linux/fb.h> 33 34 #include <asm/errno.h> 35 #include <asm/io.h> 36 #include <asm/arch/hardware.h> 37 38 #include "videomodes.h" 39 #include <asm/arch/da8xx-fb.h> 40 41 #define DRIVER_NAME "da8xx_lcdc" 42 43 /* LCD Status Register */ 44 #define LCD_END_OF_FRAME1 (1 << 9) 45 #define LCD_END_OF_FRAME0 (1 << 8) 46 #define LCD_PL_LOAD_DONE (1 << 6) 47 #define LCD_FIFO_UNDERFLOW (1 << 5) 48 #define LCD_SYNC_LOST (1 << 2) 49 50 /* LCD DMA Control Register */ 51 #define LCD_DMA_BURST_SIZE(x) ((x) << 4) 52 #define LCD_DMA_BURST_1 0x0 53 #define LCD_DMA_BURST_2 0x1 54 #define LCD_DMA_BURST_4 0x2 55 #define LCD_DMA_BURST_8 0x3 56 #define LCD_DMA_BURST_16 0x4 57 #define LCD_END_OF_FRAME_INT_ENA (1 << 2) 58 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) 59 60 /* LCD Control Register */ 61 #define LCD_CLK_DIVISOR(x) ((x) << 8) 62 #define LCD_RASTER_MODE 0x01 63 64 /* LCD Raster Control Register */ 65 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) 66 #define PALETTE_AND_DATA 0x00 67 #define PALETTE_ONLY 0x01 68 #define DATA_ONLY 0x02 69 70 #define LCD_MONO_8BIT_MODE (1 << 9) 71 #define LCD_RASTER_ORDER (1 << 8) 72 #define LCD_TFT_MODE (1 << 7) 73 #define LCD_UNDERFLOW_INT_ENA (1 << 6) 74 #define LCD_PL_ENABLE (1 << 4) 75 #define LCD_MONOCHROME_MODE (1 << 1) 76 #define LCD_RASTER_ENABLE (1 << 0) 77 #define LCD_TFT_ALT_ENABLE (1 << 23) 78 #define LCD_STN_565_ENABLE (1 << 24) 79 80 /* LCD Raster Timing 2 Register */ 81 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) 82 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) 83 #define LCD_SYNC_CTRL (1 << 25) 84 #define LCD_SYNC_EDGE (1 << 24) 85 #define LCD_INVERT_PIXEL_CLOCK (1 << 22) 86 #define LCD_INVERT_LINE_CLOCK (1 << 21) 87 #define LCD_INVERT_FRAME_CLOCK (1 << 20) 88 89 /* LCD Block */ 90 struct da8xx_lcd_regs { 91 u32 revid; 92 u32 ctrl; 93 u32 stat; 94 u32 lidd_ctrl; 95 u32 lidd_cs0_conf; 96 u32 lidd_cs0_addr; 97 u32 lidd_cs0_data; 98 u32 lidd_cs1_conf; 99 u32 lidd_cs1_addr; 100 u32 lidd_cs1_data; 101 u32 raster_ctrl; 102 u32 raster_timing_0; 103 u32 raster_timing_1; 104 u32 raster_timing_2; 105 u32 raster_subpanel; 106 u32 reserved; 107 u32 dma_ctrl; 108 u32 dma_frm_buf_base_addr_0; 109 u32 dma_frm_buf_ceiling_addr_0; 110 u32 dma_frm_buf_base_addr_1; 111 u32 dma_frm_buf_ceiling_addr_1; 112 }; 113 114 #define LCD_NUM_BUFFERS 1 115 116 #define WSI_TIMEOUT 50 117 #define PALETTE_SIZE 256 118 #define LEFT_MARGIN 64 119 #define RIGHT_MARGIN 64 120 #define UPPER_MARGIN 32 121 #define LOWER_MARGIN 32 122 123 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) 124 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) 125 126 static struct da8xx_lcd_regs *da8xx_fb_reg_base; 127 128 DECLARE_GLOBAL_DATA_PTR; 129 130 /* graphics setup */ 131 static GraphicDevice gpanel; 132 static const struct da8xx_panel *lcd_panel; 133 static struct fb_info *da8xx_fb_info; 134 static int bits_x_pixel; 135 136 static inline unsigned int lcdc_read(u32 *addr) 137 { 138 return (unsigned int)readl(addr); 139 } 140 141 static inline void lcdc_write(unsigned int val, u32 *addr) 142 { 143 writel(val, addr); 144 } 145 146 struct da8xx_fb_par { 147 u32 p_palette_base; 148 unsigned char *v_palette_base; 149 dma_addr_t vram_phys; 150 unsigned long vram_size; 151 void *vram_virt; 152 unsigned int dma_start; 153 unsigned int dma_end; 154 struct clk *lcdc_clk; 155 int irq; 156 unsigned short pseudo_palette[16]; 157 unsigned int palette_sz; 158 unsigned int pxl_clk; 159 int blank; 160 int vsync_flag; 161 int vsync_timeout; 162 }; 163 164 165 /* Variable Screen Information */ 166 static struct fb_var_screeninfo da8xx_fb_var = { 167 .xoffset = 0, 168 .yoffset = 0, 169 .transp = {0, 0, 0}, 170 .nonstd = 0, 171 .activate = 0, 172 .height = -1, 173 .width = -1, 174 .pixclock = 46666, /* 46us - AUO display */ 175 .accel_flags = 0, 176 .left_margin = LEFT_MARGIN, 177 .right_margin = RIGHT_MARGIN, 178 .upper_margin = UPPER_MARGIN, 179 .lower_margin = LOWER_MARGIN, 180 .sync = 0, 181 .vmode = FB_VMODE_NONINTERLACED 182 }; 183 184 static struct fb_fix_screeninfo da8xx_fb_fix = { 185 .id = "DA8xx FB Drv", 186 .type = FB_TYPE_PACKED_PIXELS, 187 .type_aux = 0, 188 .visual = FB_VISUAL_PSEUDOCOLOR, 189 .xpanstep = 0, 190 .ypanstep = 1, 191 .ywrapstep = 0, 192 .accel = FB_ACCEL_NONE 193 }; 194 195 static const struct display_panel disp_panel = { 196 QVGA, 197 16, 198 16, 199 COLOR_ACTIVE, 200 }; 201 202 static const struct lcd_ctrl_config lcd_cfg = { 203 &disp_panel, 204 .ac_bias = 255, 205 .ac_bias_intrpt = 0, 206 .dma_burst_sz = 16, 207 .bpp = 16, 208 .fdd = 255, 209 .tft_alt_mode = 0, 210 .stn_565_mode = 0, 211 .mono_8bit_mode = 0, 212 .invert_line_clock = 1, 213 .invert_frm_clock = 1, 214 .sync_edge = 0, 215 .sync_ctrl = 1, 216 .raster_order = 0, 217 }; 218 219 /* Enable the Raster Engine of the LCD Controller */ 220 static inline void lcd_enable_raster(void) 221 { 222 u32 reg; 223 224 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); 225 if (!(reg & LCD_RASTER_ENABLE)) 226 lcdc_write(reg | LCD_RASTER_ENABLE, 227 &da8xx_fb_reg_base->raster_ctrl); 228 } 229 230 /* Disable the Raster Engine of the LCD Controller */ 231 static inline void lcd_disable_raster(void) 232 { 233 u32 reg; 234 235 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); 236 if (reg & LCD_RASTER_ENABLE) 237 lcdc_write(reg & ~LCD_RASTER_ENABLE, 238 &da8xx_fb_reg_base->raster_ctrl); 239 } 240 241 static void lcd_blit(int load_mode, struct da8xx_fb_par *par) 242 { 243 u32 start; 244 u32 end; 245 u32 reg_ras; 246 u32 reg_dma; 247 248 /* init reg to clear PLM (loading mode) fields */ 249 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); 250 reg_ras &= ~(3 << 20); 251 252 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); 253 254 if (load_mode == LOAD_DATA) { 255 start = par->dma_start; 256 end = par->dma_end; 257 258 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); 259 reg_dma |= LCD_END_OF_FRAME_INT_ENA; 260 261 #if (LCD_NUM_BUFFERS == 2) 262 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; 263 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); 264 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); 265 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); 266 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); 267 #else 268 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE; 269 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); 270 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); 271 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); 272 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); 273 #endif 274 275 } else if (load_mode == LOAD_PALETTE) { 276 start = par->p_palette_base; 277 end = start + par->palette_sz - 1; 278 279 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); 280 reg_ras |= LCD_PL_ENABLE; 281 282 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); 283 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); 284 } 285 286 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); 287 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); 288 289 /* 290 * The Raster enable bit must be set after all other control fields are 291 * set. 292 */ 293 lcd_enable_raster(); 294 } 295 296 /* Configure the Burst Size of DMA */ 297 static int lcd_cfg_dma(int burst_size) 298 { 299 u32 reg; 300 301 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; 302 switch (burst_size) { 303 case 1: 304 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); 305 break; 306 case 2: 307 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); 308 break; 309 case 4: 310 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); 311 break; 312 case 8: 313 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); 314 break; 315 case 16: 316 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); 317 break; 318 default: 319 return -EINVAL; 320 } 321 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); 322 323 return 0; 324 } 325 326 static void lcd_cfg_ac_bias(int period, int transitions_per_int) 327 { 328 u32 reg; 329 330 /* Set the AC Bias Period and Number of Transisitons per Interrupt */ 331 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; 332 reg |= LCD_AC_BIAS_FREQUENCY(period) | 333 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); 334 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); 335 } 336 337 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, 338 int front_porch) 339 { 340 u32 reg; 341 342 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; 343 reg |= ((back_porch & 0xff) << 24) 344 | ((front_porch & 0xff) << 16) 345 | ((pulse_width & 0x3f) << 10); 346 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); 347 } 348 349 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, 350 int front_porch) 351 { 352 u32 reg; 353 354 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; 355 reg |= ((back_porch & 0xff) << 24) 356 | ((front_porch & 0xff) << 16) 357 | ((pulse_width & 0x3f) << 10); 358 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); 359 } 360 361 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) 362 { 363 u32 reg; 364 365 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | 366 LCD_MONO_8BIT_MODE | 367 LCD_MONOCHROME_MODE); 368 369 switch (cfg->p_disp_panel->panel_shade) { 370 case MONOCHROME: 371 reg |= LCD_MONOCHROME_MODE; 372 if (cfg->mono_8bit_mode) 373 reg |= LCD_MONO_8BIT_MODE; 374 break; 375 case COLOR_ACTIVE: 376 reg |= LCD_TFT_MODE; 377 if (cfg->tft_alt_mode) 378 reg |= LCD_TFT_ALT_ENABLE; 379 break; 380 381 case COLOR_PASSIVE: 382 if (cfg->stn_565_mode) 383 reg |= LCD_STN_565_ENABLE; 384 break; 385 386 default: 387 return -EINVAL; 388 } 389 390 /* enable additional interrupts here */ 391 reg |= LCD_UNDERFLOW_INT_ENA; 392 393 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); 394 395 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); 396 397 if (cfg->sync_ctrl) 398 reg |= LCD_SYNC_CTRL; 399 else 400 reg &= ~LCD_SYNC_CTRL; 401 402 if (cfg->sync_edge) 403 reg |= LCD_SYNC_EDGE; 404 else 405 reg &= ~LCD_SYNC_EDGE; 406 407 if (cfg->invert_line_clock) 408 reg |= LCD_INVERT_LINE_CLOCK; 409 else 410 reg &= ~LCD_INVERT_LINE_CLOCK; 411 412 if (cfg->invert_frm_clock) 413 reg |= LCD_INVERT_FRAME_CLOCK; 414 else 415 reg &= ~LCD_INVERT_FRAME_CLOCK; 416 417 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); 418 419 return 0; 420 } 421 422 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, 423 u32 bpp, u32 raster_order) 424 { 425 u32 reg; 426 427 /* Set the Panel Width */ 428 /* Pixels per line = (PPL + 1)*16 */ 429 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ 430 width &= 0x3f0; 431 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); 432 reg &= 0xfffffc00; 433 reg |= ((width >> 4) - 1) << 4; 434 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); 435 436 /* Set the Panel Height */ 437 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); 438 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); 439 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); 440 441 /* Set the Raster Order of the Frame Buffer */ 442 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); 443 if (raster_order) 444 reg |= LCD_RASTER_ORDER; 445 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); 446 447 switch (bpp) { 448 case 1: 449 case 2: 450 case 4: 451 case 16: 452 par->palette_sz = 16 * 2; 453 break; 454 455 case 8: 456 par->palette_sz = 256 * 2; 457 break; 458 459 default: 460 return -EINVAL; 461 } 462 463 return 0; 464 } 465 466 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, 467 unsigned blue, unsigned transp, 468 struct fb_info *info) 469 { 470 struct da8xx_fb_par *par = info->par; 471 unsigned short *palette = (unsigned short *) par->v_palette_base; 472 u_short pal; 473 int update_hw = 0; 474 475 if (regno > 255) 476 return 1; 477 478 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) 479 return 1; 480 481 if (info->var.bits_per_pixel == 8) { 482 red >>= 4; 483 green >>= 8; 484 blue >>= 12; 485 486 pal = (red & 0x0f00); 487 pal |= (green & 0x00f0); 488 pal |= (blue & 0x000f); 489 490 if (palette[regno] != pal) { 491 update_hw = 1; 492 palette[regno] = pal; 493 } 494 } else if ((info->var.bits_per_pixel == 16) && regno < 16) { 495 red >>= (16 - info->var.red.length); 496 red <<= info->var.red.offset; 497 498 green >>= (16 - info->var.green.length); 499 green <<= info->var.green.offset; 500 501 blue >>= (16 - info->var.blue.length); 502 blue <<= info->var.blue.offset; 503 504 par->pseudo_palette[regno] = red | green | blue; 505 506 if (palette[0] != 0x4000) { 507 update_hw = 1; 508 palette[0] = 0x4000; 509 } 510 } 511 512 /* Update the palette in the h/w as needed. */ 513 if (update_hw) 514 lcd_blit(LOAD_PALETTE, par); 515 516 return 0; 517 } 518 519 static void lcd_reset(struct da8xx_fb_par *par) 520 { 521 /* Disable the Raster if previously Enabled */ 522 lcd_disable_raster(); 523 524 /* DMA has to be disabled */ 525 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); 526 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); 527 } 528 529 static void lcd_calc_clk_divider(struct da8xx_fb_par *par) 530 { 531 unsigned int lcd_clk, div; 532 533 /* Get clock from sysclk2 */ 534 lcd_clk = clk_get(2); 535 536 div = lcd_clk / par->pxl_clk; 537 debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n", 538 lcd_clk, div, par->pxl_clk); 539 540 /* Configure the LCD clock divisor. */ 541 lcdc_write(LCD_CLK_DIVISOR(div) | 542 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); 543 } 544 545 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, 546 const struct da8xx_panel *panel) 547 { 548 u32 bpp; 549 int ret = 0; 550 551 lcd_reset(par); 552 553 /* Calculate the divider */ 554 lcd_calc_clk_divider(par); 555 556 if (panel->invert_pxl_clk) 557 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | 558 LCD_INVERT_PIXEL_CLOCK), 559 &da8xx_fb_reg_base->raster_timing_2); 560 else 561 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 562 ~LCD_INVERT_PIXEL_CLOCK), 563 &da8xx_fb_reg_base->raster_timing_2); 564 565 /* Configure the DMA burst size. */ 566 ret = lcd_cfg_dma(cfg->dma_burst_sz); 567 if (ret < 0) 568 return ret; 569 570 /* Configure the AC bias properties. */ 571 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); 572 573 /* Configure the vertical and horizontal sync properties. */ 574 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); 575 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); 576 577 /* Configure for disply */ 578 ret = lcd_cfg_display(cfg); 579 if (ret < 0) 580 return ret; 581 582 if (QVGA != cfg->p_disp_panel->panel_type) 583 return -EINVAL; 584 585 if (cfg->bpp <= cfg->p_disp_panel->max_bpp && 586 cfg->bpp >= cfg->p_disp_panel->min_bpp) 587 bpp = cfg->bpp; 588 else 589 bpp = cfg->p_disp_panel->max_bpp; 590 if (bpp == 12) 591 bpp = 16; 592 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, 593 (unsigned int)panel->height, bpp, 594 cfg->raster_order); 595 if (ret < 0) 596 return ret; 597 598 /* Configure FDD */ 599 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | 600 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); 601 602 return 0; 603 } 604 605 static void lcdc_dma_start(void) 606 { 607 struct da8xx_fb_par *par = da8xx_fb_info->par; 608 lcdc_write(par->dma_start, 609 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); 610 lcdc_write(par->dma_end, 611 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); 612 lcdc_write(0, 613 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); 614 lcdc_write(0, 615 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); 616 } 617 618 static u32 lcdc_irq_handler(void) 619 { 620 struct da8xx_fb_par *par = da8xx_fb_info->par; 621 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); 622 u32 reg_ras; 623 624 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { 625 debug("LCD_SYNC_LOST\n"); 626 lcd_disable_raster(); 627 lcdc_write(stat, &da8xx_fb_reg_base->stat); 628 lcd_enable_raster(); 629 return LCD_SYNC_LOST; 630 } else if (stat & LCD_PL_LOAD_DONE) { 631 debug("LCD_PL_LOAD_DONE\n"); 632 /* 633 * Must disable raster before changing state of any control bit. 634 * And also must be disabled before clearing the PL loading 635 * interrupt via the following write to the status register. If 636 * this is done after then one gets multiple PL done interrupts. 637 */ 638 lcd_disable_raster(); 639 640 lcdc_write(stat, &da8xx_fb_reg_base->stat); 641 642 /* Disable PL completion inerrupt */ 643 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); 644 reg_ras &= ~LCD_PL_ENABLE; 645 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); 646 647 /* Setup and start data loading mode */ 648 lcd_blit(LOAD_DATA, par); 649 return LCD_PL_LOAD_DONE; 650 } else { 651 lcdc_write(stat, &da8xx_fb_reg_base->stat); 652 653 if (stat & LCD_END_OF_FRAME0) 654 debug("LCD_END_OF_FRAME0\n"); 655 656 lcdc_write(par->dma_start, 657 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); 658 lcdc_write(par->dma_end, 659 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); 660 par->vsync_flag = 1; 661 return LCD_END_OF_FRAME0; 662 } 663 return stat; 664 } 665 666 static u32 wait_for_event(u32 event) 667 { 668 u32 timeout = 50000; 669 u32 ret; 670 671 do { 672 ret = lcdc_irq_handler(); 673 udelay(1000); 674 } while (!(ret & event)); 675 676 if (timeout <= 0) { 677 printf("%s: event %d not hit\n", __func__, event); 678 return -1; 679 } 680 681 return 0; 682 683 } 684 685 void *video_hw_init(void) 686 { 687 struct da8xx_fb_par *par; 688 u32 size; 689 char *p; 690 691 if (!lcd_panel) { 692 printf("Display not initialized\n"); 693 return NULL; 694 } 695 gpanel.winSizeX = lcd_panel->width; 696 gpanel.winSizeY = lcd_panel->height; 697 gpanel.plnSizeX = lcd_panel->width; 698 gpanel.plnSizeY = lcd_panel->height; 699 700 switch (bits_x_pixel) { 701 case 24: 702 gpanel.gdfBytesPP = 4; 703 gpanel.gdfIndex = GDF_32BIT_X888RGB; 704 break; 705 case 16: 706 gpanel.gdfBytesPP = 2; 707 gpanel.gdfIndex = GDF_16BIT_565RGB; 708 break; 709 default: 710 gpanel.gdfBytesPP = 1; 711 gpanel.gdfIndex = GDF__8BIT_INDEX; 712 break; 713 } 714 715 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE; 716 717 debug("Resolution: %dx%d %x\n", 718 gpanel.winSizeX, 719 gpanel.winSizeY, 720 lcd_cfg.bpp); 721 722 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); 723 da8xx_fb_info = malloc(size); 724 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info); 725 726 if (!da8xx_fb_info) { 727 printf("Memory allocation failed for fb_info\n"); 728 return NULL; 729 } 730 memset(da8xx_fb_info, 0, size); 731 p = (char *)da8xx_fb_info; 732 da8xx_fb_info->par = p + sizeof(struct fb_info); 733 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par); 734 735 par = da8xx_fb_info->par; 736 par->pxl_clk = lcd_panel->pxl_clk; 737 738 if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) { 739 printf("lcd_init failed\n"); 740 goto err_release_fb; 741 } 742 743 /* allocate frame buffer */ 744 par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp; 745 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; 746 747 par->vram_virt = malloc(par->vram_size); 748 749 par->vram_phys = (dma_addr_t) par->vram_virt; 750 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n", 751 (unsigned int)par->vram_size, 752 (unsigned int)par->vram_virt); 753 if (!par->vram_virt) { 754 printf("GLCD: malloc for frame buffer failed\n"); 755 goto err_release_fb; 756 } 757 758 gpanel.frameAdrs = (unsigned int)par->vram_virt; 759 da8xx_fb_info->screen_base = (char *) par->vram_virt; 760 da8xx_fb_fix.smem_start = gpanel.frameAdrs; 761 da8xx_fb_fix.smem_len = par->vram_size; 762 da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8; 763 764 par->dma_start = par->vram_phys; 765 par->dma_end = par->dma_start + lcd_panel->height * 766 da8xx_fb_fix.line_length - 1; 767 768 /* allocate palette buffer */ 769 par->v_palette_base = malloc(PALETTE_SIZE); 770 if (!par->v_palette_base) { 771 printf("GLCD: malloc for palette buffer failed\n"); 772 goto err_release_fb_mem; 773 } 774 memset(par->v_palette_base, 0, PALETTE_SIZE); 775 par->p_palette_base = (unsigned int)par->v_palette_base; 776 777 /* Initialize par */ 778 da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp; 779 780 da8xx_fb_var.xres = lcd_panel->width; 781 da8xx_fb_var.xres_virtual = lcd_panel->width; 782 783 da8xx_fb_var.yres = lcd_panel->height; 784 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; 785 786 da8xx_fb_var.grayscale = 787 lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; 788 da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp; 789 790 da8xx_fb_var.hsync_len = lcd_panel->hsw; 791 da8xx_fb_var.vsync_len = lcd_panel->vsw; 792 793 /* Initialize fbinfo */ 794 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; 795 da8xx_fb_info->fix = da8xx_fb_fix; 796 da8xx_fb_info->var = da8xx_fb_var; 797 da8xx_fb_info->pseudo_palette = par->pseudo_palette; 798 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? 799 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 800 801 /* Clear interrupt */ 802 memset((void *)par->vram_virt, 0, par->vram_size); 803 lcd_disable_raster(); 804 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); 805 debug("Palette at 0x%x size %d\n", par->p_palette_base, 806 par->palette_sz); 807 lcdc_dma_start(); 808 809 /* Load a default palette */ 810 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info); 811 812 /* Check that the palette is loaded */ 813 wait_for_event(LCD_PL_LOAD_DONE); 814 815 /* Wait until DMA is working */ 816 wait_for_event(LCD_END_OF_FRAME0); 817 818 return (void *)&gpanel; 819 820 err_release_fb_mem: 821 free(par->vram_virt); 822 823 err_release_fb: 824 free(da8xx_fb_info); 825 826 return NULL; 827 } 828 829 void video_set_lut(unsigned int index, /* color number */ 830 unsigned char r, /* red */ 831 unsigned char g, /* green */ 832 unsigned char b /* blue */ 833 ) 834 { 835 836 return; 837 } 838 839 void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel) 840 { 841 lcd_panel = panel; 842 bits_x_pixel = bits_pixel; 843 } 844