1 /* 2 * Driver for AT91/AT32 LCD Controller 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <atmel_lcd.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <video.h> 14 #include <asm/io.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <bmp_layout.h> 19 #include <atmel_lcdc.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #ifdef CONFIG_DM_VIDEO 24 enum { 25 /* Maximum LCD size we support */ 26 LCD_MAX_WIDTH = 1366, 27 LCD_MAX_HEIGHT = 768, 28 LCD_MAX_LOG2_BPP = VIDEO_BPP16, 29 }; 30 #endif 31 32 struct atmel_fb_priv { 33 struct display_timing timing; 34 }; 35 36 /* configurable parameters */ 37 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 38 #define ATMEL_LCDC_DMA_BURST_LEN 8 39 #ifndef ATMEL_LCDC_GUARD_TIME 40 #define ATMEL_LCDC_GUARD_TIME 1 41 #endif 42 43 #if defined(CONFIG_AT91SAM9263) 44 #define ATMEL_LCDC_FIFO_SIZE 2048 45 #else 46 #define ATMEL_LCDC_FIFO_SIZE 512 47 #endif 48 49 #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) 50 #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) 51 52 #ifndef CONFIG_DM_VIDEO 53 ushort *configuration_get_cmap(void) 54 { 55 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0)); 56 } 57 58 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555) 59 void fb_put_word(uchar **fb, uchar **from) 60 { 61 *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03); 62 *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2); 63 *from += 2; 64 } 65 #endif 66 67 #ifdef CONFIG_LCD_LOGO 68 #include <bmp_logo.h> 69 void lcd_logo_set_cmap(void) 70 { 71 int i; 72 uint lut_entry; 73 ushort colreg; 74 uint *cmap = (uint *)configuration_get_cmap(); 75 76 for (i = 0; i < BMP_LOGO_COLORS; ++i) { 77 colreg = bmp_logo_palette[i]; 78 #ifdef CONFIG_ATMEL_LCD_BGR555 79 lut_entry = ((colreg & 0x000F) << 11) | 80 ((colreg & 0x00F0) << 2) | 81 ((colreg & 0x0F00) >> 7); 82 #else 83 lut_entry = ((colreg & 0x000F) << 1) | 84 ((colreg & 0x00F0) << 3) | 85 ((colreg & 0x0F00) << 4); 86 #endif 87 *(cmap + BMP_LOGO_OFFSET) = lut_entry; 88 cmap++; 89 } 90 } 91 #endif 92 93 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 94 { 95 #if defined(CONFIG_ATMEL_LCD_BGR555) 96 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), 97 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7)); 98 #else 99 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), 100 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8)); 101 #endif 102 } 103 104 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors) 105 { 106 int i; 107 108 for (i = 0; i < colors; ++i) { 109 struct bmp_color_table_entry cte = bmp->color_table[i]; 110 lcd_setcolreg(i, cte.red, cte.green, cte.blue); 111 } 112 } 113 #endif 114 115 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, 116 bool tft, bool cont_pol_low, ulong lcdbase) 117 { 118 unsigned long value; 119 void *reg = (void *)addr; 120 121 /* Turn off the LCD controller and the DMA controller */ 122 lcdc_writel(reg, ATMEL_LCDC_PWRCON, 123 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET); 124 125 /* Wait for the LCDC core to become idle */ 126 while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) 127 udelay(10); 128 129 lcdc_writel(reg, ATMEL_LCDC_DMACON, 0); 130 131 /* Reset LCDC DMA */ 132 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); 133 134 /* ...set frame size and burst length = 8 words (?) */ 135 value = (timing->hactive.typ * timing->vactive.typ * 136 (1 << bpix)) / 32; 137 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); 138 lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value); 139 140 /* Set pixel clock */ 141 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; 142 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) 143 value++; 144 value = (value / 2) - 1; 145 146 if (!value) { 147 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); 148 } else 149 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, 150 value << ATMEL_LCDC_CLKVAL_OFFSET); 151 152 /* Initialize control register 2 */ 153 #ifdef CONFIG_AVR32 154 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; 155 #else 156 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; 157 #endif 158 if (tft) 159 value |= ATMEL_LCDC_DISTYPE_TFT; 160 161 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) 162 value |= ATMEL_LCDC_INVLINE_INVERTED; 163 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) 164 value |= ATMEL_LCDC_INVFRAME_INVERTED; 165 value |= bpix << 5; 166 lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value); 167 168 /* Vertical timing */ 169 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; 170 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; 171 value |= timing->vfront_porch.typ; 172 /* Magic! (Datasheet says "Bit 31 must be written to 1") */ 173 value |= 1U << 31; 174 lcdc_writel(reg, ATMEL_LCDC_TIM1, value); 175 176 /* Horizontal timing */ 177 value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET; 178 value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET; 179 value |= (timing->hback_porch.typ - 1); 180 lcdc_writel(reg, ATMEL_LCDC_TIM2, value); 181 182 /* Display size */ 183 value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET; 184 value |= timing->vactive.typ - 1; 185 lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value); 186 187 /* FIFO Threshold: Use formula from data sheet */ 188 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); 189 lcdc_writel(reg, ATMEL_LCDC_FIFO, value); 190 191 /* Toggle LCD_MODE every frame */ 192 lcdc_writel(reg, ATMEL_LCDC_MVAL, 0); 193 194 /* Disable all interrupts */ 195 lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL); 196 197 /* Set contrast */ 198 value = ATMEL_LCDC_PS_DIV8 | 199 ATMEL_LCDC_ENA_PWMENABLE; 200 if (!cont_pol_low) 201 value |= ATMEL_LCDC_POL_POSITIVE; 202 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value); 203 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); 204 205 /* Set framebuffer DMA base address and pixel offset */ 206 lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase); 207 208 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); 209 lcdc_writel(reg, ATMEL_LCDC_PWRCON, 210 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); 211 } 212 213 #ifndef CONFIG_DM_VIDEO 214 void lcd_ctrl_init(void *lcdbase) 215 { 216 struct display_timing timing; 217 218 timing.flags = 0; 219 if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED)) 220 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 221 if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED)) 222 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW; 223 timing.pixelclock.typ = panel_info.vl_clk; 224 225 timing.hactive.typ = panel_info.vl_col; 226 timing.hfront_porch.typ = panel_info.vl_right_margin; 227 timing.hback_porch.typ = panel_info.vl_left_margin; 228 timing.hsync_len.typ = panel_info.vl_hsync_len; 229 230 timing.vactive.typ = panel_info.vl_row; 231 timing.vfront_porch.typ = panel_info.vl_clk; 232 timing.vback_porch.typ = panel_info.vl_clk; 233 timing.vsync_len.typ = panel_info.vl_clk; 234 235 atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix, 236 panel_info.vl_tft, panel_info.vl_cont_pol_low, 237 (ulong)lcdbase); 238 } 239 240 ulong calc_fbsize(void) 241 { 242 return ((panel_info.vl_col * panel_info.vl_row * 243 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; 244 } 245 #endif 246 247 #ifdef CONFIG_DM_VIDEO 248 static int atmel_fb_lcd_probe(struct udevice *dev) 249 { 250 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 251 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 252 struct atmel_fb_priv *priv = dev_get_priv(dev); 253 struct display_timing *timing = &priv->timing; 254 255 /* 256 * For now some values are hard-coded. We could use the device tree 257 * bindings in simple-framebuffer.txt to specify the format/bpp and 258 * some Atmel-specific binding for tft and cont_pol_low. 259 */ 260 atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false, 261 uc_plat->base); 262 uc_priv->xsize = timing->hactive.typ; 263 uc_priv->ysize = timing->vactive.typ; 264 uc_priv->bpix = VIDEO_BPP16; 265 video_set_flush_dcache(dev, true); 266 debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base, 267 uc_plat->size, uc_priv->xsize, uc_priv->ysize); 268 269 return 0; 270 } 271 272 static int atmel_fb_ofdata_to_platdata(struct udevice *dev) 273 { 274 struct atmel_lcd_platdata *plat = dev_get_platdata(dev); 275 struct atmel_fb_priv *priv = dev_get_priv(dev); 276 struct display_timing *timing = &priv->timing; 277 const void *blob = gd->fdt_blob; 278 279 if (fdtdec_decode_display_timing(blob, dev->of_offset, 280 plat->timing_index, timing)) { 281 debug("%s: Failed to decode display timing\n", __func__); 282 return -EINVAL; 283 } 284 285 return 0; 286 } 287 288 static int atmel_fb_lcd_bind(struct udevice *dev) 289 { 290 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); 291 292 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * 293 (1 << VIDEO_BPP16) / 8; 294 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); 295 296 return 0; 297 } 298 299 static const struct udevice_id atmel_fb_lcd_ids[] = { 300 { .compatible = "atmel,at91sam9g45-lcdc" }, 301 { } 302 }; 303 304 U_BOOT_DRIVER(atmel_fb) = { 305 .name = "atmel_fb", 306 .id = UCLASS_VIDEO, 307 .of_match = atmel_fb_lcd_ids, 308 .bind = atmel_fb_lcd_bind, 309 .ofdata_to_platdata = atmel_fb_ofdata_to_platdata, 310 .probe = atmel_fb_lcd_probe, 311 .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata), 312 .priv_auto_alloc_size = sizeof(struct atmel_fb_priv), 313 }; 314 #endif 315