1 /* 2 * Driver for AT91/AT32 MULTI LAYER LCD Controller 3 * 4 * Copyright (C) 2012 Atmel Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/clk.h> 29 #include <lcd.h> 30 #include <atmel_hlcdc.h> 31 32 /* configurable parameters */ 33 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 34 #define ATMEL_LCDC_DMA_BURST_LEN 8 35 #ifndef ATMEL_LCDC_GUARD_TIME 36 #define ATMEL_LCDC_GUARD_TIME 1 37 #endif 38 39 #define ATMEL_LCDC_FIFO_SIZE 512 40 41 #define lcdc_readl(reg) __raw_readl((reg)) 42 #define lcdc_writel(reg, val) __raw_writel((val), (reg)) 43 44 /* 45 * the CLUT register map as following 46 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) 47 */ 48 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 49 { 50 lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) 51 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) 52 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), 53 panel_info.mmio + ATMEL_LCDC_LUT(regno)); 54 } 55 56 void lcd_ctrl_init(void *lcdbase) 57 { 58 unsigned long value; 59 struct lcd_dma_desc *desc; 60 struct atmel_hlcd_regs *regs; 61 62 if (!has_lcdc()) 63 return; /* No lcdc */ 64 65 regs = (struct atmel_hlcd_regs *)panel_info.mmio; 66 67 /* Disable DISP signal */ 68 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); 69 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 70 udelay(1); 71 /* Disable synchronization */ 72 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); 73 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 74 udelay(1); 75 /* Disable pixel clock */ 76 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); 77 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 78 udelay(1); 79 /* Disable PWM */ 80 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); 81 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 82 udelay(1); 83 84 /* Set pixel clock */ 85 value = get_lcdc_clk_rate(0) / panel_info.vl_clk; 86 if (get_lcdc_clk_rate(0) % panel_info.vl_clk) 87 value++; 88 89 if (value < 1) { 90 /* Using system clock as pixel clock */ 91 lcdc_writel(®s->lcdc_lcdcfg0, 92 LCDC_LCDCFG0_CLKDIV(0) 93 | LCDC_LCDCFG0_CGDISHCR 94 | LCDC_LCDCFG0_CGDISHEO 95 | LCDC_LCDCFG0_CGDISOVR1 96 | LCDC_LCDCFG0_CGDISBASE 97 | panel_info.vl_clk_pol 98 | LCDC_LCDCFG0_CLKSEL); 99 100 } else { 101 lcdc_writel(®s->lcdc_lcdcfg0, 102 LCDC_LCDCFG0_CLKDIV(value - 2) 103 | LCDC_LCDCFG0_CGDISHCR 104 | LCDC_LCDCFG0_CGDISHEO 105 | LCDC_LCDCFG0_CGDISOVR1 106 | LCDC_LCDCFG0_CGDISBASE 107 | panel_info.vl_clk_pol); 108 } 109 110 /* Initialize control register 5 */ 111 value = 0; 112 113 value |= panel_info.vl_sync; 114 115 #ifndef LCD_OUTPUT_BPP 116 /* Output is 24bpp */ 117 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 118 #else 119 switch (LCD_OUTPUT_BPP) { 120 case 12: 121 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; 122 break; 123 case 16: 124 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; 125 break; 126 case 18: 127 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; 128 break; 129 case 24: 130 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 131 break; 132 default: 133 BUG(); 134 break; 135 } 136 #endif 137 138 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); 139 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); 140 lcdc_writel(®s->lcdc_lcdcfg5, value); 141 142 /* Vertical & Horizontal Timing */ 143 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); 144 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); 145 lcdc_writel(®s->lcdc_lcdcfg1, value); 146 147 value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); 148 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); 149 lcdc_writel(®s->lcdc_lcdcfg2, value); 150 151 value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); 152 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); 153 lcdc_writel(®s->lcdc_lcdcfg3, value); 154 155 /* Display size */ 156 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); 157 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); 158 lcdc_writel(®s->lcdc_lcdcfg4, value); 159 160 lcdc_writel(®s->lcdc_basecfg0, 161 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); 162 163 switch (NBITS(panel_info.vl_bpix)) { 164 case 16: 165 lcdc_writel(®s->lcdc_basecfg1, 166 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); 167 break; 168 default: 169 BUG(); 170 break; 171 } 172 173 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); 174 lcdc_writel(®s->lcdc_basecfg3, 0); 175 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); 176 177 /* Disable all interrupts */ 178 lcdc_writel(®s->lcdc_lcdidr, ~0UL); 179 lcdc_writel(®s->lcdc_baseidr, ~0UL); 180 181 /* Setup the DMA descriptor, this descriptor will loop to itself */ 182 desc = (struct lcd_dma_desc *)(lcdbase - 16); 183 184 desc->address = (u32)lcdbase; 185 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ 186 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN 187 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; 188 desc->next = (u32)desc; 189 190 lcdc_writel(®s->lcdc_baseaddr, desc->address); 191 lcdc_writel(®s->lcdc_basectrl, desc->control); 192 lcdc_writel(®s->lcdc_basenext, desc->next); 193 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | 194 LCDC_BASECHER_UPDATEEN); 195 196 /* Enable LCD */ 197 value = lcdc_readl(®s->lcdc_lcden); 198 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); 199 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 200 udelay(1); 201 value = lcdc_readl(®s->lcdc_lcden); 202 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); 203 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 204 udelay(1); 205 value = lcdc_readl(®s->lcdc_lcden); 206 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); 207 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 208 udelay(1); 209 value = lcdc_readl(®s->lcdc_lcden); 210 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); 211 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 212 udelay(1); 213 } 214