1 /* 2 * Driver for AT91/AT32 MULTI LAYER LCD Controller 3 * 4 * Copyright (C) 2012 Atmel Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/clk.h> 29 #include <lcd.h> 30 #include <atmel_hlcdc.h> 31 32 int lcd_line_length; 33 int lcd_color_fg; 34 int lcd_color_bg; 35 36 void *lcd_base; /* Start of framebuffer memory */ 37 void *lcd_console_address; /* Start of console buffer */ 38 39 short console_col; 40 short console_row; 41 42 /* configurable parameters */ 43 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 44 #define ATMEL_LCDC_DMA_BURST_LEN 8 45 #ifndef ATMEL_LCDC_GUARD_TIME 46 #define ATMEL_LCDC_GUARD_TIME 1 47 #endif 48 49 #define ATMEL_LCDC_FIFO_SIZE 512 50 51 #define lcdc_readl(reg) __raw_readl((reg)) 52 #define lcdc_writel(reg, val) __raw_writel((val), (reg)) 53 54 /* 55 * the CLUT register map as following 56 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) 57 */ 58 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 59 { 60 lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) 61 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) 62 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), 63 panel_info.mmio + ATMEL_LCDC_LUT(regno)); 64 } 65 66 void lcd_ctrl_init(void *lcdbase) 67 { 68 unsigned long value; 69 struct lcd_dma_desc *desc; 70 struct atmel_hlcd_regs *regs; 71 72 if (!has_lcdc()) 73 return; /* No lcdc */ 74 75 regs = (struct atmel_hlcd_regs *)panel_info.mmio; 76 77 /* Disable DISP signal */ 78 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); 79 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 80 udelay(1); 81 /* Disable synchronization */ 82 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); 83 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 84 udelay(1); 85 /* Disable pixel clock */ 86 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); 87 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 88 udelay(1); 89 /* Disable PWM */ 90 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); 91 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 92 udelay(1); 93 94 /* Set pixel clock */ 95 value = get_lcdc_clk_rate(0) / panel_info.vl_clk; 96 if (get_lcdc_clk_rate(0) % panel_info.vl_clk) 97 value++; 98 99 if (value < 1) { 100 /* Using system clock as pixel clock */ 101 lcdc_writel(®s->lcdc_lcdcfg0, 102 LCDC_LCDCFG0_CLKDIV(0) 103 | LCDC_LCDCFG0_CGDISHCR 104 | LCDC_LCDCFG0_CGDISHEO 105 | LCDC_LCDCFG0_CGDISOVR1 106 | LCDC_LCDCFG0_CGDISBASE 107 | panel_info.vl_clk_pol 108 | LCDC_LCDCFG0_CLKSEL); 109 110 } else { 111 lcdc_writel(®s->lcdc_lcdcfg0, 112 LCDC_LCDCFG0_CLKDIV(value - 2) 113 | LCDC_LCDCFG0_CGDISHCR 114 | LCDC_LCDCFG0_CGDISHEO 115 | LCDC_LCDCFG0_CGDISOVR1 116 | LCDC_LCDCFG0_CGDISBASE 117 | panel_info.vl_clk_pol); 118 } 119 120 /* Initialize control register 5 */ 121 value = 0; 122 123 value |= panel_info.vl_sync; 124 125 #ifndef LCD_OUTPUT_BPP 126 /* Output is 24bpp */ 127 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 128 #else 129 switch (LCD_OUTPUT_BPP) { 130 case 12: 131 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; 132 break; 133 case 16: 134 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; 135 break; 136 case 18: 137 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; 138 break; 139 case 24: 140 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 141 break; 142 default: 143 BUG(); 144 break; 145 } 146 #endif 147 148 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); 149 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); 150 lcdc_writel(®s->lcdc_lcdcfg5, value); 151 152 /* Vertical & Horizontal Timing */ 153 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); 154 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); 155 lcdc_writel(®s->lcdc_lcdcfg1, value); 156 157 value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); 158 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); 159 lcdc_writel(®s->lcdc_lcdcfg2, value); 160 161 value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); 162 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); 163 lcdc_writel(®s->lcdc_lcdcfg3, value); 164 165 /* Display size */ 166 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); 167 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); 168 lcdc_writel(®s->lcdc_lcdcfg4, value); 169 170 lcdc_writel(®s->lcdc_basecfg0, 171 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); 172 173 switch (NBITS(panel_info.vl_bpix)) { 174 case 16: 175 lcdc_writel(®s->lcdc_basecfg1, 176 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); 177 break; 178 default: 179 BUG(); 180 break; 181 } 182 183 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); 184 lcdc_writel(®s->lcdc_basecfg3, 0); 185 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); 186 187 /* Disable all interrupts */ 188 lcdc_writel(®s->lcdc_lcdidr, ~0UL); 189 lcdc_writel(®s->lcdc_baseidr, ~0UL); 190 191 /* Setup the DMA descriptor, this descriptor will loop to itself */ 192 desc = (struct lcd_dma_desc *)(lcdbase - 16); 193 194 desc->address = (u32)lcdbase; 195 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ 196 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN 197 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; 198 desc->next = (u32)desc; 199 200 lcdc_writel(®s->lcdc_baseaddr, desc->address); 201 lcdc_writel(®s->lcdc_basectrl, desc->control); 202 lcdc_writel(®s->lcdc_basenext, desc->next); 203 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | 204 LCDC_BASECHER_UPDATEEN); 205 206 /* Enable LCD */ 207 value = lcdc_readl(®s->lcdc_lcden); 208 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); 209 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 210 udelay(1); 211 value = lcdc_readl(®s->lcdc_lcden); 212 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); 213 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 214 udelay(1); 215 value = lcdc_readl(®s->lcdc_lcden); 216 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); 217 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 218 udelay(1); 219 value = lcdc_readl(®s->lcdc_lcden); 220 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); 221 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 222 udelay(1); 223 } 224