1 /* 2 * Driver for AT91/AT32 MULTI LAYER LCD Controller 3 * 4 * Copyright (C) 2012 Atmel Corporation 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/clk.h> 29 #include <lcd.h> 30 #include <atmel_hlcdc.h> 31 32 int lcd_line_length; 33 int lcd_color_fg; 34 int lcd_color_bg; 35 36 void *lcd_base; /* Start of framebuffer memory */ 37 void *lcd_console_address; /* Start of console buffer */ 38 39 short console_col; 40 short console_row; 41 42 /* configurable parameters */ 43 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 44 #define ATMEL_LCDC_DMA_BURST_LEN 8 45 #ifndef ATMEL_LCDC_GUARD_TIME 46 #define ATMEL_LCDC_GUARD_TIME 1 47 #endif 48 49 #define ATMEL_LCDC_FIFO_SIZE 512 50 51 #define lcdc_readl(reg) __raw_readl((reg)) 52 #define lcdc_writel(reg, val) __raw_writel((val), (reg)) 53 54 void lcd_ctrl_init(void *lcdbase) 55 { 56 unsigned long value; 57 struct lcd_dma_desc *desc; 58 struct atmel_hlcd_regs *regs; 59 60 if (!has_lcdc()) 61 return; /* No lcdc */ 62 63 regs = (struct atmel_hlcd_regs *)panel_info.mmio; 64 65 /* Disable DISP signal */ 66 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); 67 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 68 udelay(1); 69 /* Disable synchronization */ 70 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); 71 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 72 udelay(1); 73 /* Disable pixel clock */ 74 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); 75 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 76 udelay(1); 77 /* Disable PWM */ 78 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); 79 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 80 udelay(1); 81 82 /* Set pixel clock */ 83 value = get_lcdc_clk_rate(0) / panel_info.vl_clk; 84 if (get_lcdc_clk_rate(0) % panel_info.vl_clk) 85 value++; 86 87 if (value < 1) { 88 /* Using system clock as pixel clock */ 89 lcdc_writel(®s->lcdc_lcdcfg0, 90 LCDC_LCDCFG0_CLKDIV(0) 91 | LCDC_LCDCFG0_CGDISHCR 92 | LCDC_LCDCFG0_CGDISHEO 93 | LCDC_LCDCFG0_CGDISOVR1 94 | LCDC_LCDCFG0_CGDISBASE 95 | panel_info.vl_clk_pol 96 | LCDC_LCDCFG0_CLKSEL); 97 98 } else { 99 lcdc_writel(®s->lcdc_lcdcfg0, 100 LCDC_LCDCFG0_CLKDIV(value - 2) 101 | LCDC_LCDCFG0_CGDISHCR 102 | LCDC_LCDCFG0_CGDISHEO 103 | LCDC_LCDCFG0_CGDISOVR1 104 | LCDC_LCDCFG0_CGDISBASE 105 | panel_info.vl_clk_pol); 106 } 107 108 /* Initialize control register 5 */ 109 value = 0; 110 111 value |= panel_info.vl_sync; 112 113 #ifndef LCD_OUTPUT_BPP 114 /* Output is 24bpp */ 115 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 116 #else 117 switch (LCD_OUTPUT_BPP) { 118 case 12: 119 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; 120 break; 121 case 16: 122 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; 123 break; 124 case 18: 125 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; 126 break; 127 case 24: 128 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; 129 break; 130 default: 131 BUG(); 132 break; 133 } 134 #endif 135 136 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); 137 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); 138 lcdc_writel(®s->lcdc_lcdcfg5, value); 139 140 /* Vertical & Horizontal Timing */ 141 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); 142 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); 143 lcdc_writel(®s->lcdc_lcdcfg1, value); 144 145 value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); 146 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); 147 lcdc_writel(®s->lcdc_lcdcfg2, value); 148 149 value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); 150 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); 151 lcdc_writel(®s->lcdc_lcdcfg3, value); 152 153 /* Display size */ 154 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); 155 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); 156 lcdc_writel(®s->lcdc_lcdcfg4, value); 157 158 lcdc_writel(®s->lcdc_basecfg0, 159 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); 160 161 switch (NBITS(panel_info.vl_bpix)) { 162 case 16: 163 lcdc_writel(®s->lcdc_basecfg1, 164 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); 165 break; 166 default: 167 BUG(); 168 break; 169 } 170 171 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); 172 lcdc_writel(®s->lcdc_basecfg3, 0); 173 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); 174 175 /* Disable all interrupts */ 176 lcdc_writel(®s->lcdc_lcdidr, ~0UL); 177 lcdc_writel(®s->lcdc_baseidr, ~0UL); 178 179 /* Setup the DMA descriptor, this descriptor will loop to itself */ 180 desc = (struct lcd_dma_desc *)(lcdbase - 16); 181 182 desc->address = (u32)lcdbase; 183 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ 184 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN 185 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; 186 desc->next = (u32)desc; 187 188 lcdc_writel(®s->lcdc_baseaddr, desc->address); 189 lcdc_writel(®s->lcdc_basectrl, desc->control); 190 lcdc_writel(®s->lcdc_basenext, desc->next); 191 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | 192 LCDC_BASECHER_UPDATEEN); 193 194 /* Enable LCD */ 195 value = lcdc_readl(®s->lcdc_lcden); 196 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); 197 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) 198 udelay(1); 199 value = lcdc_readl(®s->lcdc_lcden); 200 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); 201 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) 202 udelay(1); 203 value = lcdc_readl(®s->lcdc_lcden); 204 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); 205 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) 206 udelay(1); 207 value = lcdc_readl(®s->lcdc_lcden); 208 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); 209 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) 210 udelay(1); 211 } 212