1352d2591SJean-Christophe PLAGNIOL-VILLARD /* 2352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI Radeon Video card Framebuffer driver. 3352d2591SJean-Christophe PLAGNIOL-VILLARD * 4352d2591SJean-Christophe PLAGNIOL-VILLARD * Copyright 2007 Freescale Semiconductor, Inc. 5352d2591SJean-Christophe PLAGNIOL-VILLARD * Zhang Wei <wei.zhang@freescale.com> 6352d2591SJean-Christophe PLAGNIOL-VILLARD * Jason Jin <jason.jin@freescale.com> 7352d2591SJean-Christophe PLAGNIOL-VILLARD * 8352d2591SJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 9352d2591SJean-Christophe PLAGNIOL-VILLARD * project. 10352d2591SJean-Christophe PLAGNIOL-VILLARD * 11352d2591SJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 12352d2591SJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 13352d2591SJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 14352d2591SJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 15352d2591SJean-Christophe PLAGNIOL-VILLARD * 16352d2591SJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 17352d2591SJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 18352d2591SJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19352d2591SJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 20352d2591SJean-Christophe PLAGNIOL-VILLARD * 21352d2591SJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 22352d2591SJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 23352d2591SJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24352d2591SJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 25352d2591SJean-Christophe PLAGNIOL-VILLARD * 26352d2591SJean-Christophe PLAGNIOL-VILLARD * Some codes of this file is partly ported from Linux kernel 27352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI video framebuffer driver. 28352d2591SJean-Christophe PLAGNIOL-VILLARD * 29352d2591SJean-Christophe PLAGNIOL-VILLARD * Now the driver is tested on below ATI chips: 30352d2591SJean-Christophe PLAGNIOL-VILLARD * 9200 31352d2591SJean-Christophe PLAGNIOL-VILLARD * X300 32352d2591SJean-Christophe PLAGNIOL-VILLARD * X700 33352d2591SJean-Christophe PLAGNIOL-VILLARD * 34352d2591SJean-Christophe PLAGNIOL-VILLARD */ 35352d2591SJean-Christophe PLAGNIOL-VILLARD 36352d2591SJean-Christophe PLAGNIOL-VILLARD #include <common.h> 37352d2591SJean-Christophe PLAGNIOL-VILLARD 38352d2591SJean-Christophe PLAGNIOL-VILLARD #include <command.h> 39352d2591SJean-Christophe PLAGNIOL-VILLARD #include <pci.h> 40352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/processor.h> 41352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/errno.h> 42352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 43352d2591SJean-Christophe PLAGNIOL-VILLARD #include <malloc.h> 44352d2591SJean-Christophe PLAGNIOL-VILLARD #include <video_fb.h> 451b8607e1SAnatolij Gustschin #include "videomodes.h" 46352d2591SJean-Christophe PLAGNIOL-VILLARD 47352d2591SJean-Christophe PLAGNIOL-VILLARD #include <radeon.h> 48352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_ids.h" 49352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_radeon_fb.h" 50352d2591SJean-Christophe PLAGNIOL-VILLARD 51352d2591SJean-Christophe PLAGNIOL-VILLARD #undef DEBUG 52352d2591SJean-Christophe PLAGNIOL-VILLARD 53352d2591SJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG 54352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) printf(x) 55352d2591SJean-Christophe PLAGNIOL-VILLARD #else 56352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) do{}while(0) 57352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 58352d2591SJean-Christophe PLAGNIOL-VILLARD 59352d2591SJean-Christophe PLAGNIOL-VILLARD #ifndef min_t 60352d2591SJean-Christophe PLAGNIOL-VILLARD #define min_t(type,x,y) \ 61352d2591SJean-Christophe PLAGNIOL-VILLARD ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 62352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 63352d2591SJean-Christophe PLAGNIOL-VILLARD 64352d2591SJean-Christophe PLAGNIOL-VILLARD #define MAX_MAPPED_VRAM (2048*2048*4) 65352d2591SJean-Christophe PLAGNIOL-VILLARD #define MIN_MAPPED_VRAM (1024*768*1) 66352d2591SJean-Christophe PLAGNIOL-VILLARD 671b8607e1SAnatolij Gustschin #define RADEON_BUFFER_ALIGN 0x00000fff 681b8607e1SAnatolij Gustschin #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ 691b8607e1SAnatolij Gustschin & ~RADEON_BUFFER_ALIGN) - 1) 701b8607e1SAnatolij Gustschin #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ 711b8607e1SAnatolij Gustschin ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) 721b8607e1SAnatolij Gustschin 731b8607e1SAnatolij Gustschin #define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ 741b8607e1SAnatolij Gustschin (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) 751b8607e1SAnatolij Gustschin #define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ 761b8607e1SAnatolij Gustschin (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) 771b8607e1SAnatolij Gustschin #define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ 781b8607e1SAnatolij Gustschin ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) 791b8607e1SAnatolij Gustschin #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ 801b8607e1SAnatolij Gustschin ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) 811b8607e1SAnatolij Gustschin 82352d2591SJean-Christophe PLAGNIOL-VILLARD /*#define PCI_VENDOR_ID_ATI*/ 83352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5960 0x5960 84352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5961 0x5961 85352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5962 0x5962 86352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5964 0x5964 87e5c6f9f8SAnatolij Gustschin #define PCI_CHIP_RV280_5C63 0x5C63 88352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B60 0x5B60 89352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_5657 0x5657 90352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_554d 0x554d 91352d2591SJean-Christophe PLAGNIOL-VILLARD 92352d2591SJean-Christophe PLAGNIOL-VILLARD static struct pci_device_id ati_radeon_pci_ids[] = { 93352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, 94352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, 95352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, 96352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, 97e5c6f9f8SAnatolij Gustschin {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, 98352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, 99352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, 100352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, 101352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 102352d2591SJean-Christophe PLAGNIOL-VILLARD }; 103352d2591SJean-Christophe PLAGNIOL-VILLARD 104352d2591SJean-Christophe PLAGNIOL-VILLARD static u16 ati_radeon_id_family_table[][2] = { 105352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, 106352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, 107352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, 108352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, 109e5c6f9f8SAnatolij Gustschin {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, 110352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, 111352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, 112352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, 113352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 114352d2591SJean-Christophe PLAGNIOL-VILLARD }; 115352d2591SJean-Christophe PLAGNIOL-VILLARD 116352d2591SJean-Christophe PLAGNIOL-VILLARD u16 get_radeon_id_family(u16 device) 117352d2591SJean-Christophe PLAGNIOL-VILLARD { 118352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 119352d2591SJean-Christophe PLAGNIOL-VILLARD for (i=0; ati_radeon_id_family_table[0][i]; i+=2) 120352d2591SJean-Christophe PLAGNIOL-VILLARD if (ati_radeon_id_family_table[0][i] == device) 121352d2591SJean-Christophe PLAGNIOL-VILLARD return ati_radeon_id_family_table[0][i + 1]; 122352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 123352d2591SJean-Christophe PLAGNIOL-VILLARD } 124352d2591SJean-Christophe PLAGNIOL-VILLARD 125352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeonfb_info *rinfo; 126352d2591SJean-Christophe PLAGNIOL-VILLARD 127352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_identify_vram(struct radeonfb_info *rinfo) 128352d2591SJean-Christophe PLAGNIOL-VILLARD { 129352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tmp; 130352d2591SJean-Christophe PLAGNIOL-VILLARD 131352d2591SJean-Christophe PLAGNIOL-VILLARD /* framebuffer size */ 132352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 133352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200) || 134352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS300)) { 135352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tom = INREG(NB_TOM); 136352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 137352d2591SJean-Christophe PLAGNIOL-VILLARD 138352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(6); 139352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(MC_FB_LOCATION, tom); 140352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 141352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 142352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 143352d2591SJean-Christophe PLAGNIOL-VILLARD 144352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is supposed to fix the crtc2 noise problem. */ 145352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 146352d2591SJean-Christophe PLAGNIOL-VILLARD 147352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 148352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)) { 149352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is to workaround the asic bug for RMX, some versions 150352d2591SJean-Christophe PLAGNIOL-VILLARD of BIOS dosen't have this register initialized correctly. 151352d2591SJean-Christophe PLAGNIOL-VILLARD */ 152352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 153352d2591SJean-Christophe PLAGNIOL-VILLARD ~CRTC_H_CUTOFF_ACTIVE_EN); 154352d2591SJean-Christophe PLAGNIOL-VILLARD } 155352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 156352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(CONFIG_MEMSIZE); 157352d2591SJean-Christophe PLAGNIOL-VILLARD } 158352d2591SJean-Christophe PLAGNIOL-VILLARD 159352d2591SJean-Christophe PLAGNIOL-VILLARD /* mem size is bits [28:0], mask off the rest */ 160352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; 161352d2591SJean-Christophe PLAGNIOL-VILLARD 162352d2591SJean-Christophe PLAGNIOL-VILLARD /* 163352d2591SJean-Christophe PLAGNIOL-VILLARD * Hack to get around some busted production M6's 164352d2591SJean-Christophe PLAGNIOL-VILLARD * reporting no ram 165352d2591SJean-Christophe PLAGNIOL-VILLARD */ 166352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->video_ram == 0) { 167352d2591SJean-Christophe PLAGNIOL-VILLARD switch (rinfo->pdev.device) { 168352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LY: 169352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LZ: 170352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = 8192 * 1024; 171352d2591SJean-Christophe PLAGNIOL-VILLARD break; 172352d2591SJean-Christophe PLAGNIOL-VILLARD default: 173352d2591SJean-Christophe PLAGNIOL-VILLARD break; 174352d2591SJean-Christophe PLAGNIOL-VILLARD } 175352d2591SJean-Christophe PLAGNIOL-VILLARD } 176352d2591SJean-Christophe PLAGNIOL-VILLARD 177352d2591SJean-Christophe PLAGNIOL-VILLARD /* 178352d2591SJean-Christophe PLAGNIOL-VILLARD * Now try to identify VRAM type 179352d2591SJean-Christophe PLAGNIOL-VILLARD */ 180352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family >= CHIP_FAMILY_R300) || 181352d2591SJean-Christophe PLAGNIOL-VILLARD (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 182352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 1; 183352d2591SJean-Christophe PLAGNIOL-VILLARD else 184352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 0; 185352d2591SJean-Christophe PLAGNIOL-VILLARD 186352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(MEM_CNTL); 187352d2591SJean-Christophe PLAGNIOL-VILLARD if (IS_R300_VARIANT(rinfo)) { 188352d2591SJean-Christophe PLAGNIOL-VILLARD tmp &= R300_MEM_NUM_CHANNELS_MASK; 189352d2591SJean-Christophe PLAGNIOL-VILLARD switch (tmp) { 190352d2591SJean-Christophe PLAGNIOL-VILLARD case 0: rinfo->vram_width = 64; break; 191352d2591SJean-Christophe PLAGNIOL-VILLARD case 1: rinfo->vram_width = 128; break; 192352d2591SJean-Christophe PLAGNIOL-VILLARD case 2: rinfo->vram_width = 256; break; 193352d2591SJean-Christophe PLAGNIOL-VILLARD default: rinfo->vram_width = 128; break; 194352d2591SJean-Christophe PLAGNIOL-VILLARD } 195352d2591SJean-Christophe PLAGNIOL-VILLARD } else if ((rinfo->family == CHIP_FAMILY_RV100) || 196352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS100) || 197352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)){ 198352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & RV100_MEM_HALF_MODE) 199352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 32; 200352d2591SJean-Christophe PLAGNIOL-VILLARD else 201352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 202352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 203352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & MEM_NUM_CHANNELS_MASK) 204352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 128; 205352d2591SJean-Christophe PLAGNIOL-VILLARD else 206352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 207352d2591SJean-Christophe PLAGNIOL-VILLARD } 208352d2591SJean-Christophe PLAGNIOL-VILLARD 209352d2591SJean-Christophe PLAGNIOL-VILLARD /* This may not be correct, as some cards can have half of channel disabled 210352d2591SJean-Christophe PLAGNIOL-VILLARD * ToDo: identify these cases 211352d2591SJean-Christophe PLAGNIOL-VILLARD */ 212352d2591SJean-Christophe PLAGNIOL-VILLARD 213352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", 214352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram / 1024, 215352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr ? "DDR" : "SDRAM", 216352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width); 217352d2591SJean-Christophe PLAGNIOL-VILLARD 218352d2591SJean-Christophe PLAGNIOL-VILLARD } 219352d2591SJean-Christophe PLAGNIOL-VILLARD 220352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 221352d2591SJean-Christophe PLAGNIOL-VILLARD { 222352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 223352d2591SJean-Christophe PLAGNIOL-VILLARD 224352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(20); 225352d2591SJean-Christophe PLAGNIOL-VILLARD 226352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 227352d2591SJean-Christophe PLAGNIOL-VILLARD /* Workaround from XFree */ 228352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->is_mobility) { 229352d2591SJean-Christophe PLAGNIOL-VILLARD /* A temporal workaround for the occational blanking on certain laptop 230352d2591SJean-Christophe PLAGNIOL-VILLARD * panels. This appears to related to the PLL divider registers 231352d2591SJean-Christophe PLAGNIOL-VILLARD * (fail to lock?). It occurs even when all dividers are the same 232352d2591SJean-Christophe PLAGNIOL-VILLARD * with their old settings. In this case we really don't need to 233352d2591SJean-Christophe PLAGNIOL-VILLARD * fiddle with PLL registers. By doing this we can avoid the blanking 234352d2591SJean-Christophe PLAGNIOL-VILLARD * problem with some panels. 235352d2591SJean-Christophe PLAGNIOL-VILLARD */ 236352d2591SJean-Christophe PLAGNIOL-VILLARD if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 237352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 238352d2591SJean-Christophe PLAGNIOL-VILLARD (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 239352d2591SJean-Christophe PLAGNIOL-VILLARD /* We still have to force a switch to selected PPLL div thanks to 240352d2591SJean-Christophe PLAGNIOL-VILLARD * an XFree86 driver bug which will switch it away in some cases 241352d2591SJean-Christophe PLAGNIOL-VILLARD * even when using UseFDev */ 242352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 243352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 244352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 245352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_index(rinfo); 246352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_data(rinfo); 247352d2591SJean-Christophe PLAGNIOL-VILLARD return; 248352d2591SJean-Christophe PLAGNIOL-VILLARD } 249352d2591SJean-Christophe PLAGNIOL-VILLARD } 250352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 251352d2591SJean-Christophe PLAGNIOL-VILLARD if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; 252352d2591SJean-Christophe PLAGNIOL-VILLARD 253352d2591SJean-Christophe PLAGNIOL-VILLARD /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 254352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 255352d2591SJean-Christophe PLAGNIOL-VILLARD 256352d2591SJean-Christophe PLAGNIOL-VILLARD /* Reset PPLL & enable atomic update */ 257352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 258352d2591SJean-Christophe PLAGNIOL-VILLARD PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 259352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 260352d2591SJean-Christophe PLAGNIOL-VILLARD 261352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch to selected PPLL divider */ 262352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 263352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 264352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 265352d2591SJean-Christophe PLAGNIOL-VILLARD 266352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL ref. div */ 267352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->family == CHIP_FAMILY_R300 || 268352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RS300 || 269352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_R350 || 270352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RV350) { 271352d2591SJean-Christophe PLAGNIOL-VILLARD if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 272352d2591SJean-Christophe PLAGNIOL-VILLARD /* When restoring console mode, use saved PPLL_REF_DIV 273352d2591SJean-Christophe PLAGNIOL-VILLARD * setting. 274352d2591SJean-Christophe PLAGNIOL-VILLARD */ 275352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 276352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 277352d2591SJean-Christophe PLAGNIOL-VILLARD /* R300 uses ref_div_acc field as real ref divider */ 278352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, 279352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 280352d2591SJean-Christophe PLAGNIOL-VILLARD ~R300_PPLL_REF_DIV_ACC_MASK); 281352d2591SJean-Christophe PLAGNIOL-VILLARD } 282352d2591SJean-Christophe PLAGNIOL-VILLARD } else 283352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 284352d2591SJean-Christophe PLAGNIOL-VILLARD 285352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL divider 3 & post divider*/ 286352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 287352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 288352d2591SJean-Christophe PLAGNIOL-VILLARD 289352d2591SJean-Christophe PLAGNIOL-VILLARD /* Write update */ 290352d2591SJean-Christophe PLAGNIOL-VILLARD while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 291352d2591SJean-Christophe PLAGNIOL-VILLARD ; 292352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 293352d2591SJean-Christophe PLAGNIOL-VILLARD 294352d2591SJean-Christophe PLAGNIOL-VILLARD /* Wait read update complete */ 295352d2591SJean-Christophe PLAGNIOL-VILLARD /* FIXME: Certain revisions of R300 can't recover here. Not sure of 296352d2591SJean-Christophe PLAGNIOL-VILLARD the cause yet, but this workaround will mask the problem for now. 297352d2591SJean-Christophe PLAGNIOL-VILLARD Other chips usually will pass at the very first test, so the 298352d2591SJean-Christophe PLAGNIOL-VILLARD workaround shouldn't have any effect on them. */ 299352d2591SJean-Christophe PLAGNIOL-VILLARD for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 300352d2591SJean-Christophe PLAGNIOL-VILLARD ; 301352d2591SJean-Christophe PLAGNIOL-VILLARD 302352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLL(HTOTAL_CNTL, 0); 303352d2591SJean-Christophe PLAGNIOL-VILLARD 304352d2591SJean-Christophe PLAGNIOL-VILLARD /* Clear reset & atomic update */ 305352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 0, 306352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 307352d2591SJean-Christophe PLAGNIOL-VILLARD 308352d2591SJean-Christophe PLAGNIOL-VILLARD /* We may want some locking ... oh well */ 309352d2591SJean-Christophe PLAGNIOL-VILLARD udelay(5000); 310352d2591SJean-Christophe PLAGNIOL-VILLARD 311352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch back VCLK source to PPLL */ 312352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 313352d2591SJean-Christophe PLAGNIOL-VILLARD } 314352d2591SJean-Christophe PLAGNIOL-VILLARD 315352d2591SJean-Christophe PLAGNIOL-VILLARD typedef struct { 316352d2591SJean-Christophe PLAGNIOL-VILLARD u16 reg; 317352d2591SJean-Christophe PLAGNIOL-VILLARD u32 val; 318352d2591SJean-Christophe PLAGNIOL-VILLARD } reg_val; 319352d2591SJean-Christophe PLAGNIOL-VILLARD 320352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 /* unused ? -> scheduled for removal */ 321352d2591SJean-Christophe PLAGNIOL-VILLARD /* these common regs are cleared before mode setting so they do not 322352d2591SJean-Christophe PLAGNIOL-VILLARD * interfere with anything 323352d2591SJean-Christophe PLAGNIOL-VILLARD */ 324352d2591SJean-Christophe PLAGNIOL-VILLARD static reg_val common_regs[] = { 325352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_CLR, 0 }, 326352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_LEFT_RIGHT, 0 }, 327352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_TOP_BOTTOM, 0 }, 328352d2591SJean-Christophe PLAGNIOL-VILLARD { OV0_SCALE_CNTL, 0 }, 329352d2591SJean-Christophe PLAGNIOL-VILLARD { SUBPIC_CNTL, 0 }, 330352d2591SJean-Christophe PLAGNIOL-VILLARD { VIPH_CONTROL, 0 }, 331352d2591SJean-Christophe PLAGNIOL-VILLARD { I2C_CNTL_1, 0 }, 332352d2591SJean-Christophe PLAGNIOL-VILLARD { GEN_INT_CNTL, 0 }, 333352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP0_TRIG_CNTL, 0 }, 334352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP1_TRIG_CNTL, 0 }, 335352d2591SJean-Christophe PLAGNIOL-VILLARD }; 336352d2591SJean-Christophe PLAGNIOL-VILLARD #endif /* 0 */ 337352d2591SJean-Christophe PLAGNIOL-VILLARD 338352d2591SJean-Christophe PLAGNIOL-VILLARD void radeon_setmode(void) 339352d2591SJean-Christophe PLAGNIOL-VILLARD { 340352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 341352d2591SJean-Christophe PLAGNIOL-VILLARD 342352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_gen_cntl = 0x03000200; 343352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_ext_cntl = 0x00008048; 344352d2591SJean-Christophe PLAGNIOL-VILLARD mode->dac_cntl = 0xff002100; 345352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_total_disp = 0x4f0063; 346352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_sync_strt_wid = 0x8c02a2; 347352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_total_disp = 0x01df020c; 348352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_sync_strt_wid = 0x8201ea; 349352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_pitch = 0x00500050; 350352d2591SJean-Christophe PLAGNIOL-VILLARD 351352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 352352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 353352d2591SJean-Christophe PLAGNIOL-VILLARD ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 354352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 355352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 356352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 357352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 358352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 359352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET, 0); 360352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET_CNTL, 0); 361352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_PITCH, mode->crtc_pitch); 362352d2591SJean-Christophe PLAGNIOL-VILLARD 363352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index = 0x300; 364352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_ref_div = 0xc; 365352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_div_3 = 0x00030059; 366352d2591SJean-Christophe PLAGNIOL-VILLARD 367352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_write_pll_regs(rinfo, mode); 368352d2591SJean-Christophe PLAGNIOL-VILLARD } 369352d2591SJean-Christophe PLAGNIOL-VILLARD 3701b8607e1SAnatolij Gustschin static void set_pal(void) 3711b8607e1SAnatolij Gustschin { 3721b8607e1SAnatolij Gustschin int idx, val = 0; 3731b8607e1SAnatolij Gustschin 3741b8607e1SAnatolij Gustschin for (idx = 0; idx < 256; idx++) { 3751b8607e1SAnatolij Gustschin OUTREG8(PALETTE_INDEX, idx); 3761b8607e1SAnatolij Gustschin OUTREG(PALETTE_DATA, val); 3771b8607e1SAnatolij Gustschin val += 0x00010101; 3781b8607e1SAnatolij Gustschin } 3791b8607e1SAnatolij Gustschin } 3801b8607e1SAnatolij Gustschin 3811b8607e1SAnatolij Gustschin void radeon_setmode_9200(int vesa_idx, int bpp) 3821b8607e1SAnatolij Gustschin { 3831b8607e1SAnatolij Gustschin struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 3841b8607e1SAnatolij Gustschin 3851b8607e1SAnatolij Gustschin mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; 3861b8607e1SAnatolij Gustschin mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; 3871b8607e1SAnatolij Gustschin mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; 3881b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; 3891b8607e1SAnatolij Gustschin 3901b8607e1SAnatolij Gustschin switch (bpp) { 3911b8607e1SAnatolij Gustschin case 24: 3921b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ 3931b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 3941b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 3951b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 3961b8607e1SAnatolij Gustschin #endif 3971b8607e1SAnatolij Gustschin break; 3981b8607e1SAnatolij Gustschin case 16: 3991b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ 4001b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 4011b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 4021b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 4031b8607e1SAnatolij Gustschin #endif 4041b8607e1SAnatolij Gustschin break; 4051b8607e1SAnatolij Gustschin default: 4061b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ 4071b8607e1SAnatolij Gustschin mode->surface_cntl = 0x00000000; 4081b8607e1SAnatolij Gustschin break; 4091b8607e1SAnatolij Gustschin } 4101b8607e1SAnatolij Gustschin 4111b8607e1SAnatolij Gustschin switch (vesa_idx) { 4121b8607e1SAnatolij Gustschin case RES_MODE_1280x1024: 4131b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); 4141b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); 4151b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); 4161b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4171b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); 4181b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010078; 4191b8607e1SAnatolij Gustschin #else /* default @ 60 Hz */ 4201b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); 4211b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010060; 4221b8607e1SAnatolij Gustschin #endif 4231b8607e1SAnatolij Gustschin /* 4241b8607e1SAnatolij Gustschin * for this mode pitch expands to the same value for 32, 16 and 8 bpp, 4251b8607e1SAnatolij Gustschin * so we set it here once only. 4261b8607e1SAnatolij Gustschin */ 4271b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); 4281b8607e1SAnatolij Gustschin switch (bpp) { 4291b8607e1SAnatolij Gustschin case 24: 4301b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); 4311b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); 4321b8607e1SAnatolij Gustschin break; 4331b8607e1SAnatolij Gustschin case 16: 4341b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); 4351b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); 4361b8607e1SAnatolij Gustschin break; 4371b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4381b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); 4391b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); 4401b8607e1SAnatolij Gustschin break; 4411b8607e1SAnatolij Gustschin } 4421b8607e1SAnatolij Gustschin break; 4431b8607e1SAnatolij Gustschin case RES_MODE_1024x768: 4441b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4451b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); 4461b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); 4471b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); 4481b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); 4491b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0002008c; 4501b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 4511b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); 4521b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; 4531b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); 4541b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; 4551b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00020074; 4561b8607e1SAnatolij Gustschin #endif 4571b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 4581b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); 4591b8607e1SAnatolij Gustschin switch (bpp) { 4601b8607e1SAnatolij Gustschin case 24: 4611b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); 4621b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); 4631b8607e1SAnatolij Gustschin break; 4641b8607e1SAnatolij Gustschin case 16: 4651b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); 4661b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); 4671b8607e1SAnatolij Gustschin break; 4681b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4691b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 4701b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); 4711b8607e1SAnatolij Gustschin break; 4721b8607e1SAnatolij Gustschin } 4731b8607e1SAnatolij Gustschin break; 4741b8607e1SAnatolij Gustschin case RES_MODE_800x600: 4751b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); 4761b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4771b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); 4781b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); 4791b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); 4801b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x000300b0; 4811b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 4821b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); 4831b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); 4841b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); 4851b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0003008e; 4861b8607e1SAnatolij Gustschin #endif 4871b8607e1SAnatolij Gustschin switch (bpp) { 4881b8607e1SAnatolij Gustschin case 24: 4891b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(832,32); 4901b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); 4911b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); 4921b8607e1SAnatolij Gustschin break; 4931b8607e1SAnatolij Gustschin case 16: 4941b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(896,16); 4951b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); 4961b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); 4971b8607e1SAnatolij Gustschin break; 4981b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4991b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); 5001b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 5011b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); 5021b8607e1SAnatolij Gustschin break; 5031b8607e1SAnatolij Gustschin } 5041b8607e1SAnatolij Gustschin break; 5051b8607e1SAnatolij Gustschin default: /* RES_MODE_640x480 */ 5061b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 5071b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); 5081b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; 5091b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); 5101b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; 5111b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030070; 5121b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 5131b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); 5141b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; 5151b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); 5161b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; 5171b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030059; 5181b8607e1SAnatolij Gustschin #endif 5191b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 5201b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(640,32); 5211b8607e1SAnatolij Gustschin switch (bpp) { 5221b8607e1SAnatolij Gustschin case 24: 5231b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); 5241b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); 5251b8607e1SAnatolij Gustschin break; 5261b8607e1SAnatolij Gustschin case 16: 5271b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); 5281b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); 5291b8607e1SAnatolij Gustschin break; 5301b8607e1SAnatolij Gustschin default: /* 8 bpp */ 5311b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = 0x00000000; 5321b8607e1SAnatolij Gustschin break; 5331b8607e1SAnatolij Gustschin } 5341b8607e1SAnatolij Gustschin break; 5351b8607e1SAnatolij Gustschin } 5361b8607e1SAnatolij Gustschin 5371b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 5381b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 5391b8607e1SAnatolij Gustschin (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 5401b8607e1SAnatolij Gustschin OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 5411b8607e1SAnatolij Gustschin OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 5421b8607e1SAnatolij Gustschin OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 5431b8607e1SAnatolij Gustschin OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 5441b8607e1SAnatolij Gustschin OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 5451b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET, 0); 5461b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); 5471b8607e1SAnatolij Gustschin OUTREG(CRTC_PITCH, mode->crtc_pitch); 5481b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 5491b8607e1SAnatolij Gustschin 5501b8607e1SAnatolij Gustschin mode->clk_cntl_index = 0x300; 5511b8607e1SAnatolij Gustschin mode->ppll_ref_div = 0xc; 5521b8607e1SAnatolij Gustschin 5531b8607e1SAnatolij Gustschin radeon_write_pll_regs(rinfo, mode); 5541b8607e1SAnatolij Gustschin 5551b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 5561b8607e1SAnatolij Gustschin ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 5571b8607e1SAnatolij Gustschin OUTREG(SURFACE0_INFO, mode->surf_info[0]); 5581b8607e1SAnatolij Gustschin OUTREG(SURFACE0_LOWER_BOUND, 0); 5591b8607e1SAnatolij Gustschin OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); 5601b8607e1SAnatolij Gustschin OUTREG(SURFACE_CNTL, mode->surface_cntl); 5611b8607e1SAnatolij Gustschin 5621b8607e1SAnatolij Gustschin if (bpp > 8) 5631b8607e1SAnatolij Gustschin set_pal(); 5641b8607e1SAnatolij Gustschin 5651b8607e1SAnatolij Gustschin free(mode); 5661b8607e1SAnatolij Gustschin } 5671b8607e1SAnatolij Gustschin 568352d2591SJean-Christophe PLAGNIOL-VILLARD #include "../bios_emulator/include/biosemu.h" 569352d2591SJean-Christophe PLAGNIOL-VILLARD extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); 570352d2591SJean-Christophe PLAGNIOL-VILLARD 571352d2591SJean-Christophe PLAGNIOL-VILLARD int radeon_probe(struct radeonfb_info *rinfo) 572352d2591SJean-Christophe PLAGNIOL-VILLARD { 573352d2591SJean-Christophe PLAGNIOL-VILLARD pci_dev_t pdev; 574352d2591SJean-Christophe PLAGNIOL-VILLARD u16 did; 575352d2591SJean-Christophe PLAGNIOL-VILLARD 576352d2591SJean-Christophe PLAGNIOL-VILLARD pdev = pci_find_devices(ati_radeon_pci_ids, 0); 577352d2591SJean-Christophe PLAGNIOL-VILLARD 578352d2591SJean-Christophe PLAGNIOL-VILLARD if (pdev != -1) { 579352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 580352d2591SJean-Christophe PLAGNIOL-VILLARD printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", 581352d2591SJean-Christophe PLAGNIOL-VILLARD PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, 582352d2591SJean-Christophe PLAGNIOL-VILLARD (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 583352d2591SJean-Christophe PLAGNIOL-VILLARD 584352d2591SJean-Christophe PLAGNIOL-VILLARD strcpy(rinfo->name, "ATI Radeon"); 585352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; 586352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.device = did; 587352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family = get_radeon_id_family(rinfo->pdev.device); 588352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, 589352d2591SJean-Christophe PLAGNIOL-VILLARD &rinfo->fb_base_phys); 590352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, 591352d2591SJean-Christophe PLAGNIOL-VILLARD &rinfo->mmio_base_phys); 592352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base_phys &= 0xfffff000; 593352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mmio_base_phys &= ~0x04; 594352d2591SJean-Christophe PLAGNIOL-VILLARD 595352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mmio_base = (void *)rinfo->mmio_base_phys; 596352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); 597352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 598352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); 599352d2591SJean-Christophe PLAGNIOL-VILLARD /* PostBIOS with x86 emulater */ 600*9624f6d9SEd Swarthout if (!BootVideoCardBIOS(pdev, NULL, 0)) 601*9624f6d9SEd Swarthout return -1; 602352d2591SJean-Christophe PLAGNIOL-VILLARD 603352d2591SJean-Christophe PLAGNIOL-VILLARD /* 604352d2591SJean-Christophe PLAGNIOL-VILLARD * Check for errata 605352d2591SJean-Christophe PLAGNIOL-VILLARD * (These will be added in the future for the chipfamily 606352d2591SJean-Christophe PLAGNIOL-VILLARD * R300, RV200, RS200, RV100, RS100.) 607352d2591SJean-Christophe PLAGNIOL-VILLARD */ 608352d2591SJean-Christophe PLAGNIOL-VILLARD 609352d2591SJean-Christophe PLAGNIOL-VILLARD /* Get VRAM size and type */ 610352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_identify_vram(rinfo); 611352d2591SJean-Christophe PLAGNIOL-VILLARD 612352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, 613352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram); 614352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base = (void *)rinfo->fb_base_phys; 615352d2591SJean-Christophe PLAGNIOL-VILLARD 616352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("Radeon: framebuffer base phy address 0x%08x," \ 617352d2591SJean-Christophe PLAGNIOL-VILLARD "MMIO base phy address 0x%08x," \ 618352d2591SJean-Christophe PLAGNIOL-VILLARD "framebuffer local base 0x%08x.\n ", 619352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base_phys, rinfo->mmio_base_phys, 620352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base); 621352d2591SJean-Christophe PLAGNIOL-VILLARD 622352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 623352d2591SJean-Christophe PLAGNIOL-VILLARD } 624352d2591SJean-Christophe PLAGNIOL-VILLARD return -1; 625352d2591SJean-Christophe PLAGNIOL-VILLARD } 626352d2591SJean-Christophe PLAGNIOL-VILLARD 627352d2591SJean-Christophe PLAGNIOL-VILLARD /* 628352d2591SJean-Christophe PLAGNIOL-VILLARD * The Graphic Device 629352d2591SJean-Christophe PLAGNIOL-VILLARD */ 630352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice ctfb; 631352d2591SJean-Christophe PLAGNIOL-VILLARD 632352d2591SJean-Christophe PLAGNIOL-VILLARD #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ 633352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ 634352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ 635352d2591SJean-Christophe PLAGNIOL-VILLARD #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ 636352d2591SJean-Christophe PLAGNIOL-VILLARD 637352d2591SJean-Christophe PLAGNIOL-VILLARD void *video_hw_init(void) 638352d2591SJean-Christophe PLAGNIOL-VILLARD { 639352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice *pGD = (GraphicDevice *) & ctfb; 640352d2591SJean-Christophe PLAGNIOL-VILLARD u32 *vm; 6411b8607e1SAnatolij Gustschin char *penv; 6421b8607e1SAnatolij Gustschin unsigned long t1, hsynch, vsynch; 6431b8607e1SAnatolij Gustschin int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; 6441b8607e1SAnatolij Gustschin struct ctfb_res_modes *res_mode; 6451b8607e1SAnatolij Gustschin struct ctfb_res_modes var_mode; 646352d2591SJean-Christophe PLAGNIOL-VILLARD 647352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo = malloc(sizeof(struct radeonfb_info)); 648352d2591SJean-Christophe PLAGNIOL-VILLARD 6491b8607e1SAnatolij Gustschin printf("Video: "); 650352d2591SJean-Christophe PLAGNIOL-VILLARD if(radeon_probe(rinfo)) { 651352d2591SJean-Christophe PLAGNIOL-VILLARD printf("No radeon video card found!\n"); 652352d2591SJean-Christophe PLAGNIOL-VILLARD return NULL; 653352d2591SJean-Christophe PLAGNIOL-VILLARD } 654352d2591SJean-Christophe PLAGNIOL-VILLARD 6551b8607e1SAnatolij Gustschin tmp = 0; 6561b8607e1SAnatolij Gustschin 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; 6581b8607e1SAnatolij Gustschin /* get video mode via environment */ 6591b8607e1SAnatolij Gustschin if ((penv = getenv ("videomode")) != NULL) { 6601b8607e1SAnatolij Gustschin /* deceide if it is a string */ 6611b8607e1SAnatolij Gustschin if (penv[0] <= '9') { 6621b8607e1SAnatolij Gustschin videomode = (int) simple_strtoul (penv, NULL, 16); 6631b8607e1SAnatolij Gustschin tmp = 1; 6641b8607e1SAnatolij Gustschin } 6651b8607e1SAnatolij Gustschin } else { 6661b8607e1SAnatolij Gustschin tmp = 1; 6671b8607e1SAnatolij Gustschin } 6681b8607e1SAnatolij Gustschin if (tmp) { 6691b8607e1SAnatolij Gustschin /* parameter are vesa modes */ 6701b8607e1SAnatolij Gustschin /* search params */ 6711b8607e1SAnatolij Gustschin for (i = 0; i < VESA_MODES_COUNT; i++) { 6721b8607e1SAnatolij Gustschin if (vesa_modes[i].vesanr == videomode) 6731b8607e1SAnatolij Gustschin break; 6741b8607e1SAnatolij Gustschin } 6751b8607e1SAnatolij Gustschin if (i == VESA_MODES_COUNT) { 6766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); 6771b8607e1SAnatolij Gustschin i = 0; 6781b8607e1SAnatolij Gustschin } 6791b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; 6801b8607e1SAnatolij Gustschin bits_per_pixel = vesa_modes[i].bits_per_pixel; 6811b8607e1SAnatolij Gustschin vesa_idx = vesa_modes[i].resindex; 6821b8607e1SAnatolij Gustschin } else { 6831b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &var_mode; 6841b8607e1SAnatolij Gustschin bits_per_pixel = video_get_params (res_mode, penv); 6851b8607e1SAnatolij Gustschin } 6861b8607e1SAnatolij Gustschin 6871b8607e1SAnatolij Gustschin /* calculate hsynch and vsynch freq (info only) */ 6881b8607e1SAnatolij Gustschin t1 = (res_mode->left_margin + res_mode->xres + 6891b8607e1SAnatolij Gustschin res_mode->right_margin + res_mode->hsync_len) / 8; 6901b8607e1SAnatolij Gustschin t1 *= 8; 6911b8607e1SAnatolij Gustschin t1 *= res_mode->pixclock; 6921b8607e1SAnatolij Gustschin t1 /= 1000; 6931b8607e1SAnatolij Gustschin hsynch = 1000000000L / t1; 6941b8607e1SAnatolij Gustschin t1 *= (res_mode->upper_margin + res_mode->yres + 6951b8607e1SAnatolij Gustschin res_mode->lower_margin + res_mode->vsync_len); 6961b8607e1SAnatolij Gustschin t1 /= 1000; 6971b8607e1SAnatolij Gustschin vsynch = 1000000000L / t1; 6981b8607e1SAnatolij Gustschin 699352d2591SJean-Christophe PLAGNIOL-VILLARD /* fill in Graphic device struct */ 7001b8607e1SAnatolij Gustschin sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 7011b8607e1SAnatolij Gustschin res_mode->yres, bits_per_pixel, (hsynch / 1000), 7021b8607e1SAnatolij Gustschin (vsynch / 1000)); 703352d2591SJean-Christophe PLAGNIOL-VILLARD printf ("%s\n", pGD->modeIdent); 7041b8607e1SAnatolij Gustschin pGD->winSizeX = res_mode->xres; 7051b8607e1SAnatolij Gustschin pGD->winSizeY = res_mode->yres; 7061b8607e1SAnatolij Gustschin pGD->plnSizeX = res_mode->xres; 7071b8607e1SAnatolij Gustschin pGD->plnSizeY = res_mode->yres; 708352d2591SJean-Christophe PLAGNIOL-VILLARD 7091b8607e1SAnatolij Gustschin switch (bits_per_pixel) { 7101b8607e1SAnatolij Gustschin case 24: 7111b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 4; 7121b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_32BIT_X888RGB; 7131b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 7141b8607e1SAnatolij Gustschin pGD->winSizeX = 832; 7151b8607e1SAnatolij Gustschin pGD->plnSizeX = 832; 7161b8607e1SAnatolij Gustschin } 7171b8607e1SAnatolij Gustschin break; 7181b8607e1SAnatolij Gustschin case 16: 7191b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 2; 7201b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_16BIT_565RGB; 7211b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 7221b8607e1SAnatolij Gustschin pGD->winSizeX = 896; 7231b8607e1SAnatolij Gustschin pGD->plnSizeX = 896; 7241b8607e1SAnatolij Gustschin } 7251b8607e1SAnatolij Gustschin break; 7261b8607e1SAnatolij Gustschin default: 7271b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 7281b8607e1SAnatolij Gustschin pGD->winSizeX = 1024; 7291b8607e1SAnatolij Gustschin pGD->plnSizeX = 1024; 7301b8607e1SAnatolij Gustschin } 731352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfBytesPP = 1; 732352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfIndex = GDF__8BIT_INDEX; 7331b8607e1SAnatolij Gustschin break; 7341b8607e1SAnatolij Gustschin } 735352d2591SJean-Christophe PLAGNIOL-VILLARD 7366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; 737352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->pciBase = rinfo->fb_base_phys; 738352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->frameAdrs = rinfo->fb_base_phys; 739352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->memSize = 64 * 1024 * 1024; 740352d2591SJean-Christophe PLAGNIOL-VILLARD 741352d2591SJean-Christophe PLAGNIOL-VILLARD /* Cursor Start Address */ 742352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase = 743352d2591SJean-Christophe PLAGNIOL-VILLARD (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; 744352d2591SJean-Christophe PLAGNIOL-VILLARD if ((pGD->dprBase & 0x0fff) != 0) { 745352d2591SJean-Christophe PLAGNIOL-VILLARD /* allign it */ 746352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase &= 0xfffff000; 747352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase += 0x00001000; 748352d2591SJean-Christophe PLAGNIOL-VILLARD } 749352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, 750352d2591SJean-Christophe PLAGNIOL-VILLARD PATTERN_ADR); 751352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ 752352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ 753352d2591SJean-Christophe PLAGNIOL-VILLARD /* set up Hardware */ 754352d2591SJean-Christophe PLAGNIOL-VILLARD 7551b8607e1SAnatolij Gustschin /* Clear video memory (only visible screen area) */ 7561b8607e1SAnatolij Gustschin i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; 757352d2591SJean-Christophe PLAGNIOL-VILLARD vm = (unsigned int *) pGD->pciBase; 758352d2591SJean-Christophe PLAGNIOL-VILLARD while (i--) 759352d2591SJean-Christophe PLAGNIOL-VILLARD *vm++ = 0; 760352d2591SJean-Christophe PLAGNIOL-VILLARD /*SetDrawingEngine (bits_per_pixel);*/ 761352d2591SJean-Christophe PLAGNIOL-VILLARD 7621b8607e1SAnatolij Gustschin if (rinfo->family == CHIP_FAMILY_RV280) 7631b8607e1SAnatolij Gustschin radeon_setmode_9200(vesa_idx, bits_per_pixel); 7641b8607e1SAnatolij Gustschin else 765352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_setmode(); 766352d2591SJean-Christophe PLAGNIOL-VILLARD 767352d2591SJean-Christophe PLAGNIOL-VILLARD return ((void *) pGD); 768352d2591SJean-Christophe PLAGNIOL-VILLARD } 769352d2591SJean-Christophe PLAGNIOL-VILLARD 770352d2591SJean-Christophe PLAGNIOL-VILLARD void video_set_lut (unsigned int index, /* color number */ 771352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char r, /* red */ 772352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char g, /* green */ 773352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char b /* blue */ 774352d2591SJean-Christophe PLAGNIOL-VILLARD ) 775352d2591SJean-Christophe PLAGNIOL-VILLARD { 776352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_INDEX, index); 777352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); 778352d2591SJean-Christophe PLAGNIOL-VILLARD } 779