1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2352d2591SJean-Christophe PLAGNIOL-VILLARD /* 3352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI Radeon Video card Framebuffer driver. 4352d2591SJean-Christophe PLAGNIOL-VILLARD * 5352d2591SJean-Christophe PLAGNIOL-VILLARD * Copyright 2007 Freescale Semiconductor, Inc. 6352d2591SJean-Christophe PLAGNIOL-VILLARD * Zhang Wei <wei.zhang@freescale.com> 7352d2591SJean-Christophe PLAGNIOL-VILLARD * Jason Jin <jason.jin@freescale.com> 8352d2591SJean-Christophe PLAGNIOL-VILLARD * 9352d2591SJean-Christophe PLAGNIOL-VILLARD * Some codes of this file is partly ported from Linux kernel 10352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI video framebuffer driver. 11352d2591SJean-Christophe PLAGNIOL-VILLARD * 12352d2591SJean-Christophe PLAGNIOL-VILLARD * Now the driver is tested on below ATI chips: 13352d2591SJean-Christophe PLAGNIOL-VILLARD * 9200 14352d2591SJean-Christophe PLAGNIOL-VILLARD * X300 15352d2591SJean-Christophe PLAGNIOL-VILLARD * X700 16352d2591SJean-Christophe PLAGNIOL-VILLARD */ 17352d2591SJean-Christophe PLAGNIOL-VILLARD 18352d2591SJean-Christophe PLAGNIOL-VILLARD #include <common.h> 19352d2591SJean-Christophe PLAGNIOL-VILLARD 20352d2591SJean-Christophe PLAGNIOL-VILLARD #include <command.h> 21176bf4ceSSimon Glass #include <bios_emul.h> 22352d2591SJean-Christophe PLAGNIOL-VILLARD #include <pci.h> 23352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/processor.h> 241221ce45SMasahiro Yamada #include <linux/errno.h> 25352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 26352d2591SJean-Christophe PLAGNIOL-VILLARD #include <malloc.h> 27352d2591SJean-Christophe PLAGNIOL-VILLARD #include <video_fb.h> 281b8607e1SAnatolij Gustschin #include "videomodes.h" 29352d2591SJean-Christophe PLAGNIOL-VILLARD 30352d2591SJean-Christophe PLAGNIOL-VILLARD #include <radeon.h> 31352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_ids.h" 32352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_radeon_fb.h" 33352d2591SJean-Christophe PLAGNIOL-VILLARD 34352d2591SJean-Christophe PLAGNIOL-VILLARD #undef DEBUG 35352d2591SJean-Christophe PLAGNIOL-VILLARD 36352d2591SJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG 37352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) printf(x) 38352d2591SJean-Christophe PLAGNIOL-VILLARD #else 39352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) do{}while(0) 40352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 41352d2591SJean-Christophe PLAGNIOL-VILLARD 42352d2591SJean-Christophe PLAGNIOL-VILLARD #define MAX_MAPPED_VRAM (2048*2048*4) 43352d2591SJean-Christophe PLAGNIOL-VILLARD #define MIN_MAPPED_VRAM (1024*768*1) 44352d2591SJean-Christophe PLAGNIOL-VILLARD 451b8607e1SAnatolij Gustschin #define RADEON_BUFFER_ALIGN 0x00000fff 461b8607e1SAnatolij Gustschin #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ 471b8607e1SAnatolij Gustschin & ~RADEON_BUFFER_ALIGN) - 1) 481b8607e1SAnatolij Gustschin #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ 491b8607e1SAnatolij Gustschin ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) 501b8607e1SAnatolij Gustschin 511b8607e1SAnatolij Gustschin #define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ 521b8607e1SAnatolij Gustschin (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) 531b8607e1SAnatolij Gustschin #define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ 541b8607e1SAnatolij Gustschin (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) 551b8607e1SAnatolij Gustschin #define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ 561b8607e1SAnatolij Gustschin ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) 571b8607e1SAnatolij Gustschin #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ 581b8607e1SAnatolij Gustschin ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) 591b8607e1SAnatolij Gustschin 60352d2591SJean-Christophe PLAGNIOL-VILLARD /*#define PCI_VENDOR_ID_ATI*/ 61352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5960 0x5960 62352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5961 0x5961 63352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5962 0x5962 64352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5964 0x5964 65e5c6f9f8SAnatolij Gustschin #define PCI_CHIP_RV280_5C63 0x5C63 66352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B60 0x5B60 67352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_5657 0x5657 68352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_554d 0x554d 69352d2591SJean-Christophe PLAGNIOL-VILLARD 70352d2591SJean-Christophe PLAGNIOL-VILLARD static struct pci_device_id ati_radeon_pci_ids[] = { 71352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, 72352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, 73352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, 74352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, 75e5c6f9f8SAnatolij Gustschin {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, 76352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, 77352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, 78352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, 79352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 80352d2591SJean-Christophe PLAGNIOL-VILLARD }; 81352d2591SJean-Christophe PLAGNIOL-VILLARD 82352d2591SJean-Christophe PLAGNIOL-VILLARD static u16 ati_radeon_id_family_table[][2] = { 83352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, 84352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, 85352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, 86352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, 87e5c6f9f8SAnatolij Gustschin {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, 88352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, 89352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, 90352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, 91352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 92352d2591SJean-Christophe PLAGNIOL-VILLARD }; 93352d2591SJean-Christophe PLAGNIOL-VILLARD 94352d2591SJean-Christophe PLAGNIOL-VILLARD u16 get_radeon_id_family(u16 device) 95352d2591SJean-Christophe PLAGNIOL-VILLARD { 96352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 97352d2591SJean-Christophe PLAGNIOL-VILLARD for (i=0; ati_radeon_id_family_table[0][i]; i+=2) 98352d2591SJean-Christophe PLAGNIOL-VILLARD if (ati_radeon_id_family_table[0][i] == device) 99352d2591SJean-Christophe PLAGNIOL-VILLARD return ati_radeon_id_family_table[0][i + 1]; 100352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 101352d2591SJean-Christophe PLAGNIOL-VILLARD } 102352d2591SJean-Christophe PLAGNIOL-VILLARD 103352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeonfb_info *rinfo; 104352d2591SJean-Christophe PLAGNIOL-VILLARD 105352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_identify_vram(struct radeonfb_info *rinfo) 106352d2591SJean-Christophe PLAGNIOL-VILLARD { 107352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tmp; 108352d2591SJean-Christophe PLAGNIOL-VILLARD 109352d2591SJean-Christophe PLAGNIOL-VILLARD /* framebuffer size */ 110352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 111352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200) || 112352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS300)) { 113352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tom = INREG(NB_TOM); 114352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 115352d2591SJean-Christophe PLAGNIOL-VILLARD 116352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(6); 117352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(MC_FB_LOCATION, tom); 118352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 119352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 120352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 121352d2591SJean-Christophe PLAGNIOL-VILLARD 122352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is supposed to fix the crtc2 noise problem. */ 123352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 124352d2591SJean-Christophe PLAGNIOL-VILLARD 125352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 126352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)) { 127352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is to workaround the asic bug for RMX, some versions 128352d2591SJean-Christophe PLAGNIOL-VILLARD of BIOS dosen't have this register initialized correctly. 129352d2591SJean-Christophe PLAGNIOL-VILLARD */ 130352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 131352d2591SJean-Christophe PLAGNIOL-VILLARD ~CRTC_H_CUTOFF_ACTIVE_EN); 132352d2591SJean-Christophe PLAGNIOL-VILLARD } 133352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 134352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(CONFIG_MEMSIZE); 135352d2591SJean-Christophe PLAGNIOL-VILLARD } 136352d2591SJean-Christophe PLAGNIOL-VILLARD 137352d2591SJean-Christophe PLAGNIOL-VILLARD /* mem size is bits [28:0], mask off the rest */ 138352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; 139352d2591SJean-Christophe PLAGNIOL-VILLARD 140352d2591SJean-Christophe PLAGNIOL-VILLARD /* 141352d2591SJean-Christophe PLAGNIOL-VILLARD * Hack to get around some busted production M6's 142352d2591SJean-Christophe PLAGNIOL-VILLARD * reporting no ram 143352d2591SJean-Christophe PLAGNIOL-VILLARD */ 144352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->video_ram == 0) { 145352d2591SJean-Christophe PLAGNIOL-VILLARD switch (rinfo->pdev.device) { 146352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LY: 147352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LZ: 148352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = 8192 * 1024; 149352d2591SJean-Christophe PLAGNIOL-VILLARD break; 150352d2591SJean-Christophe PLAGNIOL-VILLARD default: 151352d2591SJean-Christophe PLAGNIOL-VILLARD break; 152352d2591SJean-Christophe PLAGNIOL-VILLARD } 153352d2591SJean-Christophe PLAGNIOL-VILLARD } 154352d2591SJean-Christophe PLAGNIOL-VILLARD 155352d2591SJean-Christophe PLAGNIOL-VILLARD /* 156352d2591SJean-Christophe PLAGNIOL-VILLARD * Now try to identify VRAM type 157352d2591SJean-Christophe PLAGNIOL-VILLARD */ 158352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family >= CHIP_FAMILY_R300) || 159352d2591SJean-Christophe PLAGNIOL-VILLARD (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 160352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 1; 161352d2591SJean-Christophe PLAGNIOL-VILLARD else 162352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 0; 163352d2591SJean-Christophe PLAGNIOL-VILLARD 164352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(MEM_CNTL); 165352d2591SJean-Christophe PLAGNIOL-VILLARD if (IS_R300_VARIANT(rinfo)) { 166352d2591SJean-Christophe PLAGNIOL-VILLARD tmp &= R300_MEM_NUM_CHANNELS_MASK; 167352d2591SJean-Christophe PLAGNIOL-VILLARD switch (tmp) { 168352d2591SJean-Christophe PLAGNIOL-VILLARD case 0: rinfo->vram_width = 64; break; 169352d2591SJean-Christophe PLAGNIOL-VILLARD case 1: rinfo->vram_width = 128; break; 170352d2591SJean-Christophe PLAGNIOL-VILLARD case 2: rinfo->vram_width = 256; break; 171352d2591SJean-Christophe PLAGNIOL-VILLARD default: rinfo->vram_width = 128; break; 172352d2591SJean-Christophe PLAGNIOL-VILLARD } 173352d2591SJean-Christophe PLAGNIOL-VILLARD } else if ((rinfo->family == CHIP_FAMILY_RV100) || 174352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS100) || 175352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)){ 176352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & RV100_MEM_HALF_MODE) 177352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 32; 178352d2591SJean-Christophe PLAGNIOL-VILLARD else 179352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 180352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 181352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & MEM_NUM_CHANNELS_MASK) 182352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 128; 183352d2591SJean-Christophe PLAGNIOL-VILLARD else 184352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 185352d2591SJean-Christophe PLAGNIOL-VILLARD } 186352d2591SJean-Christophe PLAGNIOL-VILLARD 187352d2591SJean-Christophe PLAGNIOL-VILLARD /* This may not be correct, as some cards can have half of channel disabled 188352d2591SJean-Christophe PLAGNIOL-VILLARD * ToDo: identify these cases 189352d2591SJean-Christophe PLAGNIOL-VILLARD */ 190352d2591SJean-Christophe PLAGNIOL-VILLARD 191f6a7a2e8SEd Swarthout DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", 192352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram / 1024, 193352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr ? "DDR" : "SDRAM", 194352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width); 195352d2591SJean-Christophe PLAGNIOL-VILLARD 196352d2591SJean-Christophe PLAGNIOL-VILLARD } 197352d2591SJean-Christophe PLAGNIOL-VILLARD 198352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 199352d2591SJean-Christophe PLAGNIOL-VILLARD { 200352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 201352d2591SJean-Christophe PLAGNIOL-VILLARD 202352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(20); 203352d2591SJean-Christophe PLAGNIOL-VILLARD 204352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 205352d2591SJean-Christophe PLAGNIOL-VILLARD /* Workaround from XFree */ 206352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->is_mobility) { 207352d2591SJean-Christophe PLAGNIOL-VILLARD /* A temporal workaround for the occational blanking on certain laptop 208352d2591SJean-Christophe PLAGNIOL-VILLARD * panels. This appears to related to the PLL divider registers 209352d2591SJean-Christophe PLAGNIOL-VILLARD * (fail to lock?). It occurs even when all dividers are the same 210352d2591SJean-Christophe PLAGNIOL-VILLARD * with their old settings. In this case we really don't need to 211352d2591SJean-Christophe PLAGNIOL-VILLARD * fiddle with PLL registers. By doing this we can avoid the blanking 212352d2591SJean-Christophe PLAGNIOL-VILLARD * problem with some panels. 213352d2591SJean-Christophe PLAGNIOL-VILLARD */ 214352d2591SJean-Christophe PLAGNIOL-VILLARD if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 215352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 216352d2591SJean-Christophe PLAGNIOL-VILLARD (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 217352d2591SJean-Christophe PLAGNIOL-VILLARD /* We still have to force a switch to selected PPLL div thanks to 218352d2591SJean-Christophe PLAGNIOL-VILLARD * an XFree86 driver bug which will switch it away in some cases 219352d2591SJean-Christophe PLAGNIOL-VILLARD * even when using UseFDev */ 220352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 221352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 222352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 223352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_index(rinfo); 224352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_data(rinfo); 225352d2591SJean-Christophe PLAGNIOL-VILLARD return; 226352d2591SJean-Christophe PLAGNIOL-VILLARD } 227352d2591SJean-Christophe PLAGNIOL-VILLARD } 228352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 229352d2591SJean-Christophe PLAGNIOL-VILLARD if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; 230352d2591SJean-Christophe PLAGNIOL-VILLARD 231352d2591SJean-Christophe PLAGNIOL-VILLARD /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 232352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 233352d2591SJean-Christophe PLAGNIOL-VILLARD 234352d2591SJean-Christophe PLAGNIOL-VILLARD /* Reset PPLL & enable atomic update */ 235352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 236352d2591SJean-Christophe PLAGNIOL-VILLARD PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 237352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 238352d2591SJean-Christophe PLAGNIOL-VILLARD 239352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch to selected PPLL divider */ 240352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 241352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 242352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 243352d2591SJean-Christophe PLAGNIOL-VILLARD 244352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL ref. div */ 245352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->family == CHIP_FAMILY_R300 || 246352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RS300 || 247352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_R350 || 248352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RV350) { 249352d2591SJean-Christophe PLAGNIOL-VILLARD if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 250352d2591SJean-Christophe PLAGNIOL-VILLARD /* When restoring console mode, use saved PPLL_REF_DIV 251352d2591SJean-Christophe PLAGNIOL-VILLARD * setting. 252352d2591SJean-Christophe PLAGNIOL-VILLARD */ 253352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 254352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 255352d2591SJean-Christophe PLAGNIOL-VILLARD /* R300 uses ref_div_acc field as real ref divider */ 256352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, 257352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 258352d2591SJean-Christophe PLAGNIOL-VILLARD ~R300_PPLL_REF_DIV_ACC_MASK); 259352d2591SJean-Christophe PLAGNIOL-VILLARD } 260352d2591SJean-Christophe PLAGNIOL-VILLARD } else 261352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 262352d2591SJean-Christophe PLAGNIOL-VILLARD 263352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL divider 3 & post divider*/ 264352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 265352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 266352d2591SJean-Christophe PLAGNIOL-VILLARD 267352d2591SJean-Christophe PLAGNIOL-VILLARD /* Write update */ 268352d2591SJean-Christophe PLAGNIOL-VILLARD while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 269352d2591SJean-Christophe PLAGNIOL-VILLARD ; 270352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 271352d2591SJean-Christophe PLAGNIOL-VILLARD 272352d2591SJean-Christophe PLAGNIOL-VILLARD /* Wait read update complete */ 273352d2591SJean-Christophe PLAGNIOL-VILLARD /* FIXME: Certain revisions of R300 can't recover here. Not sure of 274352d2591SJean-Christophe PLAGNIOL-VILLARD the cause yet, but this workaround will mask the problem for now. 275352d2591SJean-Christophe PLAGNIOL-VILLARD Other chips usually will pass at the very first test, so the 276352d2591SJean-Christophe PLAGNIOL-VILLARD workaround shouldn't have any effect on them. */ 277352d2591SJean-Christophe PLAGNIOL-VILLARD for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 278352d2591SJean-Christophe PLAGNIOL-VILLARD ; 279352d2591SJean-Christophe PLAGNIOL-VILLARD 280352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLL(HTOTAL_CNTL, 0); 281352d2591SJean-Christophe PLAGNIOL-VILLARD 282352d2591SJean-Christophe PLAGNIOL-VILLARD /* Clear reset & atomic update */ 283352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 0, 284352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 285352d2591SJean-Christophe PLAGNIOL-VILLARD 286352d2591SJean-Christophe PLAGNIOL-VILLARD /* We may want some locking ... oh well */ 287352d2591SJean-Christophe PLAGNIOL-VILLARD udelay(5000); 288352d2591SJean-Christophe PLAGNIOL-VILLARD 289352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch back VCLK source to PPLL */ 290352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 291352d2591SJean-Christophe PLAGNIOL-VILLARD } 292352d2591SJean-Christophe PLAGNIOL-VILLARD 293352d2591SJean-Christophe PLAGNIOL-VILLARD typedef struct { 294352d2591SJean-Christophe PLAGNIOL-VILLARD u16 reg; 295352d2591SJean-Christophe PLAGNIOL-VILLARD u32 val; 296352d2591SJean-Christophe PLAGNIOL-VILLARD } reg_val; 297352d2591SJean-Christophe PLAGNIOL-VILLARD 298352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 /* unused ? -> scheduled for removal */ 299352d2591SJean-Christophe PLAGNIOL-VILLARD /* these common regs are cleared before mode setting so they do not 300352d2591SJean-Christophe PLAGNIOL-VILLARD * interfere with anything 301352d2591SJean-Christophe PLAGNIOL-VILLARD */ 302352d2591SJean-Christophe PLAGNIOL-VILLARD static reg_val common_regs[] = { 303352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_CLR, 0 }, 304352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_LEFT_RIGHT, 0 }, 305352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_TOP_BOTTOM, 0 }, 306352d2591SJean-Christophe PLAGNIOL-VILLARD { OV0_SCALE_CNTL, 0 }, 307352d2591SJean-Christophe PLAGNIOL-VILLARD { SUBPIC_CNTL, 0 }, 308352d2591SJean-Christophe PLAGNIOL-VILLARD { VIPH_CONTROL, 0 }, 309352d2591SJean-Christophe PLAGNIOL-VILLARD { I2C_CNTL_1, 0 }, 310352d2591SJean-Christophe PLAGNIOL-VILLARD { GEN_INT_CNTL, 0 }, 311352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP0_TRIG_CNTL, 0 }, 312352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP1_TRIG_CNTL, 0 }, 313352d2591SJean-Christophe PLAGNIOL-VILLARD }; 314352d2591SJean-Christophe PLAGNIOL-VILLARD #endif /* 0 */ 315352d2591SJean-Christophe PLAGNIOL-VILLARD 316352d2591SJean-Christophe PLAGNIOL-VILLARD void radeon_setmode(void) 317352d2591SJean-Christophe PLAGNIOL-VILLARD { 318352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 319352d2591SJean-Christophe PLAGNIOL-VILLARD 320352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_gen_cntl = 0x03000200; 321352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_ext_cntl = 0x00008048; 322352d2591SJean-Christophe PLAGNIOL-VILLARD mode->dac_cntl = 0xff002100; 323352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_total_disp = 0x4f0063; 324352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_sync_strt_wid = 0x8c02a2; 325352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_total_disp = 0x01df020c; 326352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_sync_strt_wid = 0x8201ea; 327352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_pitch = 0x00500050; 328352d2591SJean-Christophe PLAGNIOL-VILLARD 329352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 330352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 331352d2591SJean-Christophe PLAGNIOL-VILLARD ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 332352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 333352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 334352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 335352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 336352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 337352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET, 0); 338352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET_CNTL, 0); 339352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_PITCH, mode->crtc_pitch); 340352d2591SJean-Christophe PLAGNIOL-VILLARD 341352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index = 0x300; 342352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_ref_div = 0xc; 343352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_div_3 = 0x00030059; 344352d2591SJean-Christophe PLAGNIOL-VILLARD 345352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_write_pll_regs(rinfo, mode); 346352d2591SJean-Christophe PLAGNIOL-VILLARD } 347352d2591SJean-Christophe PLAGNIOL-VILLARD 3481b8607e1SAnatolij Gustschin static void set_pal(void) 3491b8607e1SAnatolij Gustschin { 3501b8607e1SAnatolij Gustschin int idx, val = 0; 3511b8607e1SAnatolij Gustschin 3521b8607e1SAnatolij Gustschin for (idx = 0; idx < 256; idx++) { 3531b8607e1SAnatolij Gustschin OUTREG8(PALETTE_INDEX, idx); 3541b8607e1SAnatolij Gustschin OUTREG(PALETTE_DATA, val); 3551b8607e1SAnatolij Gustschin val += 0x00010101; 3561b8607e1SAnatolij Gustschin } 3571b8607e1SAnatolij Gustschin } 3581b8607e1SAnatolij Gustschin 3591b8607e1SAnatolij Gustschin void radeon_setmode_9200(int vesa_idx, int bpp) 3601b8607e1SAnatolij Gustschin { 3611b8607e1SAnatolij Gustschin struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 3621b8607e1SAnatolij Gustschin 3631b8607e1SAnatolij Gustschin mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; 3641b8607e1SAnatolij Gustschin mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; 3651b8607e1SAnatolij Gustschin mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; 3661b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; 3671b8607e1SAnatolij Gustschin 3681b8607e1SAnatolij Gustschin switch (bpp) { 3691b8607e1SAnatolij Gustschin case 24: 3701b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ 3711b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 3721b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 3731b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 3741b8607e1SAnatolij Gustschin #endif 3751b8607e1SAnatolij Gustschin break; 3761b8607e1SAnatolij Gustschin case 16: 3771b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ 3781b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 3791b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 3801b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 3811b8607e1SAnatolij Gustschin #endif 3821b8607e1SAnatolij Gustschin break; 3831b8607e1SAnatolij Gustschin default: 3841b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ 3851b8607e1SAnatolij Gustschin mode->surface_cntl = 0x00000000; 3861b8607e1SAnatolij Gustschin break; 3871b8607e1SAnatolij Gustschin } 3881b8607e1SAnatolij Gustschin 3891b8607e1SAnatolij Gustschin switch (vesa_idx) { 3901b8607e1SAnatolij Gustschin case RES_MODE_1280x1024: 3911b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); 3921b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); 3931b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); 3941b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 3951b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); 3961b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010078; 3971b8607e1SAnatolij Gustschin #else /* default @ 60 Hz */ 3981b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); 3991b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010060; 4001b8607e1SAnatolij Gustschin #endif 4011b8607e1SAnatolij Gustschin /* 4021b8607e1SAnatolij Gustschin * for this mode pitch expands to the same value for 32, 16 and 8 bpp, 4031b8607e1SAnatolij Gustschin * so we set it here once only. 4041b8607e1SAnatolij Gustschin */ 4051b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); 4061b8607e1SAnatolij Gustschin switch (bpp) { 4071b8607e1SAnatolij Gustschin case 24: 4081b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); 4091b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); 4101b8607e1SAnatolij Gustschin break; 4111b8607e1SAnatolij Gustschin case 16: 4121b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); 4131b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); 4141b8607e1SAnatolij Gustschin break; 4151b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4161b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); 4171b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); 4181b8607e1SAnatolij Gustschin break; 4191b8607e1SAnatolij Gustschin } 4201b8607e1SAnatolij Gustschin break; 4211b8607e1SAnatolij Gustschin case RES_MODE_1024x768: 4221b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4231b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); 4241b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); 4251b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); 4261b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); 4271b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0002008c; 4281b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 4291b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); 4301b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; 4311b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); 4321b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; 4331b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00020074; 4341b8607e1SAnatolij Gustschin #endif 4351b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 4361b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); 4371b8607e1SAnatolij Gustschin switch (bpp) { 4381b8607e1SAnatolij Gustschin case 24: 4391b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); 4401b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); 4411b8607e1SAnatolij Gustschin break; 4421b8607e1SAnatolij Gustschin case 16: 4431b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); 4441b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); 4451b8607e1SAnatolij Gustschin break; 4461b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4471b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 4481b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); 4491b8607e1SAnatolij Gustschin break; 4501b8607e1SAnatolij Gustschin } 4511b8607e1SAnatolij Gustschin break; 4521b8607e1SAnatolij Gustschin case RES_MODE_800x600: 4531b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); 4541b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4551b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); 4561b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); 4571b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); 4581b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x000300b0; 4591b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 4601b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); 4611b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); 4621b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); 4631b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0003008e; 4641b8607e1SAnatolij Gustschin #endif 4651b8607e1SAnatolij Gustschin switch (bpp) { 4661b8607e1SAnatolij Gustschin case 24: 4671b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(832,32); 4681b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); 4691b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); 4701b8607e1SAnatolij Gustschin break; 4711b8607e1SAnatolij Gustschin case 16: 4721b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(896,16); 4731b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); 4741b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); 4751b8607e1SAnatolij Gustschin break; 4761b8607e1SAnatolij Gustschin default: /* 8 bpp */ 4771b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); 4781b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 4791b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); 4801b8607e1SAnatolij Gustschin break; 4811b8607e1SAnatolij Gustschin } 4821b8607e1SAnatolij Gustschin break; 4831b8607e1SAnatolij Gustschin default: /* RES_MODE_640x480 */ 4841b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 4851b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); 4861b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; 4871b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); 4881b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; 4891b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030070; 4901b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 4911b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); 4921b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; 4931b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); 4941b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; 4951b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030059; 4961b8607e1SAnatolij Gustschin #endif 4971b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 4981b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(640,32); 4991b8607e1SAnatolij Gustschin switch (bpp) { 5001b8607e1SAnatolij Gustschin case 24: 5011b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); 5021b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); 5031b8607e1SAnatolij Gustschin break; 5041b8607e1SAnatolij Gustschin case 16: 5051b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); 5061b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); 5071b8607e1SAnatolij Gustschin break; 5081b8607e1SAnatolij Gustschin default: /* 8 bpp */ 5091b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = 0x00000000; 5101b8607e1SAnatolij Gustschin break; 5111b8607e1SAnatolij Gustschin } 5121b8607e1SAnatolij Gustschin break; 5131b8607e1SAnatolij Gustschin } 5141b8607e1SAnatolij Gustschin 5151b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 5161b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 5171b8607e1SAnatolij Gustschin (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 5181b8607e1SAnatolij Gustschin OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 5191b8607e1SAnatolij Gustschin OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 5201b8607e1SAnatolij Gustschin OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 5211b8607e1SAnatolij Gustschin OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 5221b8607e1SAnatolij Gustschin OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 5231b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET, 0); 5241b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); 5251b8607e1SAnatolij Gustschin OUTREG(CRTC_PITCH, mode->crtc_pitch); 5261b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 5271b8607e1SAnatolij Gustschin 5281b8607e1SAnatolij Gustschin mode->clk_cntl_index = 0x300; 5291b8607e1SAnatolij Gustschin mode->ppll_ref_div = 0xc; 5301b8607e1SAnatolij Gustschin 5311b8607e1SAnatolij Gustschin radeon_write_pll_regs(rinfo, mode); 5321b8607e1SAnatolij Gustschin 5331b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 5341b8607e1SAnatolij Gustschin ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 5351b8607e1SAnatolij Gustschin OUTREG(SURFACE0_INFO, mode->surf_info[0]); 5361b8607e1SAnatolij Gustschin OUTREG(SURFACE0_LOWER_BOUND, 0); 5371b8607e1SAnatolij Gustschin OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); 5381b8607e1SAnatolij Gustschin OUTREG(SURFACE_CNTL, mode->surface_cntl); 5391b8607e1SAnatolij Gustschin 5401b8607e1SAnatolij Gustschin if (bpp > 8) 5411b8607e1SAnatolij Gustschin set_pal(); 5421b8607e1SAnatolij Gustschin 5431b8607e1SAnatolij Gustschin free(mode); 5441b8607e1SAnatolij Gustschin } 5451b8607e1SAnatolij Gustschin 546352d2591SJean-Christophe PLAGNIOL-VILLARD #include "../bios_emulator/include/biosemu.h" 547352d2591SJean-Christophe PLAGNIOL-VILLARD 548352d2591SJean-Christophe PLAGNIOL-VILLARD int radeon_probe(struct radeonfb_info *rinfo) 549352d2591SJean-Christophe PLAGNIOL-VILLARD { 550352d2591SJean-Christophe PLAGNIOL-VILLARD pci_dev_t pdev; 551352d2591SJean-Christophe PLAGNIOL-VILLARD u16 did; 552352d2591SJean-Christophe PLAGNIOL-VILLARD 553352d2591SJean-Christophe PLAGNIOL-VILLARD pdev = pci_find_devices(ati_radeon_pci_ids, 0); 554352d2591SJean-Christophe PLAGNIOL-VILLARD 555352d2591SJean-Christophe PLAGNIOL-VILLARD if (pdev != -1) { 556352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 557352d2591SJean-Christophe PLAGNIOL-VILLARD printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", 558352d2591SJean-Christophe PLAGNIOL-VILLARD PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, 559352d2591SJean-Christophe PLAGNIOL-VILLARD (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 560352d2591SJean-Christophe PLAGNIOL-VILLARD 561352d2591SJean-Christophe PLAGNIOL-VILLARD strcpy(rinfo->name, "ATI Radeon"); 562352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; 563352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.device = did; 564352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family = get_radeon_id_family(rinfo->pdev.device); 565352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, 566f6a7a2e8SEd Swarthout &rinfo->fb_base_bus); 567352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, 568f6a7a2e8SEd Swarthout &rinfo->mmio_base_bus); 569f6a7a2e8SEd Swarthout rinfo->fb_base_bus &= 0xfffff000; 570f6a7a2e8SEd Swarthout rinfo->mmio_base_bus &= ~0x04; 571352d2591SJean-Christophe PLAGNIOL-VILLARD 572f6a7a2e8SEd Swarthout rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, 573f6a7a2e8SEd Swarthout PCI_REGION_MEM, 0, MAP_NOCACHE); 574760bce07SAnatolij Gustschin DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", 575f6a7a2e8SEd Swarthout rinfo->mmio_base, rinfo->mmio_base_bus); 576352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 577352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); 578352d2591SJean-Christophe PLAGNIOL-VILLARD /* PostBIOS with x86 emulater */ 5799624f6d9SEd Swarthout if (!BootVideoCardBIOS(pdev, NULL, 0)) 5809624f6d9SEd Swarthout return -1; 581352d2591SJean-Christophe PLAGNIOL-VILLARD 582352d2591SJean-Christophe PLAGNIOL-VILLARD /* 583352d2591SJean-Christophe PLAGNIOL-VILLARD * Check for errata 584352d2591SJean-Christophe PLAGNIOL-VILLARD * (These will be added in the future for the chipfamily 585352d2591SJean-Christophe PLAGNIOL-VILLARD * R300, RV200, RS200, RV100, RS100.) 586352d2591SJean-Christophe PLAGNIOL-VILLARD */ 587352d2591SJean-Christophe PLAGNIOL-VILLARD 588352d2591SJean-Christophe PLAGNIOL-VILLARD /* Get VRAM size and type */ 589352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_identify_vram(rinfo); 590352d2591SJean-Christophe PLAGNIOL-VILLARD 591352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, 592352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram); 593f6a7a2e8SEd Swarthout rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, 594f6a7a2e8SEd Swarthout PCI_REGION_MEM, 0, MAP_NOCACHE); 595f6a7a2e8SEd Swarthout DPRINT("Radeon: framebuffer base address 0x%08x, " 596f6a7a2e8SEd Swarthout "bus address 0x%08x\n" 597f6a7a2e8SEd Swarthout "MMIO base address 0x%08x, bus address 0x%08x, " 598352d2591SJean-Christophe PLAGNIOL-VILLARD "framebuffer local base 0x%08x.\n ", 599f6a7a2e8SEd Swarthout (u32)rinfo->fb_base, rinfo->fb_base_bus, 600f6a7a2e8SEd Swarthout (u32)rinfo->mmio_base, rinfo->mmio_base_bus, 601352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base); 602352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 603352d2591SJean-Christophe PLAGNIOL-VILLARD } 604352d2591SJean-Christophe PLAGNIOL-VILLARD return -1; 605352d2591SJean-Christophe PLAGNIOL-VILLARD } 606352d2591SJean-Christophe PLAGNIOL-VILLARD 607352d2591SJean-Christophe PLAGNIOL-VILLARD /* 608352d2591SJean-Christophe PLAGNIOL-VILLARD * The Graphic Device 609352d2591SJean-Christophe PLAGNIOL-VILLARD */ 610352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice ctfb; 611352d2591SJean-Christophe PLAGNIOL-VILLARD 612352d2591SJean-Christophe PLAGNIOL-VILLARD #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ 613352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ 614352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ 615352d2591SJean-Christophe PLAGNIOL-VILLARD #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ 616352d2591SJean-Christophe PLAGNIOL-VILLARD 617352d2591SJean-Christophe PLAGNIOL-VILLARD void *video_hw_init(void) 618352d2591SJean-Christophe PLAGNIOL-VILLARD { 619352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice *pGD = (GraphicDevice *) & ctfb; 620352d2591SJean-Christophe PLAGNIOL-VILLARD u32 *vm; 6211b8607e1SAnatolij Gustschin char *penv; 6221b8607e1SAnatolij Gustschin unsigned long t1, hsynch, vsynch; 6231b8607e1SAnatolij Gustschin int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; 6241b8607e1SAnatolij Gustschin struct ctfb_res_modes *res_mode; 6251b8607e1SAnatolij Gustschin struct ctfb_res_modes var_mode; 626352d2591SJean-Christophe PLAGNIOL-VILLARD 627352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo = malloc(sizeof(struct radeonfb_info)); 628352d2591SJean-Christophe PLAGNIOL-VILLARD 6291b8607e1SAnatolij Gustschin printf("Video: "); 630352d2591SJean-Christophe PLAGNIOL-VILLARD if(radeon_probe(rinfo)) { 631352d2591SJean-Christophe PLAGNIOL-VILLARD printf("No radeon video card found!\n"); 632352d2591SJean-Christophe PLAGNIOL-VILLARD return NULL; 633352d2591SJean-Christophe PLAGNIOL-VILLARD } 634352d2591SJean-Christophe PLAGNIOL-VILLARD 6351b8607e1SAnatolij Gustschin tmp = 0; 6361b8607e1SAnatolij Gustschin 6376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; 6381b8607e1SAnatolij Gustschin /* get video mode via environment */ 63900caae6dSSimon Glass penv = env_get("videomode"); 64000caae6dSSimon Glass if (penv) { 6411b8607e1SAnatolij Gustschin /* deceide if it is a string */ 6421b8607e1SAnatolij Gustschin if (penv[0] <= '9') { 6431b8607e1SAnatolij Gustschin videomode = (int) simple_strtoul (penv, NULL, 16); 6441b8607e1SAnatolij Gustschin tmp = 1; 6451b8607e1SAnatolij Gustschin } 6461b8607e1SAnatolij Gustschin } else { 6471b8607e1SAnatolij Gustschin tmp = 1; 6481b8607e1SAnatolij Gustschin } 6491b8607e1SAnatolij Gustschin if (tmp) { 6501b8607e1SAnatolij Gustschin /* parameter are vesa modes */ 6511b8607e1SAnatolij Gustschin /* search params */ 6521b8607e1SAnatolij Gustschin for (i = 0; i < VESA_MODES_COUNT; i++) { 6531b8607e1SAnatolij Gustschin if (vesa_modes[i].vesanr == videomode) 6541b8607e1SAnatolij Gustschin break; 6551b8607e1SAnatolij Gustschin } 6561b8607e1SAnatolij Gustschin if (i == VESA_MODES_COUNT) { 6576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); 6581b8607e1SAnatolij Gustschin i = 0; 6591b8607e1SAnatolij Gustschin } 6601b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; 6611b8607e1SAnatolij Gustschin bits_per_pixel = vesa_modes[i].bits_per_pixel; 6621b8607e1SAnatolij Gustschin vesa_idx = vesa_modes[i].resindex; 6631b8607e1SAnatolij Gustschin } else { 6641b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &var_mode; 6651b8607e1SAnatolij Gustschin bits_per_pixel = video_get_params (res_mode, penv); 6661b8607e1SAnatolij Gustschin } 6671b8607e1SAnatolij Gustschin 6681b8607e1SAnatolij Gustschin /* calculate hsynch and vsynch freq (info only) */ 6691b8607e1SAnatolij Gustschin t1 = (res_mode->left_margin + res_mode->xres + 6701b8607e1SAnatolij Gustschin res_mode->right_margin + res_mode->hsync_len) / 8; 6711b8607e1SAnatolij Gustschin t1 *= 8; 6721b8607e1SAnatolij Gustschin t1 *= res_mode->pixclock; 6731b8607e1SAnatolij Gustschin t1 /= 1000; 6741b8607e1SAnatolij Gustschin hsynch = 1000000000L / t1; 6751b8607e1SAnatolij Gustschin t1 *= (res_mode->upper_margin + res_mode->yres + 6761b8607e1SAnatolij Gustschin res_mode->lower_margin + res_mode->vsync_len); 6771b8607e1SAnatolij Gustschin t1 /= 1000; 6781b8607e1SAnatolij Gustschin vsynch = 1000000000L / t1; 6791b8607e1SAnatolij Gustschin 680352d2591SJean-Christophe PLAGNIOL-VILLARD /* fill in Graphic device struct */ 6811b8607e1SAnatolij Gustschin sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 6821b8607e1SAnatolij Gustschin res_mode->yres, bits_per_pixel, (hsynch / 1000), 6831b8607e1SAnatolij Gustschin (vsynch / 1000)); 684352d2591SJean-Christophe PLAGNIOL-VILLARD printf ("%s\n", pGD->modeIdent); 6851b8607e1SAnatolij Gustschin pGD->winSizeX = res_mode->xres; 6861b8607e1SAnatolij Gustschin pGD->winSizeY = res_mode->yres; 6871b8607e1SAnatolij Gustschin pGD->plnSizeX = res_mode->xres; 6881b8607e1SAnatolij Gustschin pGD->plnSizeY = res_mode->yres; 689352d2591SJean-Christophe PLAGNIOL-VILLARD 6901b8607e1SAnatolij Gustschin switch (bits_per_pixel) { 6911b8607e1SAnatolij Gustschin case 24: 6921b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 4; 6931b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_32BIT_X888RGB; 6941b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 6951b8607e1SAnatolij Gustschin pGD->winSizeX = 832; 6961b8607e1SAnatolij Gustschin pGD->plnSizeX = 832; 6971b8607e1SAnatolij Gustschin } 6981b8607e1SAnatolij Gustschin break; 6991b8607e1SAnatolij Gustschin case 16: 7001b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 2; 7011b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_16BIT_565RGB; 7021b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 7031b8607e1SAnatolij Gustschin pGD->winSizeX = 896; 7041b8607e1SAnatolij Gustschin pGD->plnSizeX = 896; 7051b8607e1SAnatolij Gustschin } 7061b8607e1SAnatolij Gustschin break; 7071b8607e1SAnatolij Gustschin default: 7081b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 7091b8607e1SAnatolij Gustschin pGD->winSizeX = 1024; 7101b8607e1SAnatolij Gustschin pGD->plnSizeX = 1024; 7111b8607e1SAnatolij Gustschin } 712352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfBytesPP = 1; 713352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfIndex = GDF__8BIT_INDEX; 7141b8607e1SAnatolij Gustschin break; 7151b8607e1SAnatolij Gustschin } 716352d2591SJean-Christophe PLAGNIOL-VILLARD 7176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; 718f6a7a2e8SEd Swarthout pGD->pciBase = (unsigned int)rinfo->fb_base; 719f6a7a2e8SEd Swarthout pGD->frameAdrs = (unsigned int)rinfo->fb_base; 720352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->memSize = 64 * 1024 * 1024; 721352d2591SJean-Christophe PLAGNIOL-VILLARD 722352d2591SJean-Christophe PLAGNIOL-VILLARD /* Cursor Start Address */ 723f6a7a2e8SEd Swarthout pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + 724f6a7a2e8SEd Swarthout (unsigned int)rinfo->fb_base; 725352d2591SJean-Christophe PLAGNIOL-VILLARD if ((pGD->dprBase & 0x0fff) != 0) { 726352d2591SJean-Christophe PLAGNIOL-VILLARD /* allign it */ 727352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase &= 0xfffff000; 728352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase += 0x00001000; 729352d2591SJean-Christophe PLAGNIOL-VILLARD } 730352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, 731352d2591SJean-Christophe PLAGNIOL-VILLARD PATTERN_ADR); 732f6a7a2e8SEd Swarthout pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ 733f6a7a2e8SEd Swarthout pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ 734352d2591SJean-Christophe PLAGNIOL-VILLARD /* set up Hardware */ 735352d2591SJean-Christophe PLAGNIOL-VILLARD 7361b8607e1SAnatolij Gustschin /* Clear video memory (only visible screen area) */ 7371b8607e1SAnatolij Gustschin i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; 738352d2591SJean-Christophe PLAGNIOL-VILLARD vm = (unsigned int *) pGD->pciBase; 739352d2591SJean-Christophe PLAGNIOL-VILLARD while (i--) 740352d2591SJean-Christophe PLAGNIOL-VILLARD *vm++ = 0; 741352d2591SJean-Christophe PLAGNIOL-VILLARD /*SetDrawingEngine (bits_per_pixel);*/ 742352d2591SJean-Christophe PLAGNIOL-VILLARD 7431b8607e1SAnatolij Gustschin if (rinfo->family == CHIP_FAMILY_RV280) 7441b8607e1SAnatolij Gustschin radeon_setmode_9200(vesa_idx, bits_per_pixel); 7451b8607e1SAnatolij Gustschin else 746352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_setmode(); 747352d2591SJean-Christophe PLAGNIOL-VILLARD 748352d2591SJean-Christophe PLAGNIOL-VILLARD return ((void *) pGD); 749352d2591SJean-Christophe PLAGNIOL-VILLARD } 750352d2591SJean-Christophe PLAGNIOL-VILLARD 751352d2591SJean-Christophe PLAGNIOL-VILLARD void video_set_lut (unsigned int index, /* color number */ 752352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char r, /* red */ 753352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char g, /* green */ 754352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char b /* blue */ 755352d2591SJean-Christophe PLAGNIOL-VILLARD ) 756352d2591SJean-Christophe PLAGNIOL-VILLARD { 757352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_INDEX, index); 758352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); 759352d2591SJean-Christophe PLAGNIOL-VILLARD } 760