1352d2591SJean-Christophe PLAGNIOL-VILLARD /* 2352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI Radeon Video card Framebuffer driver. 3352d2591SJean-Christophe PLAGNIOL-VILLARD * 4352d2591SJean-Christophe PLAGNIOL-VILLARD * Copyright 2007 Freescale Semiconductor, Inc. 5352d2591SJean-Christophe PLAGNIOL-VILLARD * Zhang Wei <wei.zhang@freescale.com> 6352d2591SJean-Christophe PLAGNIOL-VILLARD * Jason Jin <jason.jin@freescale.com> 7352d2591SJean-Christophe PLAGNIOL-VILLARD * 8352d2591SJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 9352d2591SJean-Christophe PLAGNIOL-VILLARD * project. 10352d2591SJean-Christophe PLAGNIOL-VILLARD * 11352d2591SJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 12352d2591SJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 13352d2591SJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 14352d2591SJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 15352d2591SJean-Christophe PLAGNIOL-VILLARD * 16352d2591SJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 17352d2591SJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 18352d2591SJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19352d2591SJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 20352d2591SJean-Christophe PLAGNIOL-VILLARD * 21352d2591SJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 22352d2591SJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 23352d2591SJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24352d2591SJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 25352d2591SJean-Christophe PLAGNIOL-VILLARD * 26352d2591SJean-Christophe PLAGNIOL-VILLARD * Some codes of this file is partly ported from Linux kernel 27352d2591SJean-Christophe PLAGNIOL-VILLARD * ATI video framebuffer driver. 28352d2591SJean-Christophe PLAGNIOL-VILLARD * 29352d2591SJean-Christophe PLAGNIOL-VILLARD * Now the driver is tested on below ATI chips: 30352d2591SJean-Christophe PLAGNIOL-VILLARD * 9200 31352d2591SJean-Christophe PLAGNIOL-VILLARD * X300 32352d2591SJean-Christophe PLAGNIOL-VILLARD * X700 33352d2591SJean-Christophe PLAGNIOL-VILLARD * 34352d2591SJean-Christophe PLAGNIOL-VILLARD */ 35352d2591SJean-Christophe PLAGNIOL-VILLARD 36352d2591SJean-Christophe PLAGNIOL-VILLARD #include <common.h> 37352d2591SJean-Christophe PLAGNIOL-VILLARD 38352d2591SJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ATI_RADEON_FB 39352d2591SJean-Christophe PLAGNIOL-VILLARD 40352d2591SJean-Christophe PLAGNIOL-VILLARD #include <command.h> 41352d2591SJean-Christophe PLAGNIOL-VILLARD #include <pci.h> 42352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/processor.h> 43352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/errno.h> 44352d2591SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 45352d2591SJean-Christophe PLAGNIOL-VILLARD #include <malloc.h> 46352d2591SJean-Christophe PLAGNIOL-VILLARD #include <video_fb.h> 47*1b8607e1SAnatolij Gustschin #include "videomodes.h" 48352d2591SJean-Christophe PLAGNIOL-VILLARD 49352d2591SJean-Christophe PLAGNIOL-VILLARD #include <radeon.h> 50352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_ids.h" 51352d2591SJean-Christophe PLAGNIOL-VILLARD #include "ati_radeon_fb.h" 52352d2591SJean-Christophe PLAGNIOL-VILLARD 53352d2591SJean-Christophe PLAGNIOL-VILLARD #undef DEBUG 54352d2591SJean-Christophe PLAGNIOL-VILLARD 55352d2591SJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG 56352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) printf(x) 57352d2591SJean-Christophe PLAGNIOL-VILLARD #else 58352d2591SJean-Christophe PLAGNIOL-VILLARD #define DPRINT(x...) do{}while(0) 59352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 60352d2591SJean-Christophe PLAGNIOL-VILLARD 61352d2591SJean-Christophe PLAGNIOL-VILLARD #ifndef min_t 62352d2591SJean-Christophe PLAGNIOL-VILLARD #define min_t(type,x,y) \ 63352d2591SJean-Christophe PLAGNIOL-VILLARD ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 64352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 65352d2591SJean-Christophe PLAGNIOL-VILLARD 66352d2591SJean-Christophe PLAGNIOL-VILLARD #define MAX_MAPPED_VRAM (2048*2048*4) 67352d2591SJean-Christophe PLAGNIOL-VILLARD #define MIN_MAPPED_VRAM (1024*768*1) 68352d2591SJean-Christophe PLAGNIOL-VILLARD 69*1b8607e1SAnatolij Gustschin #define RADEON_BUFFER_ALIGN 0x00000fff 70*1b8607e1SAnatolij Gustschin #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ 71*1b8607e1SAnatolij Gustschin & ~RADEON_BUFFER_ALIGN) - 1) 72*1b8607e1SAnatolij Gustschin #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ 73*1b8607e1SAnatolij Gustschin ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) 74*1b8607e1SAnatolij Gustschin 75*1b8607e1SAnatolij Gustschin #define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ 76*1b8607e1SAnatolij Gustschin (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) 77*1b8607e1SAnatolij Gustschin #define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ 78*1b8607e1SAnatolij Gustschin (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) 79*1b8607e1SAnatolij Gustschin #define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ 80*1b8607e1SAnatolij Gustschin ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) 81*1b8607e1SAnatolij Gustschin #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ 82*1b8607e1SAnatolij Gustschin ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) 83*1b8607e1SAnatolij Gustschin 84352d2591SJean-Christophe PLAGNIOL-VILLARD /*#define PCI_VENDOR_ID_ATI*/ 85352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5960 0x5960 86352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5961 0x5961 87352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5962 0x5962 88352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV280_5964 0x5964 89352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV370_5B60 0x5B60 90352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_RV380_5657 0x5657 91352d2591SJean-Christophe PLAGNIOL-VILLARD #define PCI_CHIP_R420_554d 0x554d 92352d2591SJean-Christophe PLAGNIOL-VILLARD 93352d2591SJean-Christophe PLAGNIOL-VILLARD static struct pci_device_id ati_radeon_pci_ids[] = { 94352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, 95352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, 96352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, 97352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, 98352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, 99352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, 100352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, 101352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 102352d2591SJean-Christophe PLAGNIOL-VILLARD }; 103352d2591SJean-Christophe PLAGNIOL-VILLARD 104352d2591SJean-Christophe PLAGNIOL-VILLARD static u16 ati_radeon_id_family_table[][2] = { 105352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, 106352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, 107352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, 108352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, 109352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, 110352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, 111352d2591SJean-Christophe PLAGNIOL-VILLARD {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, 112352d2591SJean-Christophe PLAGNIOL-VILLARD {0, 0} 113352d2591SJean-Christophe PLAGNIOL-VILLARD }; 114352d2591SJean-Christophe PLAGNIOL-VILLARD 115352d2591SJean-Christophe PLAGNIOL-VILLARD u16 get_radeon_id_family(u16 device) 116352d2591SJean-Christophe PLAGNIOL-VILLARD { 117352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 118352d2591SJean-Christophe PLAGNIOL-VILLARD for (i=0; ati_radeon_id_family_table[0][i]; i+=2) 119352d2591SJean-Christophe PLAGNIOL-VILLARD if (ati_radeon_id_family_table[0][i] == device) 120352d2591SJean-Christophe PLAGNIOL-VILLARD return ati_radeon_id_family_table[0][i + 1]; 121352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 122352d2591SJean-Christophe PLAGNIOL-VILLARD } 123352d2591SJean-Christophe PLAGNIOL-VILLARD 124352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeonfb_info *rinfo; 125352d2591SJean-Christophe PLAGNIOL-VILLARD 126352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_identify_vram(struct radeonfb_info *rinfo) 127352d2591SJean-Christophe PLAGNIOL-VILLARD { 128352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tmp; 129352d2591SJean-Christophe PLAGNIOL-VILLARD 130352d2591SJean-Christophe PLAGNIOL-VILLARD /* framebuffer size */ 131352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 132352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200) || 133352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS300)) { 134352d2591SJean-Christophe PLAGNIOL-VILLARD u32 tom = INREG(NB_TOM); 135352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 136352d2591SJean-Christophe PLAGNIOL-VILLARD 137352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(6); 138352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(MC_FB_LOCATION, tom); 139352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 140352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 141352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 142352d2591SJean-Christophe PLAGNIOL-VILLARD 143352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is supposed to fix the crtc2 noise problem. */ 144352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 145352d2591SJean-Christophe PLAGNIOL-VILLARD 146352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family == CHIP_FAMILY_RS100) || 147352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)) { 148352d2591SJean-Christophe PLAGNIOL-VILLARD /* This is to workaround the asic bug for RMX, some versions 149352d2591SJean-Christophe PLAGNIOL-VILLARD of BIOS dosen't have this register initialized correctly. 150352d2591SJean-Christophe PLAGNIOL-VILLARD */ 151352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 152352d2591SJean-Christophe PLAGNIOL-VILLARD ~CRTC_H_CUTOFF_ACTIVE_EN); 153352d2591SJean-Christophe PLAGNIOL-VILLARD } 154352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 155352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(CONFIG_MEMSIZE); 156352d2591SJean-Christophe PLAGNIOL-VILLARD } 157352d2591SJean-Christophe PLAGNIOL-VILLARD 158352d2591SJean-Christophe PLAGNIOL-VILLARD /* mem size is bits [28:0], mask off the rest */ 159352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; 160352d2591SJean-Christophe PLAGNIOL-VILLARD 161352d2591SJean-Christophe PLAGNIOL-VILLARD /* 162352d2591SJean-Christophe PLAGNIOL-VILLARD * Hack to get around some busted production M6's 163352d2591SJean-Christophe PLAGNIOL-VILLARD * reporting no ram 164352d2591SJean-Christophe PLAGNIOL-VILLARD */ 165352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->video_ram == 0) { 166352d2591SJean-Christophe PLAGNIOL-VILLARD switch (rinfo->pdev.device) { 167352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LY: 168352d2591SJean-Christophe PLAGNIOL-VILLARD case PCI_CHIP_RADEON_LZ: 169352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram = 8192 * 1024; 170352d2591SJean-Christophe PLAGNIOL-VILLARD break; 171352d2591SJean-Christophe PLAGNIOL-VILLARD default: 172352d2591SJean-Christophe PLAGNIOL-VILLARD break; 173352d2591SJean-Christophe PLAGNIOL-VILLARD } 174352d2591SJean-Christophe PLAGNIOL-VILLARD } 175352d2591SJean-Christophe PLAGNIOL-VILLARD 176352d2591SJean-Christophe PLAGNIOL-VILLARD /* 177352d2591SJean-Christophe PLAGNIOL-VILLARD * Now try to identify VRAM type 178352d2591SJean-Christophe PLAGNIOL-VILLARD */ 179352d2591SJean-Christophe PLAGNIOL-VILLARD if ((rinfo->family >= CHIP_FAMILY_R300) || 180352d2591SJean-Christophe PLAGNIOL-VILLARD (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 181352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 1; 182352d2591SJean-Christophe PLAGNIOL-VILLARD else 183352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr = 0; 184352d2591SJean-Christophe PLAGNIOL-VILLARD 185352d2591SJean-Christophe PLAGNIOL-VILLARD tmp = INREG(MEM_CNTL); 186352d2591SJean-Christophe PLAGNIOL-VILLARD if (IS_R300_VARIANT(rinfo)) { 187352d2591SJean-Christophe PLAGNIOL-VILLARD tmp &= R300_MEM_NUM_CHANNELS_MASK; 188352d2591SJean-Christophe PLAGNIOL-VILLARD switch (tmp) { 189352d2591SJean-Christophe PLAGNIOL-VILLARD case 0: rinfo->vram_width = 64; break; 190352d2591SJean-Christophe PLAGNIOL-VILLARD case 1: rinfo->vram_width = 128; break; 191352d2591SJean-Christophe PLAGNIOL-VILLARD case 2: rinfo->vram_width = 256; break; 192352d2591SJean-Christophe PLAGNIOL-VILLARD default: rinfo->vram_width = 128; break; 193352d2591SJean-Christophe PLAGNIOL-VILLARD } 194352d2591SJean-Christophe PLAGNIOL-VILLARD } else if ((rinfo->family == CHIP_FAMILY_RV100) || 195352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS100) || 196352d2591SJean-Christophe PLAGNIOL-VILLARD (rinfo->family == CHIP_FAMILY_RS200)){ 197352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & RV100_MEM_HALF_MODE) 198352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 32; 199352d2591SJean-Christophe PLAGNIOL-VILLARD else 200352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 201352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 202352d2591SJean-Christophe PLAGNIOL-VILLARD if (tmp & MEM_NUM_CHANNELS_MASK) 203352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 128; 204352d2591SJean-Christophe PLAGNIOL-VILLARD else 205352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width = 64; 206352d2591SJean-Christophe PLAGNIOL-VILLARD } 207352d2591SJean-Christophe PLAGNIOL-VILLARD 208352d2591SJean-Christophe PLAGNIOL-VILLARD /* This may not be correct, as some cards can have half of channel disabled 209352d2591SJean-Christophe PLAGNIOL-VILLARD * ToDo: identify these cases 210352d2591SJean-Christophe PLAGNIOL-VILLARD */ 211352d2591SJean-Christophe PLAGNIOL-VILLARD 212352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", 213352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram / 1024, 214352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_ddr ? "DDR" : "SDRAM", 215352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->vram_width); 216352d2591SJean-Christophe PLAGNIOL-VILLARD 217352d2591SJean-Christophe PLAGNIOL-VILLARD } 218352d2591SJean-Christophe PLAGNIOL-VILLARD 219352d2591SJean-Christophe PLAGNIOL-VILLARD static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 220352d2591SJean-Christophe PLAGNIOL-VILLARD { 221352d2591SJean-Christophe PLAGNIOL-VILLARD int i; 222352d2591SJean-Christophe PLAGNIOL-VILLARD 223352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_fifo_wait(20); 224352d2591SJean-Christophe PLAGNIOL-VILLARD 225352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 226352d2591SJean-Christophe PLAGNIOL-VILLARD /* Workaround from XFree */ 227352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->is_mobility) { 228352d2591SJean-Christophe PLAGNIOL-VILLARD /* A temporal workaround for the occational blanking on certain laptop 229352d2591SJean-Christophe PLAGNIOL-VILLARD * panels. This appears to related to the PLL divider registers 230352d2591SJean-Christophe PLAGNIOL-VILLARD * (fail to lock?). It occurs even when all dividers are the same 231352d2591SJean-Christophe PLAGNIOL-VILLARD * with their old settings. In this case we really don't need to 232352d2591SJean-Christophe PLAGNIOL-VILLARD * fiddle with PLL registers. By doing this we can avoid the blanking 233352d2591SJean-Christophe PLAGNIOL-VILLARD * problem with some panels. 234352d2591SJean-Christophe PLAGNIOL-VILLARD */ 235352d2591SJean-Christophe PLAGNIOL-VILLARD if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 236352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 237352d2591SJean-Christophe PLAGNIOL-VILLARD (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 238352d2591SJean-Christophe PLAGNIOL-VILLARD /* We still have to force a switch to selected PPLL div thanks to 239352d2591SJean-Christophe PLAGNIOL-VILLARD * an XFree86 driver bug which will switch it away in some cases 240352d2591SJean-Christophe PLAGNIOL-VILLARD * even when using UseFDev */ 241352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 242352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 243352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 244352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_index(rinfo); 245352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_pll_errata_after_data(rinfo); 246352d2591SJean-Christophe PLAGNIOL-VILLARD return; 247352d2591SJean-Christophe PLAGNIOL-VILLARD } 248352d2591SJean-Christophe PLAGNIOL-VILLARD } 249352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 250352d2591SJean-Christophe PLAGNIOL-VILLARD if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; 251352d2591SJean-Christophe PLAGNIOL-VILLARD 252352d2591SJean-Christophe PLAGNIOL-VILLARD /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 253352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 254352d2591SJean-Christophe PLAGNIOL-VILLARD 255352d2591SJean-Christophe PLAGNIOL-VILLARD /* Reset PPLL & enable atomic update */ 256352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 257352d2591SJean-Christophe PLAGNIOL-VILLARD PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 258352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 259352d2591SJean-Christophe PLAGNIOL-VILLARD 260352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch to selected PPLL divider */ 261352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CLOCK_CNTL_INDEX, 262352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 263352d2591SJean-Christophe PLAGNIOL-VILLARD ~PPLL_DIV_SEL_MASK); 264352d2591SJean-Christophe PLAGNIOL-VILLARD 265352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL ref. div */ 266352d2591SJean-Christophe PLAGNIOL-VILLARD if (rinfo->family == CHIP_FAMILY_R300 || 267352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RS300 || 268352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_R350 || 269352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family == CHIP_FAMILY_RV350) { 270352d2591SJean-Christophe PLAGNIOL-VILLARD if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 271352d2591SJean-Christophe PLAGNIOL-VILLARD /* When restoring console mode, use saved PPLL_REF_DIV 272352d2591SJean-Christophe PLAGNIOL-VILLARD * setting. 273352d2591SJean-Christophe PLAGNIOL-VILLARD */ 274352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 275352d2591SJean-Christophe PLAGNIOL-VILLARD } else { 276352d2591SJean-Christophe PLAGNIOL-VILLARD /* R300 uses ref_div_acc field as real ref divider */ 277352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, 278352d2591SJean-Christophe PLAGNIOL-VILLARD (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 279352d2591SJean-Christophe PLAGNIOL-VILLARD ~R300_PPLL_REF_DIV_ACC_MASK); 280352d2591SJean-Christophe PLAGNIOL-VILLARD } 281352d2591SJean-Christophe PLAGNIOL-VILLARD } else 282352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 283352d2591SJean-Christophe PLAGNIOL-VILLARD 284352d2591SJean-Christophe PLAGNIOL-VILLARD /* Set PPLL divider 3 & post divider*/ 285352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 286352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 287352d2591SJean-Christophe PLAGNIOL-VILLARD 288352d2591SJean-Christophe PLAGNIOL-VILLARD /* Write update */ 289352d2591SJean-Christophe PLAGNIOL-VILLARD while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 290352d2591SJean-Christophe PLAGNIOL-VILLARD ; 291352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 292352d2591SJean-Christophe PLAGNIOL-VILLARD 293352d2591SJean-Christophe PLAGNIOL-VILLARD /* Wait read update complete */ 294352d2591SJean-Christophe PLAGNIOL-VILLARD /* FIXME: Certain revisions of R300 can't recover here. Not sure of 295352d2591SJean-Christophe PLAGNIOL-VILLARD the cause yet, but this workaround will mask the problem for now. 296352d2591SJean-Christophe PLAGNIOL-VILLARD Other chips usually will pass at the very first test, so the 297352d2591SJean-Christophe PLAGNIOL-VILLARD workaround shouldn't have any effect on them. */ 298352d2591SJean-Christophe PLAGNIOL-VILLARD for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 299352d2591SJean-Christophe PLAGNIOL-VILLARD ; 300352d2591SJean-Christophe PLAGNIOL-VILLARD 301352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLL(HTOTAL_CNTL, 0); 302352d2591SJean-Christophe PLAGNIOL-VILLARD 303352d2591SJean-Christophe PLAGNIOL-VILLARD /* Clear reset & atomic update */ 304352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(PPLL_CNTL, 0, 305352d2591SJean-Christophe PLAGNIOL-VILLARD ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 306352d2591SJean-Christophe PLAGNIOL-VILLARD 307352d2591SJean-Christophe PLAGNIOL-VILLARD /* We may want some locking ... oh well */ 308352d2591SJean-Christophe PLAGNIOL-VILLARD udelay(5000); 309352d2591SJean-Christophe PLAGNIOL-VILLARD 310352d2591SJean-Christophe PLAGNIOL-VILLARD /* Switch back VCLK source to PPLL */ 311352d2591SJean-Christophe PLAGNIOL-VILLARD OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 312352d2591SJean-Christophe PLAGNIOL-VILLARD } 313352d2591SJean-Christophe PLAGNIOL-VILLARD 314352d2591SJean-Christophe PLAGNIOL-VILLARD typedef struct { 315352d2591SJean-Christophe PLAGNIOL-VILLARD u16 reg; 316352d2591SJean-Christophe PLAGNIOL-VILLARD u32 val; 317352d2591SJean-Christophe PLAGNIOL-VILLARD } reg_val; 318352d2591SJean-Christophe PLAGNIOL-VILLARD 319352d2591SJean-Christophe PLAGNIOL-VILLARD #if 0 /* unused ? -> scheduled for removal */ 320352d2591SJean-Christophe PLAGNIOL-VILLARD /* these common regs are cleared before mode setting so they do not 321352d2591SJean-Christophe PLAGNIOL-VILLARD * interfere with anything 322352d2591SJean-Christophe PLAGNIOL-VILLARD */ 323352d2591SJean-Christophe PLAGNIOL-VILLARD static reg_val common_regs[] = { 324352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_CLR, 0 }, 325352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_LEFT_RIGHT, 0 }, 326352d2591SJean-Christophe PLAGNIOL-VILLARD { OVR_WID_TOP_BOTTOM, 0 }, 327352d2591SJean-Christophe PLAGNIOL-VILLARD { OV0_SCALE_CNTL, 0 }, 328352d2591SJean-Christophe PLAGNIOL-VILLARD { SUBPIC_CNTL, 0 }, 329352d2591SJean-Christophe PLAGNIOL-VILLARD { VIPH_CONTROL, 0 }, 330352d2591SJean-Christophe PLAGNIOL-VILLARD { I2C_CNTL_1, 0 }, 331352d2591SJean-Christophe PLAGNIOL-VILLARD { GEN_INT_CNTL, 0 }, 332352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP0_TRIG_CNTL, 0 }, 333352d2591SJean-Christophe PLAGNIOL-VILLARD { CAP1_TRIG_CNTL, 0 }, 334352d2591SJean-Christophe PLAGNIOL-VILLARD }; 335352d2591SJean-Christophe PLAGNIOL-VILLARD #endif /* 0 */ 336352d2591SJean-Christophe PLAGNIOL-VILLARD 337352d2591SJean-Christophe PLAGNIOL-VILLARD void radeon_setmode(void) 338352d2591SJean-Christophe PLAGNIOL-VILLARD { 339352d2591SJean-Christophe PLAGNIOL-VILLARD struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 340352d2591SJean-Christophe PLAGNIOL-VILLARD 341352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_gen_cntl = 0x03000200; 342352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_ext_cntl = 0x00008048; 343352d2591SJean-Christophe PLAGNIOL-VILLARD mode->dac_cntl = 0xff002100; 344352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_total_disp = 0x4f0063; 345352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_h_sync_strt_wid = 0x8c02a2; 346352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_total_disp = 0x01df020c; 347352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_v_sync_strt_wid = 0x8201ea; 348352d2591SJean-Christophe PLAGNIOL-VILLARD mode->crtc_pitch = 0x00500050; 349352d2591SJean-Christophe PLAGNIOL-VILLARD 350352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 351352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 352352d2591SJean-Christophe PLAGNIOL-VILLARD ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 353352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 354352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 355352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 356352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 357352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 358352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET, 0); 359352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_OFFSET_CNTL, 0); 360352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(CRTC_PITCH, mode->crtc_pitch); 361352d2591SJean-Christophe PLAGNIOL-VILLARD 362352d2591SJean-Christophe PLAGNIOL-VILLARD mode->clk_cntl_index = 0x300; 363352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_ref_div = 0xc; 364352d2591SJean-Christophe PLAGNIOL-VILLARD mode->ppll_div_3 = 0x00030059; 365352d2591SJean-Christophe PLAGNIOL-VILLARD 366352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_write_pll_regs(rinfo, mode); 367352d2591SJean-Christophe PLAGNIOL-VILLARD } 368352d2591SJean-Christophe PLAGNIOL-VILLARD 369*1b8607e1SAnatolij Gustschin static void set_pal(void) 370*1b8607e1SAnatolij Gustschin { 371*1b8607e1SAnatolij Gustschin int idx, val = 0; 372*1b8607e1SAnatolij Gustschin 373*1b8607e1SAnatolij Gustschin for (idx = 0; idx < 256; idx++) { 374*1b8607e1SAnatolij Gustschin OUTREG8(PALETTE_INDEX, idx); 375*1b8607e1SAnatolij Gustschin OUTREG(PALETTE_DATA, val); 376*1b8607e1SAnatolij Gustschin val += 0x00010101; 377*1b8607e1SAnatolij Gustschin } 378*1b8607e1SAnatolij Gustschin } 379*1b8607e1SAnatolij Gustschin 380*1b8607e1SAnatolij Gustschin void radeon_setmode_9200(int vesa_idx, int bpp) 381*1b8607e1SAnatolij Gustschin { 382*1b8607e1SAnatolij Gustschin struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 383*1b8607e1SAnatolij Gustschin 384*1b8607e1SAnatolij Gustschin mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; 385*1b8607e1SAnatolij Gustschin mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; 386*1b8607e1SAnatolij Gustschin mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; 387*1b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; 388*1b8607e1SAnatolij Gustschin 389*1b8607e1SAnatolij Gustschin switch (bpp) { 390*1b8607e1SAnatolij Gustschin case 24: 391*1b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ 392*1b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 393*1b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 394*1b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; 395*1b8607e1SAnatolij Gustschin #endif 396*1b8607e1SAnatolij Gustschin break; 397*1b8607e1SAnatolij Gustschin case 16: 398*1b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ 399*1b8607e1SAnatolij Gustschin #if defined(__BIG_ENDIAN) 400*1b8607e1SAnatolij Gustschin mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 401*1b8607e1SAnatolij Gustschin mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; 402*1b8607e1SAnatolij Gustschin #endif 403*1b8607e1SAnatolij Gustschin break; 404*1b8607e1SAnatolij Gustschin default: 405*1b8607e1SAnatolij Gustschin mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ 406*1b8607e1SAnatolij Gustschin mode->surface_cntl = 0x00000000; 407*1b8607e1SAnatolij Gustschin break; 408*1b8607e1SAnatolij Gustschin } 409*1b8607e1SAnatolij Gustschin 410*1b8607e1SAnatolij Gustschin switch (vesa_idx) { 411*1b8607e1SAnatolij Gustschin case RES_MODE_1280x1024: 412*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); 413*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); 414*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); 415*1b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 416*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); 417*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010078; 418*1b8607e1SAnatolij Gustschin #else /* default @ 60 Hz */ 419*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); 420*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00010060; 421*1b8607e1SAnatolij Gustschin #endif 422*1b8607e1SAnatolij Gustschin /* 423*1b8607e1SAnatolij Gustschin * for this mode pitch expands to the same value for 32, 16 and 8 bpp, 424*1b8607e1SAnatolij Gustschin * so we set it here once only. 425*1b8607e1SAnatolij Gustschin */ 426*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); 427*1b8607e1SAnatolij Gustschin switch (bpp) { 428*1b8607e1SAnatolij Gustschin case 24: 429*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); 430*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); 431*1b8607e1SAnatolij Gustschin break; 432*1b8607e1SAnatolij Gustschin case 16: 433*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); 434*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); 435*1b8607e1SAnatolij Gustschin break; 436*1b8607e1SAnatolij Gustschin default: /* 8 bpp */ 437*1b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); 438*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); 439*1b8607e1SAnatolij Gustschin break; 440*1b8607e1SAnatolij Gustschin } 441*1b8607e1SAnatolij Gustschin break; 442*1b8607e1SAnatolij Gustschin case RES_MODE_1024x768: 443*1b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 444*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); 445*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); 446*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); 447*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); 448*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0002008c; 449*1b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 450*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); 451*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; 452*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); 453*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; 454*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00020074; 455*1b8607e1SAnatolij Gustschin #endif 456*1b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 457*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); 458*1b8607e1SAnatolij Gustschin switch (bpp) { 459*1b8607e1SAnatolij Gustschin case 24: 460*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); 461*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); 462*1b8607e1SAnatolij Gustschin break; 463*1b8607e1SAnatolij Gustschin case 16: 464*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); 465*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); 466*1b8607e1SAnatolij Gustschin break; 467*1b8607e1SAnatolij Gustschin default: /* 8 bpp */ 468*1b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 469*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); 470*1b8607e1SAnatolij Gustschin break; 471*1b8607e1SAnatolij Gustschin } 472*1b8607e1SAnatolij Gustschin break; 473*1b8607e1SAnatolij Gustschin case RES_MODE_800x600: 474*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); 475*1b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 476*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); 477*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); 478*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); 479*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x000300b0; 480*1b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 481*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); 482*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); 483*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); 484*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x0003008e; 485*1b8607e1SAnatolij Gustschin #endif 486*1b8607e1SAnatolij Gustschin switch (bpp) { 487*1b8607e1SAnatolij Gustschin case 24: 488*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(832,32); 489*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); 490*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); 491*1b8607e1SAnatolij Gustschin break; 492*1b8607e1SAnatolij Gustschin case 16: 493*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(896,16); 494*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); 495*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); 496*1b8607e1SAnatolij Gustschin break; 497*1b8607e1SAnatolij Gustschin default: /* 8 bpp */ 498*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); 499*1b8607e1SAnatolij Gustschin mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); 500*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); 501*1b8607e1SAnatolij Gustschin break; 502*1b8607e1SAnatolij Gustschin } 503*1b8607e1SAnatolij Gustschin break; 504*1b8607e1SAnatolij Gustschin default: /* RES_MODE_640x480 */ 505*1b8607e1SAnatolij Gustschin #if defined(CONFIG_RADEON_VREFRESH_75HZ) 506*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); 507*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; 508*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); 509*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; 510*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030070; 511*1b8607e1SAnatolij Gustschin #else /* @ 60 Hz */ 512*1b8607e1SAnatolij Gustschin mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); 513*1b8607e1SAnatolij Gustschin mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; 514*1b8607e1SAnatolij Gustschin mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); 515*1b8607e1SAnatolij Gustschin mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; 516*1b8607e1SAnatolij Gustschin mode->ppll_div_3 = 0x00030059; 517*1b8607e1SAnatolij Gustschin #endif 518*1b8607e1SAnatolij Gustschin /* also same pitch value for 32, 16 and 8 bpp */ 519*1b8607e1SAnatolij Gustschin mode->crtc_pitch = RADEON_CRT_PITCH(640,32); 520*1b8607e1SAnatolij Gustschin switch (bpp) { 521*1b8607e1SAnatolij Gustschin case 24: 522*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); 523*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); 524*1b8607e1SAnatolij Gustschin break; 525*1b8607e1SAnatolij Gustschin case 16: 526*1b8607e1SAnatolij Gustschin mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); 527*1b8607e1SAnatolij Gustschin mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); 528*1b8607e1SAnatolij Gustschin break; 529*1b8607e1SAnatolij Gustschin default: /* 8 bpp */ 530*1b8607e1SAnatolij Gustschin mode->crtc_offset_cntl = 0x00000000; 531*1b8607e1SAnatolij Gustschin break; 532*1b8607e1SAnatolij Gustschin } 533*1b8607e1SAnatolij Gustschin break; 534*1b8607e1SAnatolij Gustschin } 535*1b8607e1SAnatolij Gustschin 536*1b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 537*1b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 538*1b8607e1SAnatolij Gustschin (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 539*1b8607e1SAnatolij Gustschin OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 540*1b8607e1SAnatolij Gustschin OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 541*1b8607e1SAnatolij Gustschin OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 542*1b8607e1SAnatolij Gustschin OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 543*1b8607e1SAnatolij Gustschin OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 544*1b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET, 0); 545*1b8607e1SAnatolij Gustschin OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); 546*1b8607e1SAnatolij Gustschin OUTREG(CRTC_PITCH, mode->crtc_pitch); 547*1b8607e1SAnatolij Gustschin OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 548*1b8607e1SAnatolij Gustschin 549*1b8607e1SAnatolij Gustschin mode->clk_cntl_index = 0x300; 550*1b8607e1SAnatolij Gustschin mode->ppll_ref_div = 0xc; 551*1b8607e1SAnatolij Gustschin 552*1b8607e1SAnatolij Gustschin radeon_write_pll_regs(rinfo, mode); 553*1b8607e1SAnatolij Gustschin 554*1b8607e1SAnatolij Gustschin OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 555*1b8607e1SAnatolij Gustschin ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 556*1b8607e1SAnatolij Gustschin OUTREG(SURFACE0_INFO, mode->surf_info[0]); 557*1b8607e1SAnatolij Gustschin OUTREG(SURFACE0_LOWER_BOUND, 0); 558*1b8607e1SAnatolij Gustschin OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); 559*1b8607e1SAnatolij Gustschin OUTREG(SURFACE_CNTL, mode->surface_cntl); 560*1b8607e1SAnatolij Gustschin 561*1b8607e1SAnatolij Gustschin if (bpp > 8) 562*1b8607e1SAnatolij Gustschin set_pal(); 563*1b8607e1SAnatolij Gustschin 564*1b8607e1SAnatolij Gustschin free(mode); 565*1b8607e1SAnatolij Gustschin } 566*1b8607e1SAnatolij Gustschin 567352d2591SJean-Christophe PLAGNIOL-VILLARD #include "../bios_emulator/include/biosemu.h" 568352d2591SJean-Christophe PLAGNIOL-VILLARD extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); 569352d2591SJean-Christophe PLAGNIOL-VILLARD 570352d2591SJean-Christophe PLAGNIOL-VILLARD int radeon_probe(struct radeonfb_info *rinfo) 571352d2591SJean-Christophe PLAGNIOL-VILLARD { 572352d2591SJean-Christophe PLAGNIOL-VILLARD pci_dev_t pdev; 573352d2591SJean-Christophe PLAGNIOL-VILLARD u16 did; 574352d2591SJean-Christophe PLAGNIOL-VILLARD 575352d2591SJean-Christophe PLAGNIOL-VILLARD pdev = pci_find_devices(ati_radeon_pci_ids, 0); 576352d2591SJean-Christophe PLAGNIOL-VILLARD 577352d2591SJean-Christophe PLAGNIOL-VILLARD if (pdev != -1) { 578352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 579352d2591SJean-Christophe PLAGNIOL-VILLARD printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", 580352d2591SJean-Christophe PLAGNIOL-VILLARD PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, 581352d2591SJean-Christophe PLAGNIOL-VILLARD (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 582352d2591SJean-Christophe PLAGNIOL-VILLARD 583352d2591SJean-Christophe PLAGNIOL-VILLARD strcpy(rinfo->name, "ATI Radeon"); 584352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; 585352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->pdev.device = did; 586352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->family = get_radeon_id_family(rinfo->pdev.device); 587352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, 588352d2591SJean-Christophe PLAGNIOL-VILLARD &rinfo->fb_base_phys); 589352d2591SJean-Christophe PLAGNIOL-VILLARD pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, 590352d2591SJean-Christophe PLAGNIOL-VILLARD &rinfo->mmio_base_phys); 591352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base_phys &= 0xfffff000; 592352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mmio_base_phys &= ~0x04; 593352d2591SJean-Christophe PLAGNIOL-VILLARD 594352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mmio_base = (void *)rinfo->mmio_base_phys; 595352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); 596352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 597352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); 598352d2591SJean-Christophe PLAGNIOL-VILLARD /* PostBIOS with x86 emulater */ 599352d2591SJean-Christophe PLAGNIOL-VILLARD BootVideoCardBIOS(pdev, NULL, 0); 600352d2591SJean-Christophe PLAGNIOL-VILLARD 601352d2591SJean-Christophe PLAGNIOL-VILLARD /* 602352d2591SJean-Christophe PLAGNIOL-VILLARD * Check for errata 603352d2591SJean-Christophe PLAGNIOL-VILLARD * (These will be added in the future for the chipfamily 604352d2591SJean-Christophe PLAGNIOL-VILLARD * R300, RV200, RS200, RV100, RS100.) 605352d2591SJean-Christophe PLAGNIOL-VILLARD */ 606352d2591SJean-Christophe PLAGNIOL-VILLARD 607352d2591SJean-Christophe PLAGNIOL-VILLARD /* Get VRAM size and type */ 608352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_identify_vram(rinfo); 609352d2591SJean-Christophe PLAGNIOL-VILLARD 610352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, 611352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->video_ram); 612352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base = (void *)rinfo->fb_base_phys; 613352d2591SJean-Christophe PLAGNIOL-VILLARD 614352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT("Radeon: framebuffer base phy address 0x%08x," \ 615352d2591SJean-Christophe PLAGNIOL-VILLARD "MMIO base phy address 0x%08x," \ 616352d2591SJean-Christophe PLAGNIOL-VILLARD "framebuffer local base 0x%08x.\n ", 617352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_base_phys, rinfo->mmio_base_phys, 618352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo->fb_local_base); 619352d2591SJean-Christophe PLAGNIOL-VILLARD 620352d2591SJean-Christophe PLAGNIOL-VILLARD return 0; 621352d2591SJean-Christophe PLAGNIOL-VILLARD } 622352d2591SJean-Christophe PLAGNIOL-VILLARD return -1; 623352d2591SJean-Christophe PLAGNIOL-VILLARD } 624352d2591SJean-Christophe PLAGNIOL-VILLARD 625352d2591SJean-Christophe PLAGNIOL-VILLARD /* 626352d2591SJean-Christophe PLAGNIOL-VILLARD * The Graphic Device 627352d2591SJean-Christophe PLAGNIOL-VILLARD */ 628352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice ctfb; 629352d2591SJean-Christophe PLAGNIOL-VILLARD 630352d2591SJean-Christophe PLAGNIOL-VILLARD #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ 631352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ 632352d2591SJean-Christophe PLAGNIOL-VILLARD #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ 633352d2591SJean-Christophe PLAGNIOL-VILLARD #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ 634352d2591SJean-Christophe PLAGNIOL-VILLARD 635352d2591SJean-Christophe PLAGNIOL-VILLARD void *video_hw_init(void) 636352d2591SJean-Christophe PLAGNIOL-VILLARD { 637352d2591SJean-Christophe PLAGNIOL-VILLARD GraphicDevice *pGD = (GraphicDevice *) & ctfb; 638352d2591SJean-Christophe PLAGNIOL-VILLARD u32 *vm; 639*1b8607e1SAnatolij Gustschin char *penv; 640*1b8607e1SAnatolij Gustschin unsigned long t1, hsynch, vsynch; 641*1b8607e1SAnatolij Gustschin int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; 642*1b8607e1SAnatolij Gustschin struct ctfb_res_modes *res_mode; 643*1b8607e1SAnatolij Gustschin struct ctfb_res_modes var_mode; 644352d2591SJean-Christophe PLAGNIOL-VILLARD 645352d2591SJean-Christophe PLAGNIOL-VILLARD rinfo = malloc(sizeof(struct radeonfb_info)); 646352d2591SJean-Christophe PLAGNIOL-VILLARD 647*1b8607e1SAnatolij Gustschin printf("Video: "); 648352d2591SJean-Christophe PLAGNIOL-VILLARD if(radeon_probe(rinfo)) { 649352d2591SJean-Christophe PLAGNIOL-VILLARD printf("No radeon video card found!\n"); 650352d2591SJean-Christophe PLAGNIOL-VILLARD return NULL; 651352d2591SJean-Christophe PLAGNIOL-VILLARD } 652352d2591SJean-Christophe PLAGNIOL-VILLARD 653*1b8607e1SAnatolij Gustschin tmp = 0; 654*1b8607e1SAnatolij Gustschin 655*1b8607e1SAnatolij Gustschin videomode = CFG_DEFAULT_VIDEO_MODE; 656*1b8607e1SAnatolij Gustschin /* get video mode via environment */ 657*1b8607e1SAnatolij Gustschin if ((penv = getenv ("videomode")) != NULL) { 658*1b8607e1SAnatolij Gustschin /* deceide if it is a string */ 659*1b8607e1SAnatolij Gustschin if (penv[0] <= '9') { 660*1b8607e1SAnatolij Gustschin videomode = (int) simple_strtoul (penv, NULL, 16); 661*1b8607e1SAnatolij Gustschin tmp = 1; 662*1b8607e1SAnatolij Gustschin } 663*1b8607e1SAnatolij Gustschin } else { 664*1b8607e1SAnatolij Gustschin tmp = 1; 665*1b8607e1SAnatolij Gustschin } 666*1b8607e1SAnatolij Gustschin if (tmp) { 667*1b8607e1SAnatolij Gustschin /* parameter are vesa modes */ 668*1b8607e1SAnatolij Gustschin /* search params */ 669*1b8607e1SAnatolij Gustschin for (i = 0; i < VESA_MODES_COUNT; i++) { 670*1b8607e1SAnatolij Gustschin if (vesa_modes[i].vesanr == videomode) 671*1b8607e1SAnatolij Gustschin break; 672*1b8607e1SAnatolij Gustschin } 673*1b8607e1SAnatolij Gustschin if (i == VESA_MODES_COUNT) { 674*1b8607e1SAnatolij Gustschin printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); 675*1b8607e1SAnatolij Gustschin i = 0; 676*1b8607e1SAnatolij Gustschin } 677*1b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; 678*1b8607e1SAnatolij Gustschin bits_per_pixel = vesa_modes[i].bits_per_pixel; 679*1b8607e1SAnatolij Gustschin vesa_idx = vesa_modes[i].resindex; 680*1b8607e1SAnatolij Gustschin } else { 681*1b8607e1SAnatolij Gustschin res_mode = (struct ctfb_res_modes *) &var_mode; 682*1b8607e1SAnatolij Gustschin bits_per_pixel = video_get_params (res_mode, penv); 683*1b8607e1SAnatolij Gustschin } 684*1b8607e1SAnatolij Gustschin 685*1b8607e1SAnatolij Gustschin /* calculate hsynch and vsynch freq (info only) */ 686*1b8607e1SAnatolij Gustschin t1 = (res_mode->left_margin + res_mode->xres + 687*1b8607e1SAnatolij Gustschin res_mode->right_margin + res_mode->hsync_len) / 8; 688*1b8607e1SAnatolij Gustschin t1 *= 8; 689*1b8607e1SAnatolij Gustschin t1 *= res_mode->pixclock; 690*1b8607e1SAnatolij Gustschin t1 /= 1000; 691*1b8607e1SAnatolij Gustschin hsynch = 1000000000L / t1; 692*1b8607e1SAnatolij Gustschin t1 *= (res_mode->upper_margin + res_mode->yres + 693*1b8607e1SAnatolij Gustschin res_mode->lower_margin + res_mode->vsync_len); 694*1b8607e1SAnatolij Gustschin t1 /= 1000; 695*1b8607e1SAnatolij Gustschin vsynch = 1000000000L / t1; 696*1b8607e1SAnatolij Gustschin 697352d2591SJean-Christophe PLAGNIOL-VILLARD /* fill in Graphic device struct */ 698*1b8607e1SAnatolij Gustschin sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, 699*1b8607e1SAnatolij Gustschin res_mode->yres, bits_per_pixel, (hsynch / 1000), 700*1b8607e1SAnatolij Gustschin (vsynch / 1000)); 701352d2591SJean-Christophe PLAGNIOL-VILLARD printf ("%s\n", pGD->modeIdent); 702*1b8607e1SAnatolij Gustschin pGD->winSizeX = res_mode->xres; 703*1b8607e1SAnatolij Gustschin pGD->winSizeY = res_mode->yres; 704*1b8607e1SAnatolij Gustschin pGD->plnSizeX = res_mode->xres; 705*1b8607e1SAnatolij Gustschin pGD->plnSizeY = res_mode->yres; 706352d2591SJean-Christophe PLAGNIOL-VILLARD 707*1b8607e1SAnatolij Gustschin switch (bits_per_pixel) { 708*1b8607e1SAnatolij Gustschin case 24: 709*1b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 4; 710*1b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_32BIT_X888RGB; 711*1b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 712*1b8607e1SAnatolij Gustschin pGD->winSizeX = 832; 713*1b8607e1SAnatolij Gustschin pGD->plnSizeX = 832; 714*1b8607e1SAnatolij Gustschin } 715*1b8607e1SAnatolij Gustschin break; 716*1b8607e1SAnatolij Gustschin case 16: 717*1b8607e1SAnatolij Gustschin pGD->gdfBytesPP = 2; 718*1b8607e1SAnatolij Gustschin pGD->gdfIndex = GDF_16BIT_565RGB; 719*1b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 720*1b8607e1SAnatolij Gustschin pGD->winSizeX = 896; 721*1b8607e1SAnatolij Gustschin pGD->plnSizeX = 896; 722*1b8607e1SAnatolij Gustschin } 723*1b8607e1SAnatolij Gustschin break; 724*1b8607e1SAnatolij Gustschin default: 725*1b8607e1SAnatolij Gustschin if (res_mode->xres == 800) { 726*1b8607e1SAnatolij Gustschin pGD->winSizeX = 1024; 727*1b8607e1SAnatolij Gustschin pGD->plnSizeX = 1024; 728*1b8607e1SAnatolij Gustschin } 729352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfBytesPP = 1; 730352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->gdfIndex = GDF__8BIT_INDEX; 731*1b8607e1SAnatolij Gustschin break; 732*1b8607e1SAnatolij Gustschin } 733352d2591SJean-Christophe PLAGNIOL-VILLARD 734352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; 735352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->pciBase = rinfo->fb_base_phys; 736352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->frameAdrs = rinfo->fb_base_phys; 737352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->memSize = 64 * 1024 * 1024; 738352d2591SJean-Christophe PLAGNIOL-VILLARD 739352d2591SJean-Christophe PLAGNIOL-VILLARD /* Cursor Start Address */ 740352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase = 741352d2591SJean-Christophe PLAGNIOL-VILLARD (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; 742352d2591SJean-Christophe PLAGNIOL-VILLARD if ((pGD->dprBase & 0x0fff) != 0) { 743352d2591SJean-Christophe PLAGNIOL-VILLARD /* allign it */ 744352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase &= 0xfffff000; 745352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->dprBase += 0x00001000; 746352d2591SJean-Christophe PLAGNIOL-VILLARD } 747352d2591SJean-Christophe PLAGNIOL-VILLARD DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, 748352d2591SJean-Christophe PLAGNIOL-VILLARD PATTERN_ADR); 749352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ 750352d2591SJean-Christophe PLAGNIOL-VILLARD pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ 751352d2591SJean-Christophe PLAGNIOL-VILLARD /* set up Hardware */ 752352d2591SJean-Christophe PLAGNIOL-VILLARD 753*1b8607e1SAnatolij Gustschin /* Clear video memory (only visible screen area) */ 754*1b8607e1SAnatolij Gustschin i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; 755352d2591SJean-Christophe PLAGNIOL-VILLARD vm = (unsigned int *) pGD->pciBase; 756352d2591SJean-Christophe PLAGNIOL-VILLARD while (i--) 757352d2591SJean-Christophe PLAGNIOL-VILLARD *vm++ = 0; 758352d2591SJean-Christophe PLAGNIOL-VILLARD /*SetDrawingEngine (bits_per_pixel);*/ 759352d2591SJean-Christophe PLAGNIOL-VILLARD 760*1b8607e1SAnatolij Gustschin if (rinfo->family == CHIP_FAMILY_RV280) 761*1b8607e1SAnatolij Gustschin radeon_setmode_9200(vesa_idx, bits_per_pixel); 762*1b8607e1SAnatolij Gustschin else 763352d2591SJean-Christophe PLAGNIOL-VILLARD radeon_setmode(); 764352d2591SJean-Christophe PLAGNIOL-VILLARD 765352d2591SJean-Christophe PLAGNIOL-VILLARD return ((void *) pGD); 766352d2591SJean-Christophe PLAGNIOL-VILLARD } 767352d2591SJean-Christophe PLAGNIOL-VILLARD 768352d2591SJean-Christophe PLAGNIOL-VILLARD void video_set_lut (unsigned int index, /* color number */ 769352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char r, /* red */ 770352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char g, /* green */ 771352d2591SJean-Christophe PLAGNIOL-VILLARD unsigned char b /* blue */ 772352d2591SJean-Christophe PLAGNIOL-VILLARD ) 773352d2591SJean-Christophe PLAGNIOL-VILLARD { 774352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_INDEX, index); 775352d2591SJean-Christophe PLAGNIOL-VILLARD OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); 776352d2591SJean-Christophe PLAGNIOL-VILLARD } 777352d2591SJean-Christophe PLAGNIOL-VILLARD #endif 778