1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 224bf59d0SVasily Khoruzhick /* 324bf59d0SVasily Khoruzhick * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 424bf59d0SVasily Khoruzhick * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com> 524bf59d0SVasily Khoruzhick */ 624bf59d0SVasily Khoruzhick 724bf59d0SVasily Khoruzhick /* Registers at i2c address 0x38 */ 824bf59d0SVasily Khoruzhick 924bf59d0SVasily Khoruzhick #define ANX9804_HDCP_CONTROL_0_REG 0x01 1024bf59d0SVasily Khoruzhick 1124bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_REG 0x80 1224bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_PD_IO 0x80 1324bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_PD_VID 0x40 1424bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_PD_LINK 0x20 1524bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_PD_TOTAL 0x10 1624bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_MODE_SEL 0x08 1724bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_DET_STA 0x04 1824bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_FORCE_DET 0x02 1924bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL1_DET_CTRL 0x01 2024bf59d0SVasily Khoruzhick 2124bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL2_REG 0x81 2224bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL2_CHA_STA 0x04 2324bf59d0SVasily Khoruzhick 2424bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL3_REG 0x82 2524bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0) 2624bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL3_F_VALID BIT(1) 2724bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4) 2824bf59d0SVasily Khoruzhick #define ANX9804_SYS_CTRL3_F_HPD BIT(5) 2924bf59d0SVasily Khoruzhick 3024bf59d0SVasily Khoruzhick #define ANX9804_LINK_BW_SET_REG 0xa0 3124bf59d0SVasily Khoruzhick #define ANX9804_LANE_COUNT_SET_REG 0xa1 3224bf59d0SVasily Khoruzhick #define ANX9804_TRAINING_PTN_SET_REG 0xa2 3324bf59d0SVasily Khoruzhick #define ANX9804_TRAINING_LANE0_SET_REG 0xa3 3424bf59d0SVasily Khoruzhick #define ANX9804_TRAINING_LANE1_SET_REG 0xa4 3524bf59d0SVasily Khoruzhick #define ANX9804_TRAINING_LANE2_SET_REG 0xa5 3624bf59d0SVasily Khoruzhick #define ANX9804_TRAINING_LANE3_SET_REG 0xa6 3724bf59d0SVasily Khoruzhick 3824bf59d0SVasily Khoruzhick #define ANX9804_LINK_TRAINING_CTRL_REG 0xa8 3924bf59d0SVasily Khoruzhick #define ANX9804_LINK_TRAINING_CTRL_EN BIT(0) 4024bf59d0SVasily Khoruzhick 4124bf59d0SVasily Khoruzhick #define ANX9804_LINK_DEBUG_REG 0xb8 4224bf59d0SVasily Khoruzhick #define ANX9804_PLL_CTRL_REG 0xc7 4324bf59d0SVasily Khoruzhick #define ANX9804_ANALOG_POWER_DOWN_REG 0xc8 4424bf59d0SVasily Khoruzhick 4524bf59d0SVasily Khoruzhick #define ANX9804_AUX_CH_STA 0xe0 4624bf59d0SVasily Khoruzhick #define ANX9804_AUX_BUSY BIT(4) 4724bf59d0SVasily Khoruzhick #define ANX9804_AUX_STATUS_MASK 0x0f 4824bf59d0SVasily Khoruzhick 4924bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_RX_COMM 0xe3 5024bf59d0SVasily Khoruzhick #define ANX9804_AUX_RX_COMM_I2C_DEFER BIT(3) 5124bf59d0SVasily Khoruzhick #define ANX9804_AUX_RX_COMM_AUX_DEFER BIT(1) 5224bf59d0SVasily Khoruzhick 5324bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_CH_CTL_1 0xe5 5424bf59d0SVasily Khoruzhick #define ANX9804_AUX_LENGTH(x) (((x - 1) & 0x0f) << 4) 5524bf59d0SVasily Khoruzhick #define ANX9804_AUX_TX_COMM_MASK 0x0f 5624bf59d0SVasily Khoruzhick #define ANX9804_AUX_TX_COMM_DP_TRANSACTION BIT(3) 5724bf59d0SVasily Khoruzhick #define ANX9804_AUX_TX_COMM_MOT BIT(2) 5824bf59d0SVasily Khoruzhick #define ANX9804_AUX_TX_COMM_READ BIT(0) 5924bf59d0SVasily Khoruzhick 6024bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_ADDR_7_0 0xe6 6124bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_ADDR_15_8 0xe7 6224bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_ADDR_19_16 0xe8 6324bf59d0SVasily Khoruzhick 6424bf59d0SVasily Khoruzhick #define ANX9804_DP_AUX_CH_CTL_2 0xe9 6524bf59d0SVasily Khoruzhick #define ANX9804_ADDR_ONLY BIT(1) 6624bf59d0SVasily Khoruzhick #define ANX9804_AUX_EN BIT(0) 6724bf59d0SVasily Khoruzhick 6824bf59d0SVasily Khoruzhick #define ANX9804_BUF_DATA_0 0xf0 6924bf59d0SVasily Khoruzhick 7024bf59d0SVasily Khoruzhick /* Registers at i2c address 0x39 */ 7124bf59d0SVasily Khoruzhick 7224bf59d0SVasily Khoruzhick #define ANX9804_DEV_IDH_REG 0x03 7324bf59d0SVasily Khoruzhick 7424bf59d0SVasily Khoruzhick #define ANX9804_POWERD_CTRL_REG 0x05 7524bf59d0SVasily Khoruzhick #define ANX9804_POWERD_AUDIO BIT(4) 7624bf59d0SVasily Khoruzhick 7724bf59d0SVasily Khoruzhick #define ANX9804_RST_CTRL_REG 0x06 7824bf59d0SVasily Khoruzhick 7924bf59d0SVasily Khoruzhick #define ANX9804_RST_CTRL2_REG 0x07 8024bf59d0SVasily Khoruzhick #define ANX9804_RST_CTRL2_AUX BIT(2) 8124bf59d0SVasily Khoruzhick #define ANX9804_RST_CTRL2_AC_MODE BIT(6) 8224bf59d0SVasily Khoruzhick 8324bf59d0SVasily Khoruzhick #define ANX9804_VID_CTRL1_REG 0x08 8424bf59d0SVasily Khoruzhick #define ANX9804_VID_CTRL1_VID_EN BIT(7) 8524bf59d0SVasily Khoruzhick #define ANX9804_VID_CTRL1_EDGE BIT(0) 8624bf59d0SVasily Khoruzhick 8724bf59d0SVasily Khoruzhick #define ANX9804_VID_CTRL2_REG 0x09 8824bf59d0SVasily Khoruzhick #define ANX9804_ANALOG_DEBUG_REG1 0xdc 8924bf59d0SVasily Khoruzhick #define ANX9804_ANALOG_DEBUG_REG3 0xde 9024bf59d0SVasily Khoruzhick #define ANX9804_PLL_FILTER_CTRL1 0xdf 9124bf59d0SVasily Khoruzhick #define ANX9804_PLL_FILTER_CTRL3 0xe1 9224bf59d0SVasily Khoruzhick #define ANX9804_PLL_FILTER_CTRL 0xe2 9324bf59d0SVasily Khoruzhick #define ANX9804_PLL_CTRL3 0xe6 9424bf59d0SVasily Khoruzhick 9524bf59d0SVasily Khoruzhick #define ANX9804_DP_INT_STA 0xf7 9624bf59d0SVasily Khoruzhick #define ANX9804_RPLY_RECEIV BIT(1) 9724bf59d0SVasily Khoruzhick #define ANX9804_AUX_ERR BIT(0) 98