xref: /openbmc/u-boot/drivers/video/anx9804.c (revision ae485b54)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) 2015 Hans de Goede <hdegoede@redhat.com>
4  */
5 
6 /*
7  * Support for the ANX9804 bridge chip, which can take pixel data coming
8  * from a parallel LCD interface and translate it on the flight into a DP
9  * interface for driving eDP TFT displays.
10  */
11 
12 #include <common.h>
13 #include <i2c.h>
14 #include "anx98xx-edp.h"
15 #include "anx9804.h"
16 
17 /**
18  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
19  *
20  * This function will init an anx9804 parallel lcd to dp bridge chip
21  * using the passed in parameters.
22  *
23  * @i2c_bus:	Number of the i2c bus to which the anx9804 is connected.
24  * @lanes:	Number of displayport lanes to use
25  * @data_rate:	Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
26  * @bpp:	Bits per pixel, must be 18 or 24
27  */
28 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
29 {
30 	unsigned int orig_i2c_bus = i2c_get_bus_num();
31 	u8 c, colordepth;
32 	int i;
33 
34 	i2c_set_bus_num(i2c_bus);
35 
36 	if (bpp == 18)
37 		colordepth = 0x00; /* 6 bit */
38 	else
39 		colordepth = 0x10; /* 8 bit */
40 
41 	/* Reset */
42 	i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
43 	mdelay(100);
44 	i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
45 
46 	/* Write 0 to the powerdown reg (powerup everything) */
47 	i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
48 
49 	c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
50 	if (c != 0x98) {
51 		printf("Error anx9804 chipid mismatch\n");
52 		i2c_set_bus_num(orig_i2c_bus);
53 		return;
54 	}
55 
56 	for (i = 0; i < 100; i++) {
57 		c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
58 		i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
59 		c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
60 		if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
61 			break;
62 
63 		mdelay(5);
64 	}
65 	if (i == 100)
66 		printf("Error anx9804 clock is not stable\n");
67 
68 	i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
69 
70 	/* Set a bunch of analog related register values */
71 	i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
72 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
73 	i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
74 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
75 	i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
76 	i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
77 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
78 	i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
79 	i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
80 
81 	/* Force HPD */
82 	i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
83 		      ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
84 
85 	/* Power up and configure lanes */
86 	i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
87 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
88 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
89 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
90 	i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
91 
92 	/* Reset AUX CH */
93 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
94 		      ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
95 	i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
96 		      ANX9804_RST_CTRL2_AC_MODE);
97 
98 	/* Powerdown audio and some other unused bits */
99 	i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
100 	i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
101 	i2c_reg_write(0x38, 0xa7, 0x00);
102 
103 	/* Set data-rate / lanes */
104 	i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
105 	i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
106 
107 	/* Link training */
108 	i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
109 		      ANX9804_LINK_TRAINING_CTRL_EN);
110 	mdelay(5);
111 	for (i = 0; i < 100; i++) {
112 		c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
113 		if ((c & 0x01) == 0)
114 			break;
115 
116 		mdelay(5);
117 	}
118 	if(i == 100) {
119 		printf("Error anx9804 link training timeout\n");
120 		i2c_set_bus_num(orig_i2c_bus);
121 		return;
122 	}
123 
124 	/* Enable */
125 	i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
126 		      ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
127 	/* Force stream valid */
128 	i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
129 		      ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
130 		      ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
131 
132 	i2c_set_bus_num(orig_i2c_bus);
133 }
134