1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> 4 * B&R Industrial Automation GmbH - http://www.br-automation.com 5 * 6 * minimal framebuffer driver for TI's AM335x SoC to be compatible with 7 * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c) 8 * 9 * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette) 10 * - sets up LCD controller as in 'am335x_lcdpanel' struct given 11 * - starts output DMA from gd->fb_base buffer 12 */ 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <lcd.h> 20 #include "am335x-fb.h" 21 22 #if !defined(LCD_CNTL_BASE) 23 #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!" 24 #endif 25 26 #define LCDC_FMAX 200000000 27 28 /* LCD Control Register */ 29 #define LCD_CLK_DIVISOR(x) ((x) << 8) 30 #define LCD_RASTER_MODE 0x01 31 /* LCD Clock Enable Register */ 32 #define LCD_CORECLKEN (0x01 << 0) 33 #define LCD_LIDDCLKEN (0x01 << 1) 34 #define LCD_DMACLKEN (0x01 << 2) 35 /* LCD DMA Control Register */ 36 #define LCD_DMA_BURST_SIZE(x) ((x) << 4) 37 #define LCD_DMA_BURST_1 0x0 38 #define LCD_DMA_BURST_2 0x1 39 #define LCD_DMA_BURST_4 0x2 40 #define LCD_DMA_BURST_8 0x3 41 #define LCD_DMA_BURST_16 0x4 42 /* LCD Timing_0 Register */ 43 #define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24) 44 #define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16) 45 #define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10) 46 #define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4) 47 #define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4) 48 /* LCD Timing_1 Register */ 49 #define LCD_VBP(x) ((x) << 24) 50 #define LCD_VFP(x) ((x) << 16) 51 #define LCD_VSW(x) (((x)-1) << 10) 52 #define LCD_VERLSB(x) (((x)-1) & 0x3FF) 53 /* LCD Timing_2 Register */ 54 #define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21) 55 #define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16) 56 #define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4) 57 #define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8) 58 #define LCD_INVMASK(x) ((x) & 0x3F00000) 59 /* LCD Raster Ctrl Register */ 60 #define LCD_TFT_24BPP_MODE (1 << 25) 61 #define LCD_TFT_24BPP_UNPACK (1 << 26) 62 #define LCD_PALMODE_RAWDATA (0x02 << 20) 63 #define LCD_TFT_MODE (0x01 << 7) 64 #define LCD_RASTER_ENABLE (0x01 << 0) 65 66 67 /* Macro definitions */ 68 #define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3) 69 70 struct am335x_lcdhw { 71 unsigned int pid; /* 0x00 */ 72 unsigned int ctrl; /* 0x04 */ 73 unsigned int gap0; /* 0x08 */ 74 unsigned int lidd_ctrl; /* 0x0C */ 75 unsigned int lidd_cs0_conf; /* 0x10 */ 76 unsigned int lidd_cs0_addr; /* 0x14 */ 77 unsigned int lidd_cs0_data; /* 0x18 */ 78 unsigned int lidd_cs1_conf; /* 0x1C */ 79 unsigned int lidd_cs1_addr; /* 0x20 */ 80 unsigned int lidd_cs1_data; /* 0x24 */ 81 unsigned int raster_ctrl; /* 0x28 */ 82 unsigned int raster_timing0; /* 0x2C */ 83 unsigned int raster_timing1; /* 0x30 */ 84 unsigned int raster_timing2; /* 0x34 */ 85 unsigned int raster_subpanel; /* 0x38 */ 86 unsigned int raster_subpanel2; /* 0x3C */ 87 unsigned int lcddma_ctrl; /* 0x40 */ 88 unsigned int lcddma_fb0_base; /* 0x44 */ 89 unsigned int lcddma_fb0_ceiling; /* 0x48 */ 90 unsigned int lcddma_fb1_base; /* 0x4C */ 91 unsigned int lcddma_fb1_ceiling; /* 0x50 */ 92 unsigned int sysconfig; /* 0x54 */ 93 unsigned int irqstatus_raw; /* 0x58 */ 94 unsigned int irqstatus; /* 0x5C */ 95 unsigned int irqenable_set; /* 0x60 */ 96 unsigned int irqenable_clear; /* 0x64 */ 97 unsigned int gap1; /* 0x68 */ 98 unsigned int clkc_enable; /* 0x6C */ 99 unsigned int clkc_reset; /* 0x70 */ 100 }; 101 102 static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE; 103 104 DECLARE_GLOBAL_DATA_PTR; 105 106 int lcd_get_size(int *line_length) 107 { 108 *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; 109 return *line_length * panel_info.vl_row + 0x20; 110 } 111 112 int am335xfb_init(struct am335x_lcdpanel *panel) 113 { 114 u32 raster_ctrl = 0; 115 116 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; 117 struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 }; 118 unsigned int m, n, d, best_d = 2; 119 int err = 0, err_r = 0; 120 121 if (gd->fb_base == 0) { 122 printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n"); 123 return -1; 124 } 125 if (panel == NULL) { 126 printf("ERROR: missing ptr to am335x_lcdpanel!\n"); 127 return -1; 128 } 129 130 /* We can already set the bits for the raster_ctrl in this check */ 131 switch (panel->bpp) { 132 case 16: 133 break; 134 case 32: 135 raster_ctrl |= LCD_TFT_24BPP_UNPACK; 136 /* fallthrough */ 137 case 24: 138 raster_ctrl |= LCD_TFT_24BPP_MODE; 139 break; 140 default: 141 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp); 142 return -1; 143 } 144 145 /* check given clock-frequency */ 146 if (panel->pxl_clk > (LCDC_FMAX / 2)) { 147 pr_err("am335x-fb: requested pxl-clk: %d not supported!\n", 148 panel->pxl_clk); 149 return -1; 150 } 151 152 debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ", 153 panel->hactive, panel->vactive, panel->bpp, 154 panel->hfp, panel->hbp, panel->hsw); 155 debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n", 156 panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk); 157 debug("using frambuffer at 0x%08x with size %d.\n", 158 (unsigned int)gd->fb_base, FBSIZE(panel)); 159 160 /* setup display pll for requested clock frequency */ 161 err = panel->pxl_clk; 162 err_r = err; 163 164 for (d = 2; d < 255; d++) { 165 for (m = 2; m < 2047; m++) { 166 if ((V_OSCK * m) < (panel->pxl_clk * d)) 167 continue; 168 n = (V_OSCK * m) / (panel->pxl_clk * d); 169 if (n > 127) 170 break; 171 if (((V_OSCK * m) / n) > LCDC_FMAX) 172 break; 173 174 err = abs((V_OSCK * m) / n / d - panel->pxl_clk); 175 if (err < err_r) { 176 err_r = err; 177 dpll_disp.m = m; 178 dpll_disp.n = n; 179 best_d = d; 180 } 181 } 182 } 183 debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n", 184 __func__, err_r, dpll_disp.m, dpll_disp.n, best_d); 185 do_setup_dpll(&dpll_disp_regs, &dpll_disp); 186 187 /* clock source for LCDC from dispPLL M2 */ 188 writel(0x0, &cmdpll->clklcdcpixelclk); 189 190 /* palette default entry */ 191 memset((void *)gd->fb_base, 0, 0x20); 192 *(unsigned int *)gd->fb_base = 0x4000; 193 /* point fb behind palette */ 194 gd->fb_base += 0x20; 195 196 /* turn ON display through powercontrol function if accessible */ 197 if (panel->panel_power_ctrl != NULL) 198 panel->panel_power_ctrl(1); 199 200 debug("am335x-fb: wait for stable power ...\n"); 201 mdelay(panel->pup_delay); 202 lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN; 203 lcdhw->raster_ctrl = 0; 204 lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE; 205 lcdhw->lcddma_fb0_base = gd->fb_base; 206 lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel); 207 lcdhw->lcddma_fb1_base = gd->fb_base; 208 lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel); 209 lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); 210 211 lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) | 212 LCD_HORMSB(panel->hactive) | 213 LCD_HFPLSB(panel->hfp) | 214 LCD_HBPLSB(panel->hbp) | 215 LCD_HSWLSB(panel->hsw); 216 lcdhw->raster_timing1 = LCD_VBP(panel->vbp) | 217 LCD_VFP(panel->vfp) | 218 LCD_VSW(panel->vsw) | 219 LCD_VERLSB(panel->vactive); 220 lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) | 221 LCD_VERMSB(panel->vactive) | 222 LCD_INVMASK(panel->pol) | 223 LCD_HBPMSB(panel->hbp) | 224 LCD_HFPMSB(panel->hfp) | 225 0x0000FF00; /* clk cycles for ac-bias */ 226 lcdhw->raster_ctrl = raster_ctrl | 227 LCD_PALMODE_RAWDATA | 228 LCD_TFT_MODE | 229 LCD_RASTER_ENABLE; 230 231 debug("am335x-fb: waiting picture to be stable.\n."); 232 mdelay(panel->pon_delay); 233 234 return 0; 235 } 236