1ade8127aSBin Mengconfig VIDEO_X86 2ade8127aSBin Meng bool "Enable x86 video driver support" 3ade8127aSBin Meng depends on X86 4ade8127aSBin Meng default n 5ade8127aSBin Meng help 6ade8127aSBin Meng Turn on this option to enable a very simple driver which uses vesa 7ade8127aSBin Meng to discover the video mode and then provides a frame buffer for use 8ade8127aSBin Meng by U-Boot. 9b8329acfSSiarhei Siamashka 10b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828 11b8329acfSSiarhei Siamashka bool "SSD2828 bridge chip" 12b8329acfSSiarhei Siamashka default n 13b8329acfSSiarhei Siamashka ---help--- 14b8329acfSSiarhei Siamashka Support for the SSD2828 bridge chip, which can take pixel data coming 15b8329acfSSiarhei Siamashka from a parallel LCD interface and translate it on the fly into MIPI DSI 16b8329acfSSiarhei Siamashka interface for driving a MIPI compatible LCD panel. It uses SPI for 17b8329acfSSiarhei Siamashka configuration. 18b8329acfSSiarhei Siamashka 19b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_TX_CLK 20b8329acfSSiarhei Siamashka int "SSD2828 TX_CLK frequency (in MHz)" 21b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 22*dddccd69SSiarhei Siamashka default 0 23b8329acfSSiarhei Siamashka ---help--- 24b8329acfSSiarhei Siamashka The frequency of the crystal, which is clocking SSD2828. It may be 25b8329acfSSiarhei Siamashka anything in the 8MHz-30MHz range and the exact value should be 26b8329acfSSiarhei Siamashka retrieved from the board schematics. Or in the case of Allwinner 27b8329acfSSiarhei Siamashka hardware, it can be usually found as 'lcd_xtal_freq' variable in 28*dddccd69SSiarhei Siamashka FEX files. It can be also set to 0 for selecting PCLK from the 29*dddccd69SSiarhei Siamashka parallel LCD interface instead of TX_CLK as the PLL clock source. 30b8329acfSSiarhei Siamashka 31b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_RESET 32b8329acfSSiarhei Siamashka string "RESET pin of SSD2828" 33b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 34b8329acfSSiarhei Siamashka default "" 35b8329acfSSiarhei Siamashka ---help--- 36b8329acfSSiarhei Siamashka The reset pin of SSD2828 chip. This takes a string in the format 37b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 38b8329acfSSiarhei Siamashka 39b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_CS 40b8329acfSSiarhei Siamashka string "SPI CS pin for LCD related config job" 41b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 42b8329acfSSiarhei Siamashka default "" 43b8329acfSSiarhei Siamashka ---help--- 44b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 45b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 46b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 47b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 48b8329acfSSiarhei Siamashka 49b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_SCLK 50b8329acfSSiarhei Siamashka string "SPI SCLK pin for LCD related config job" 51b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 52b8329acfSSiarhei Siamashka default "" 53b8329acfSSiarhei Siamashka ---help--- 54b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 55b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 56b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 57b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 58b8329acfSSiarhei Siamashka 59b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MOSI 60b8329acfSSiarhei Siamashka string "SPI MOSI pin for LCD related config job" 61b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 62b8329acfSSiarhei Siamashka default "" 63b8329acfSSiarhei Siamashka ---help--- 64b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 65b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 66b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 67b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 68b8329acfSSiarhei Siamashka 69b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MISO 70b8329acfSSiarhei Siamashka string "SPI MISO pin for LCD related config job (optional)" 71b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 72b8329acfSSiarhei Siamashka default "" 73b8329acfSSiarhei Siamashka ---help--- 74b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 75b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 76b8329acfSSiarhei Siamashka different hardware setups. If wired up, this pin may provide additional 77b8329acfSSiarhei Siamashka useful functionality. Such as bi-directional communication with the 78b8329acfSSiarhei Siamashka hardware and LCD panel id retrieval (if the panel can report it). The 79b8329acfSSiarhei Siamashka option takes a string in the format understood by 'name_to_gpio' 80b8329acfSSiarhei Siamashka function, e.g. PH1 for pin 1 of port H. 81