16b1ba984SSimon Glassconfig VIDEO_VESA 26b1ba984SSimon Glass bool "Enable VESA video driver support" 36b1ba984SSimon Glass default n 46b1ba984SSimon Glass help 56b1ba984SSimon Glass Turn on this option to enable a very simple driver which uses vesa 66b1ba984SSimon Glass to discover the video mode and then provides a frame buffer for use 76b1ba984SSimon Glass by U-Boot. This can in principle be used with any platform that 86b1ba984SSimon Glass supports PCI and video cards that support VESA BIOS Extension (VBE). 96b1ba984SSimon Glass 10*6bde2dc5SBin Mengconfig FRAMEBUFFER_SET_VESA_MODE 11*6bde2dc5SBin Meng bool "Set framebuffer graphics resolution" 12*6bde2dc5SBin Meng depends on VIDEO_VESA 13*6bde2dc5SBin Meng help 14*6bde2dc5SBin Meng Set VESA/native framebuffer mode (needed for bootsplash and graphical 15*6bde2dc5SBin Meng framebuffer console) 16*6bde2dc5SBin Meng 17*6bde2dc5SBin Mengchoice 18*6bde2dc5SBin Meng prompt "framebuffer graphics resolution" 19*6bde2dc5SBin Meng default FRAMEBUFFER_VESA_MODE_117 20*6bde2dc5SBin Meng depends on FRAMEBUFFER_SET_VESA_MODE 21*6bde2dc5SBin Meng help 22*6bde2dc5SBin Meng This option sets the resolution used for the U-Boot framebuffer (and 23*6bde2dc5SBin Meng bootsplash screen). 24*6bde2dc5SBin Meng 25*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_100 26*6bde2dc5SBin Meng bool "640x400 256-color" 27*6bde2dc5SBin Meng 28*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_101 29*6bde2dc5SBin Meng bool "640x480 256-color" 30*6bde2dc5SBin Meng 31*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_102 32*6bde2dc5SBin Meng bool "800x600 16-color" 33*6bde2dc5SBin Meng 34*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_103 35*6bde2dc5SBin Meng bool "800x600 256-color" 36*6bde2dc5SBin Meng 37*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_104 38*6bde2dc5SBin Meng bool "1024x768 16-color" 39*6bde2dc5SBin Meng 40*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_105 41*6bde2dc5SBin Meng bool "1024x7686 256-color" 42*6bde2dc5SBin Meng 43*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_106 44*6bde2dc5SBin Meng bool "1280x1024 16-color" 45*6bde2dc5SBin Meng 46*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_107 47*6bde2dc5SBin Meng bool "1280x1024 256-color" 48*6bde2dc5SBin Meng 49*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_108 50*6bde2dc5SBin Meng bool "80x60 text" 51*6bde2dc5SBin Meng 52*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_109 53*6bde2dc5SBin Meng bool "132x25 text" 54*6bde2dc5SBin Meng 55*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10A 56*6bde2dc5SBin Meng bool "132x43 text" 57*6bde2dc5SBin Meng 58*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10B 59*6bde2dc5SBin Meng bool "132x50 text" 60*6bde2dc5SBin Meng 61*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10C 62*6bde2dc5SBin Meng bool "132x60 text" 63*6bde2dc5SBin Meng 64*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10D 65*6bde2dc5SBin Meng bool "320x200 32k-color (1:5:5:5)" 66*6bde2dc5SBin Meng 67*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10E 68*6bde2dc5SBin Meng bool "320x200 64k-color (5:6:5)" 69*6bde2dc5SBin Meng 70*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10F 71*6bde2dc5SBin Meng bool "320x200 16.8M-color (8:8:8)" 72*6bde2dc5SBin Meng 73*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_110 74*6bde2dc5SBin Meng bool "640x480 32k-color (1:5:5:5)" 75*6bde2dc5SBin Meng 76*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_111 77*6bde2dc5SBin Meng bool "640x480 64k-color (5:6:5)" 78*6bde2dc5SBin Meng 79*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_112 80*6bde2dc5SBin Meng bool "640x480 16.8M-color (8:8:8)" 81*6bde2dc5SBin Meng 82*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_113 83*6bde2dc5SBin Meng bool "800x600 32k-color (1:5:5:5)" 84*6bde2dc5SBin Meng 85*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_114 86*6bde2dc5SBin Meng bool "800x600 64k-color (5:6:5)" 87*6bde2dc5SBin Meng 88*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_115 89*6bde2dc5SBin Meng bool "800x600 16.8M-color (8:8:8)" 90*6bde2dc5SBin Meng 91*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_116 92*6bde2dc5SBin Meng bool "1024x768 32k-color (1:5:5:5)" 93*6bde2dc5SBin Meng 94*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_117 95*6bde2dc5SBin Meng bool "1024x768 64k-color (5:6:5)" 96*6bde2dc5SBin Meng 97*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_118 98*6bde2dc5SBin Meng bool "1024x768 16.8M-color (8:8:8)" 99*6bde2dc5SBin Meng 100*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_119 101*6bde2dc5SBin Meng bool "1280x1024 32k-color (1:5:5:5)" 102*6bde2dc5SBin Meng 103*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11A 104*6bde2dc5SBin Meng bool "1280x1024 64k-color (5:6:5)" 105*6bde2dc5SBin Meng 106*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11B 107*6bde2dc5SBin Meng bool "1280x1024 16.8M-color (8:8:8)" 108*6bde2dc5SBin Meng 109*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_USER 110*6bde2dc5SBin Meng bool "Manually select VESA mode" 111*6bde2dc5SBin Meng 112*6bde2dc5SBin Mengendchoice 113*6bde2dc5SBin Meng 114*6bde2dc5SBin Meng# Map the config names to an integer (KB). 115*6bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE 116*6bde2dc5SBin Meng prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 117*6bde2dc5SBin Meng hex 118*6bde2dc5SBin Meng default 0x100 if FRAMEBUFFER_VESA_MODE_100 119*6bde2dc5SBin Meng default 0x101 if FRAMEBUFFER_VESA_MODE_101 120*6bde2dc5SBin Meng default 0x102 if FRAMEBUFFER_VESA_MODE_102 121*6bde2dc5SBin Meng default 0x103 if FRAMEBUFFER_VESA_MODE_103 122*6bde2dc5SBin Meng default 0x104 if FRAMEBUFFER_VESA_MODE_104 123*6bde2dc5SBin Meng default 0x105 if FRAMEBUFFER_VESA_MODE_105 124*6bde2dc5SBin Meng default 0x106 if FRAMEBUFFER_VESA_MODE_106 125*6bde2dc5SBin Meng default 0x107 if FRAMEBUFFER_VESA_MODE_107 126*6bde2dc5SBin Meng default 0x108 if FRAMEBUFFER_VESA_MODE_108 127*6bde2dc5SBin Meng default 0x109 if FRAMEBUFFER_VESA_MODE_109 128*6bde2dc5SBin Meng default 0x10A if FRAMEBUFFER_VESA_MODE_10A 129*6bde2dc5SBin Meng default 0x10B if FRAMEBUFFER_VESA_MODE_10B 130*6bde2dc5SBin Meng default 0x10C if FRAMEBUFFER_VESA_MODE_10C 131*6bde2dc5SBin Meng default 0x10D if FRAMEBUFFER_VESA_MODE_10D 132*6bde2dc5SBin Meng default 0x10E if FRAMEBUFFER_VESA_MODE_10E 133*6bde2dc5SBin Meng default 0x10F if FRAMEBUFFER_VESA_MODE_10F 134*6bde2dc5SBin Meng default 0x110 if FRAMEBUFFER_VESA_MODE_110 135*6bde2dc5SBin Meng default 0x111 if FRAMEBUFFER_VESA_MODE_111 136*6bde2dc5SBin Meng default 0x112 if FRAMEBUFFER_VESA_MODE_112 137*6bde2dc5SBin Meng default 0x113 if FRAMEBUFFER_VESA_MODE_113 138*6bde2dc5SBin Meng default 0x114 if FRAMEBUFFER_VESA_MODE_114 139*6bde2dc5SBin Meng default 0x115 if FRAMEBUFFER_VESA_MODE_115 140*6bde2dc5SBin Meng default 0x116 if FRAMEBUFFER_VESA_MODE_116 141*6bde2dc5SBin Meng default 0x117 if FRAMEBUFFER_VESA_MODE_117 142*6bde2dc5SBin Meng default 0x118 if FRAMEBUFFER_VESA_MODE_118 143*6bde2dc5SBin Meng default 0x119 if FRAMEBUFFER_VESA_MODE_119 144*6bde2dc5SBin Meng default 0x11A if FRAMEBUFFER_VESA_MODE_11A 145*6bde2dc5SBin Meng default 0x11B if FRAMEBUFFER_VESA_MODE_11B 146*6bde2dc5SBin Meng default 0x117 if FRAMEBUFFER_VESA_MODE_USER 147*6bde2dc5SBin Meng 148b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828 149b8329acfSSiarhei Siamashka bool "SSD2828 bridge chip" 150b8329acfSSiarhei Siamashka default n 151b8329acfSSiarhei Siamashka ---help--- 152b8329acfSSiarhei Siamashka Support for the SSD2828 bridge chip, which can take pixel data coming 153b8329acfSSiarhei Siamashka from a parallel LCD interface and translate it on the fly into MIPI DSI 154b8329acfSSiarhei Siamashka interface for driving a MIPI compatible LCD panel. It uses SPI for 155b8329acfSSiarhei Siamashka configuration. 156b8329acfSSiarhei Siamashka 157b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_TX_CLK 158b8329acfSSiarhei Siamashka int "SSD2828 TX_CLK frequency (in MHz)" 159b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 160dddccd69SSiarhei Siamashka default 0 161b8329acfSSiarhei Siamashka ---help--- 162b8329acfSSiarhei Siamashka The frequency of the crystal, which is clocking SSD2828. It may be 163b8329acfSSiarhei Siamashka anything in the 8MHz-30MHz range and the exact value should be 164b8329acfSSiarhei Siamashka retrieved from the board schematics. Or in the case of Allwinner 165b8329acfSSiarhei Siamashka hardware, it can be usually found as 'lcd_xtal_freq' variable in 166dddccd69SSiarhei Siamashka FEX files. It can be also set to 0 for selecting PCLK from the 167dddccd69SSiarhei Siamashka parallel LCD interface instead of TX_CLK as the PLL clock source. 168b8329acfSSiarhei Siamashka 169b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_RESET 170b8329acfSSiarhei Siamashka string "RESET pin of SSD2828" 171b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 172b8329acfSSiarhei Siamashka default "" 173b8329acfSSiarhei Siamashka ---help--- 174b8329acfSSiarhei Siamashka The reset pin of SSD2828 chip. This takes a string in the format 175b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 176b8329acfSSiarhei Siamashka 177a5464f2bSHans de Goedeconfig VIDEO_LCD_HITACHI_TX18D42VM 178a5464f2bSHans de Goede bool "Hitachi tx18d42vm LVDS LCD panel support" 179a5464f2bSHans de Goede depends on VIDEO 180a5464f2bSHans de Goede default n 181a5464f2bSHans de Goede ---help--- 182a5464f2bSHans de Goede Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a 183a5464f2bSHans de Goede lcd controller which needs to be initialized over SPI, once that is 184a5464f2bSHans de Goede done they work like a regular LVDS panel. 185a5464f2bSHans de Goede 186b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_CS 187b8329acfSSiarhei Siamashka string "SPI CS pin for LCD related config job" 188a5464f2bSHans de Goede depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM 189b8329acfSSiarhei Siamashka default "" 190b8329acfSSiarhei Siamashka ---help--- 191b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 192b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 193b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 194b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 195b8329acfSSiarhei Siamashka 196b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_SCLK 197b8329acfSSiarhei Siamashka string "SPI SCLK pin for LCD related config job" 198a5464f2bSHans de Goede depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM 199b8329acfSSiarhei Siamashka default "" 200b8329acfSSiarhei Siamashka ---help--- 201b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 202b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 203b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 204b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 205b8329acfSSiarhei Siamashka 206b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MOSI 207b8329acfSSiarhei Siamashka string "SPI MOSI pin for LCD related config job" 208a5464f2bSHans de Goede depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM 209b8329acfSSiarhei Siamashka default "" 210b8329acfSSiarhei Siamashka ---help--- 211b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 212b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 213b8329acfSSiarhei Siamashka different hardware setups. The option takes a string in the format 214b8329acfSSiarhei Siamashka understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H. 215b8329acfSSiarhei Siamashka 216b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MISO 217b8329acfSSiarhei Siamashka string "SPI MISO pin for LCD related config job (optional)" 218b8329acfSSiarhei Siamashka depends on VIDEO_LCD_SSD2828 219b8329acfSSiarhei Siamashka default "" 220b8329acfSSiarhei Siamashka ---help--- 221b8329acfSSiarhei Siamashka This is one of the SPI communication pins, involved in setting up a 222b8329acfSSiarhei Siamashka working LCD configuration. The exact role of SPI may differ for 223b8329acfSSiarhei Siamashka different hardware setups. If wired up, this pin may provide additional 224b8329acfSSiarhei Siamashka useful functionality. Such as bi-directional communication with the 225b8329acfSSiarhei Siamashka hardware and LCD panel id retrieval (if the panel can report it). The 226b8329acfSSiarhei Siamashka option takes a string in the format understood by 'name_to_gpio' 227b8329acfSSiarhei Siamashka function, e.g. PH1 for pin 1 of port H. 22851f2c99eSSimon Glass 22951f2c99eSSimon Glassconfig DISPLAY_PORT 23051f2c99eSSimon Glass bool "Enable DisplayPort support" 23151f2c99eSSimon Glass help 23251f2c99eSSimon Glass eDP (Embedded DisplayPort) is a standard widely used in laptops 23351f2c99eSSimon Glass to drive LCD panels. This framework provides support for enabling 23451f2c99eSSimon Glass these displays where supported by the video hardware. 235e7e8823cSSimon Glass 236e7e8823cSSimon Glassconfig VIDEO_TEGRA124 237e7e8823cSSimon Glass bool "Enable video support on Tegra124" 238e7e8823cSSimon Glass help 239e7e8823cSSimon Glass Tegra124 supports many video output options including eDP and 240e7e8823cSSimon Glass HDMI. At present only eDP is supported by U-Boot. This option 241e7e8823cSSimon Glass enables this support which can be used on devices which 242e7e8823cSSimon Glass have an eDP display connected. 243