xref: /openbmc/u-boot/drivers/video/Kconfig (revision 66525bb7)
10b11dbf7SMasahiro Yamada#
20b11dbf7SMasahiro Yamada# Video configuration
30b11dbf7SMasahiro Yamada#
40b11dbf7SMasahiro Yamada
50b11dbf7SMasahiro Yamadamenu "Graphics support"
60b11dbf7SMasahiro Yamada
76b1ba984SSimon Glassconfig VIDEO_VESA
86b1ba984SSimon Glass	bool "Enable VESA video driver support"
96b1ba984SSimon Glass	default n
106b1ba984SSimon Glass	help
116b1ba984SSimon Glass	  Turn on this option to enable a very simple driver which uses vesa
126b1ba984SSimon Glass	  to discover the video mode and then provides a frame buffer for use
136b1ba984SSimon Glass	  by U-Boot. This can in principle be used with any platform that
146b1ba984SSimon Glass	  supports PCI and video cards that support VESA BIOS Extension (VBE).
156b1ba984SSimon Glass
166bde2dc5SBin Mengconfig FRAMEBUFFER_SET_VESA_MODE
176bde2dc5SBin Meng	bool "Set framebuffer graphics resolution"
186bde2dc5SBin Meng	depends on VIDEO_VESA
196bde2dc5SBin Meng	help
206bde2dc5SBin Meng	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
216bde2dc5SBin Meng	  framebuffer console)
226bde2dc5SBin Meng
236bde2dc5SBin Mengchoice
246bde2dc5SBin Meng	prompt "framebuffer graphics resolution"
256bde2dc5SBin Meng	default FRAMEBUFFER_VESA_MODE_117
266bde2dc5SBin Meng	depends on FRAMEBUFFER_SET_VESA_MODE
276bde2dc5SBin Meng	help
286bde2dc5SBin Meng	  This option sets the resolution used for the U-Boot framebuffer (and
296bde2dc5SBin Meng	  bootsplash screen).
306bde2dc5SBin Meng
316bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_100
326bde2dc5SBin Meng	bool "640x400 256-color"
336bde2dc5SBin Meng
346bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_101
356bde2dc5SBin Meng	bool "640x480 256-color"
366bde2dc5SBin Meng
376bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_102
386bde2dc5SBin Meng	bool "800x600 16-color"
396bde2dc5SBin Meng
406bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_103
416bde2dc5SBin Meng	bool "800x600 256-color"
426bde2dc5SBin Meng
436bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_104
446bde2dc5SBin Meng	bool "1024x768 16-color"
456bde2dc5SBin Meng
466bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_105
476bde2dc5SBin Meng	bool "1024x7686 256-color"
486bde2dc5SBin Meng
496bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_106
506bde2dc5SBin Meng	bool "1280x1024 16-color"
516bde2dc5SBin Meng
526bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_107
536bde2dc5SBin Meng	bool "1280x1024 256-color"
546bde2dc5SBin Meng
556bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_108
566bde2dc5SBin Meng	bool "80x60 text"
576bde2dc5SBin Meng
586bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_109
596bde2dc5SBin Meng	bool "132x25 text"
606bde2dc5SBin Meng
616bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10A
626bde2dc5SBin Meng	bool "132x43 text"
636bde2dc5SBin Meng
646bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10B
656bde2dc5SBin Meng	bool "132x50 text"
666bde2dc5SBin Meng
676bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10C
686bde2dc5SBin Meng	bool "132x60 text"
696bde2dc5SBin Meng
706bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10D
716bde2dc5SBin Meng	bool "320x200 32k-color (1:5:5:5)"
726bde2dc5SBin Meng
736bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10E
746bde2dc5SBin Meng	bool "320x200 64k-color (5:6:5)"
756bde2dc5SBin Meng
766bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_10F
776bde2dc5SBin Meng	bool "320x200 16.8M-color (8:8:8)"
786bde2dc5SBin Meng
796bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_110
806bde2dc5SBin Meng	bool "640x480 32k-color (1:5:5:5)"
816bde2dc5SBin Meng
826bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_111
836bde2dc5SBin Meng	bool "640x480 64k-color (5:6:5)"
846bde2dc5SBin Meng
856bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_112
866bde2dc5SBin Meng	bool "640x480 16.8M-color (8:8:8)"
876bde2dc5SBin Meng
886bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_113
896bde2dc5SBin Meng	bool "800x600 32k-color (1:5:5:5)"
906bde2dc5SBin Meng
916bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_114
926bde2dc5SBin Meng	bool "800x600 64k-color (5:6:5)"
936bde2dc5SBin Meng
946bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_115
956bde2dc5SBin Meng	bool "800x600 16.8M-color (8:8:8)"
966bde2dc5SBin Meng
976bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_116
986bde2dc5SBin Meng	bool "1024x768 32k-color (1:5:5:5)"
996bde2dc5SBin Meng
1006bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_117
1016bde2dc5SBin Meng	bool "1024x768 64k-color (5:6:5)"
1026bde2dc5SBin Meng
1036bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_118
1046bde2dc5SBin Meng	bool "1024x768 16.8M-color (8:8:8)"
1056bde2dc5SBin Meng
1066bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_119
1076bde2dc5SBin Meng	bool "1280x1024 32k-color (1:5:5:5)"
1086bde2dc5SBin Meng
1096bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11A
1106bde2dc5SBin Meng	bool "1280x1024 64k-color (5:6:5)"
1116bde2dc5SBin Meng
1126bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_11B
1136bde2dc5SBin Meng	bool "1280x1024 16.8M-color (8:8:8)"
1146bde2dc5SBin Meng
1156bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE_USER
1166bde2dc5SBin Meng	bool "Manually select VESA mode"
1176bde2dc5SBin Meng
1186bde2dc5SBin Mengendchoice
1196bde2dc5SBin Meng
1206bde2dc5SBin Meng# Map the config names to an integer (KB).
1216bde2dc5SBin Mengconfig FRAMEBUFFER_VESA_MODE
1226bde2dc5SBin Meng	prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
1236bde2dc5SBin Meng	hex
1246bde2dc5SBin Meng	default 0x100 if FRAMEBUFFER_VESA_MODE_100
1256bde2dc5SBin Meng	default 0x101 if FRAMEBUFFER_VESA_MODE_101
1266bde2dc5SBin Meng	default 0x102 if FRAMEBUFFER_VESA_MODE_102
1276bde2dc5SBin Meng	default 0x103 if FRAMEBUFFER_VESA_MODE_103
1286bde2dc5SBin Meng	default 0x104 if FRAMEBUFFER_VESA_MODE_104
1296bde2dc5SBin Meng	default 0x105 if FRAMEBUFFER_VESA_MODE_105
1306bde2dc5SBin Meng	default 0x106 if FRAMEBUFFER_VESA_MODE_106
1316bde2dc5SBin Meng	default 0x107 if FRAMEBUFFER_VESA_MODE_107
1326bde2dc5SBin Meng	default 0x108 if FRAMEBUFFER_VESA_MODE_108
1336bde2dc5SBin Meng	default 0x109 if FRAMEBUFFER_VESA_MODE_109
1346bde2dc5SBin Meng	default 0x10A if FRAMEBUFFER_VESA_MODE_10A
1356bde2dc5SBin Meng	default 0x10B if FRAMEBUFFER_VESA_MODE_10B
1366bde2dc5SBin Meng	default 0x10C if FRAMEBUFFER_VESA_MODE_10C
1376bde2dc5SBin Meng	default 0x10D if FRAMEBUFFER_VESA_MODE_10D
1386bde2dc5SBin Meng	default 0x10E if FRAMEBUFFER_VESA_MODE_10E
1396bde2dc5SBin Meng	default 0x10F if FRAMEBUFFER_VESA_MODE_10F
1406bde2dc5SBin Meng	default 0x110 if FRAMEBUFFER_VESA_MODE_110
1416bde2dc5SBin Meng	default 0x111 if FRAMEBUFFER_VESA_MODE_111
1426bde2dc5SBin Meng	default 0x112 if FRAMEBUFFER_VESA_MODE_112
1436bde2dc5SBin Meng	default 0x113 if FRAMEBUFFER_VESA_MODE_113
1446bde2dc5SBin Meng	default 0x114 if FRAMEBUFFER_VESA_MODE_114
1456bde2dc5SBin Meng	default 0x115 if FRAMEBUFFER_VESA_MODE_115
1466bde2dc5SBin Meng	default 0x116 if FRAMEBUFFER_VESA_MODE_116
1476bde2dc5SBin Meng	default 0x117 if FRAMEBUFFER_VESA_MODE_117
1486bde2dc5SBin Meng	default 0x118 if FRAMEBUFFER_VESA_MODE_118
1496bde2dc5SBin Meng	default 0x119 if FRAMEBUFFER_VESA_MODE_119
1506bde2dc5SBin Meng	default 0x11A if FRAMEBUFFER_VESA_MODE_11A
1516bde2dc5SBin Meng	default 0x11B if FRAMEBUFFER_VESA_MODE_11B
1526bde2dc5SBin Meng	default 0x117 if FRAMEBUFFER_VESA_MODE_USER
1536bde2dc5SBin Meng
154*66525bb7SHans de Goedeconfig VIDEO_LCD_ANX9804
155*66525bb7SHans de Goede	bool "ANX9804 bridge chip"
156*66525bb7SHans de Goede	default n
157*66525bb7SHans de Goede	---help---
158*66525bb7SHans de Goede	Support for the ANX9804 bridge chip, which can take pixel data coming
159*66525bb7SHans de Goede	from a parallel LCD interface and translate it on the fy into a DP
160*66525bb7SHans de Goede	interface for driving eDP TFT displays. It uses I2C for configuration.
161*66525bb7SHans de Goede
162b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828
163b8329acfSSiarhei Siamashka	bool "SSD2828 bridge chip"
164b8329acfSSiarhei Siamashka	default n
165b8329acfSSiarhei Siamashka	---help---
166b8329acfSSiarhei Siamashka	Support for the SSD2828 bridge chip, which can take pixel data coming
167b8329acfSSiarhei Siamashka	from a parallel LCD interface and translate it on the fly into MIPI DSI
168b8329acfSSiarhei Siamashka	interface for driving a MIPI compatible LCD panel. It uses SPI for
169b8329acfSSiarhei Siamashka	configuration.
170b8329acfSSiarhei Siamashka
171b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_TX_CLK
172b8329acfSSiarhei Siamashka	int "SSD2828 TX_CLK frequency (in MHz)"
173b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
174dddccd69SSiarhei Siamashka	default 0
175b8329acfSSiarhei Siamashka	---help---
176b8329acfSSiarhei Siamashka	The frequency of the crystal, which is clocking SSD2828. It may be
177b8329acfSSiarhei Siamashka	anything in the 8MHz-30MHz range and the exact value should be
178b8329acfSSiarhei Siamashka	retrieved from the board schematics. Or in the case of Allwinner
179b8329acfSSiarhei Siamashka	hardware, it can be usually found as 'lcd_xtal_freq' variable in
180dddccd69SSiarhei Siamashka	FEX files. It can be also set to 0 for selecting PCLK from the
181dddccd69SSiarhei Siamashka	parallel LCD interface instead of TX_CLK as the PLL clock source.
182b8329acfSSiarhei Siamashka
183b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SSD2828_RESET
184b8329acfSSiarhei Siamashka	string "RESET pin of SSD2828"
185b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
186b8329acfSSiarhei Siamashka	default ""
187b8329acfSSiarhei Siamashka	---help---
188b8329acfSSiarhei Siamashka	The reset pin of SSD2828 chip. This takes a string in the format
189b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
190b8329acfSSiarhei Siamashka
191a5464f2bSHans de Goedeconfig VIDEO_LCD_HITACHI_TX18D42VM
192a5464f2bSHans de Goede	bool "Hitachi tx18d42vm LVDS LCD panel support"
193a5464f2bSHans de Goede	depends on VIDEO
194a5464f2bSHans de Goede	default n
195a5464f2bSHans de Goede	---help---
196a5464f2bSHans de Goede	Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a
197a5464f2bSHans de Goede	lcd controller which needs to be initialized over SPI, once that is
198a5464f2bSHans de Goede	done they work like a regular LVDS panel.
199a5464f2bSHans de Goede
200b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_CS
201b8329acfSSiarhei Siamashka	string "SPI CS pin for LCD related config job"
202a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
203b8329acfSSiarhei Siamashka	default ""
204b8329acfSSiarhei Siamashka	---help---
205b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
206b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
207b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
208b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
209b8329acfSSiarhei Siamashka
210b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_SCLK
211b8329acfSSiarhei Siamashka	string "SPI SCLK pin for LCD related config job"
212a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
213b8329acfSSiarhei Siamashka	default ""
214b8329acfSSiarhei Siamashka	---help---
215b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
216b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
217b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
218b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
219b8329acfSSiarhei Siamashka
220b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MOSI
221b8329acfSSiarhei Siamashka	string "SPI MOSI pin for LCD related config job"
222a5464f2bSHans de Goede	depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM
223b8329acfSSiarhei Siamashka	default ""
224b8329acfSSiarhei Siamashka	---help---
225b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
226b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
227b8329acfSSiarhei Siamashka	different hardware setups. The option takes a string in the format
228b8329acfSSiarhei Siamashka	understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
229b8329acfSSiarhei Siamashka
230b8329acfSSiarhei Siamashkaconfig VIDEO_LCD_SPI_MISO
231b8329acfSSiarhei Siamashka	string "SPI MISO pin for LCD related config job (optional)"
232b8329acfSSiarhei Siamashka	depends on VIDEO_LCD_SSD2828
233b8329acfSSiarhei Siamashka	default ""
234b8329acfSSiarhei Siamashka	---help---
235b8329acfSSiarhei Siamashka	This is one of the SPI communication pins, involved in setting up a
236b8329acfSSiarhei Siamashka	working LCD configuration. The exact role of SPI may differ for
237b8329acfSSiarhei Siamashka	different hardware setups. If wired up, this pin may provide additional
238b8329acfSSiarhei Siamashka	useful functionality. Such as bi-directional communication with the
239b8329acfSSiarhei Siamashka	hardware and LCD panel id retrieval (if the panel can report it). The
240b8329acfSSiarhei Siamashka	option takes a string in the format understood by 'name_to_gpio'
241b8329acfSSiarhei Siamashka	function, e.g. PH1 for pin 1 of port H.
24251f2c99eSSimon Glass
24351f2c99eSSimon Glassconfig DISPLAY_PORT
24451f2c99eSSimon Glass	bool "Enable DisplayPort support"
24551f2c99eSSimon Glass	help
24651f2c99eSSimon Glass	   eDP (Embedded DisplayPort) is a standard widely used in laptops
24751f2c99eSSimon Glass	   to drive LCD panels. This framework provides support for enabling
24851f2c99eSSimon Glass	   these displays where supported by the video hardware.
249e7e8823cSSimon Glass
250e7e8823cSSimon Glassconfig VIDEO_TEGRA124
251e7e8823cSSimon Glass	bool "Enable video support on Tegra124"
252e7e8823cSSimon Glass	help
253e7e8823cSSimon Glass	   Tegra124 supports many video output options including eDP and
254e7e8823cSSimon Glass	   HDMI. At present only eDP is supported by U-Boot. This option
255e7e8823cSSimon Glass	   enables this support which can be used on devices which
256e7e8823cSSimon Glass	   have an eDP display connected.
257801ab9e9SSimon Glass
258801ab9e9SSimon Glasssource "drivers/video/bridge/Kconfig"
2590b11dbf7SMasahiro Yamada
2600b11dbf7SMasahiro Yamadaendmenu
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