1 /* 2 * OMAP USB PHY Support 3 * 4 * (C) Copyright 2013 5 * Texas Instruments, <www.ti.com> 6 * 7 * Author: Dan Murphy <dmurphy@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <usb.h> 14 #include <asm-generic/errno.h> 15 #include <asm/omap_common.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/sys_proto.h> 18 19 #include <linux/compat.h> 20 #include <linux/usb/dwc3.h> 21 #include <linux/usb/xhci-omap.h> 22 23 #include "../host/xhci.h" 24 25 #ifdef CONFIG_OMAP_USB3PHY1_HOST 26 struct usb_dpll_params { 27 u16 m; 28 u8 n; 29 u8 freq:3; 30 u8 sd; 31 u32 mf; 32 }; 33 34 #define NUM_USB_CLKS 6 35 36 static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = { 37 {1250, 5, 4, 20, 0}, /* 12 MHz */ 38 {3125, 20, 4, 20, 0}, /* 16.8 MHz */ 39 {1172, 8, 4, 20, 65537}, /* 19.2 MHz */ 40 {1250, 12, 4, 20, 0}, /* 26 MHz */ 41 {3125, 47, 4, 20, 92843}, /* 38.4 MHz */ 42 {1000, 7, 4, 10, 0}, /* 20 MHz */ 43 }; 44 45 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) 46 { 47 u32 val; 48 49 writel(SET_PLL_GO, &phy_regs->pll_go); 50 do { 51 val = readl(&phy_regs->pll_status); 52 if (val & PLL_LOCK) 53 break; 54 } while (1); 55 } 56 57 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) 58 { 59 u32 clk_index = get_sys_clk_index(); 60 u32 val; 61 62 val = readl(&phy_regs->pll_config_1); 63 val &= ~PLL_REGN_MASK; 64 val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT; 65 writel(val, &phy_regs->pll_config_1); 66 67 val = readl(&phy_regs->pll_config_2); 68 val &= ~PLL_SELFREQDCO_MASK; 69 val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT; 70 writel(val, &phy_regs->pll_config_2); 71 72 val = readl(&phy_regs->pll_config_1); 73 val &= ~PLL_REGM_MASK; 74 val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT; 75 writel(val, &phy_regs->pll_config_1); 76 77 val = readl(&phy_regs->pll_config_4); 78 val &= ~PLL_REGM_F_MASK; 79 val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT; 80 writel(val, &phy_regs->pll_config_4); 81 82 val = readl(&phy_regs->pll_config_3); 83 val &= ~PLL_SD_MASK; 84 val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT; 85 writel(val, &phy_regs->pll_config_3); 86 87 omap_usb_dpll_relock(phy_regs); 88 } 89 90 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) 91 { 92 u32 rate = get_sys_clk_freq()/1000000; 93 u32 val; 94 95 val = readl((*ctrl)->control_phy_power_usb); 96 val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); 97 val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); 98 val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; 99 100 writel(val, (*ctrl)->control_phy_power_usb); 101 } 102 103 void usb_phy_power(int on) 104 { 105 u32 val; 106 107 val = readl((*ctrl)->control_phy_power_usb); 108 if (on) { 109 val &= ~USB3_PWRCTL_CLK_CMD_MASK; 110 val |= USB3_PHY_TX_RX_POWERON; 111 } else { 112 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); 113 } 114 115 writel(val, (*ctrl)->control_phy_power_usb); 116 } 117 118 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) 119 { 120 omap_usb_dpll_lock(phy_regs); 121 usb3_phy_partial_powerup(phy_regs); 122 /* 123 * Give enough time for the PHY to partially power-up before 124 * powering it up completely. delay value suggested by the HW 125 * team. 126 */ 127 mdelay(100); 128 } 129 130 static void omap_enable_usb3_phy(struct omap_xhci *omap) 131 { 132 u32 val; 133 134 val = (USBOTGSS_DMADISABLE | 135 USBOTGSS_STANDBYMODE_SMRT_WKUP | 136 USBOTGSS_IDLEMODE_NOIDLE); 137 writel(val, &omap->otg_wrapper->sysconfig); 138 139 /* Clear the utmi OTG status */ 140 val = readl(&omap->otg_wrapper->utmi_otg_status); 141 writel(val, &omap->otg_wrapper->utmi_otg_status); 142 143 /* Enable interrupts */ 144 writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); 145 val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | 146 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | 147 USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | 148 USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | 149 USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | 150 USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | 151 USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | 152 USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | 153 USBOTGSS_IRQ_SET_1_OEVT_EN); 154 writel(val, &omap->otg_wrapper->irqenable_set_1); 155 156 /* Clear the IRQ status */ 157 val = readl(&omap->otg_wrapper->irqstatus_1); 158 writel(val, &omap->otg_wrapper->irqstatus_1); 159 val = readl(&omap->otg_wrapper->irqstatus_0); 160 writel(val, &omap->otg_wrapper->irqstatus_0); 161 }; 162 #endif /* CONFIG_OMAP_USB3PHY1_HOST */ 163 164 #ifdef CONFIG_OMAP_USB2PHY2_HOST 165 static void omap_enable_usb2_phy2(struct omap_xhci *omap) 166 { 167 u32 reg, val; 168 169 val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); 170 writel(val, (*ctrl)->control_srcomp_north_side); 171 172 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 173 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 174 175 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, 176 (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K | 177 OTG_SS_CLKCTRL_MODULEMODE_HW)); 178 179 /* This is an undocumented Reserved register */ 180 reg = 0x4a0086c0; 181 val = readl(reg); 182 val |= 0x100; 183 setbits_le32(reg, val); 184 } 185 186 void usb_phy_power(int on) 187 { 188 return; 189 } 190 #endif /* CONFIG_OMAP_USB2PHY2_HOST */ 191 192 #ifdef CONFIG_AM437X_USB2PHY2_HOST 193 static void am437x_enable_usb2_phy2(struct omap_xhci *omap) 194 { 195 const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN | 196 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); 197 198 writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL); 199 writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL); 200 201 writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL); 202 writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL); 203 } 204 205 void usb_phy_power(int on) 206 { 207 u32 val; 208 209 /* USB1_CTRL */ 210 val = readl(USB1_CTRL); 211 if (on) { 212 /* 213 * these bits are re-used on AM437x to power up/down the USB 214 * CM and OTG PHYs, if we don't toggle them, USB will not be 215 * functional on newer silicon revisions 216 */ 217 val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); 218 } else { 219 val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; 220 } 221 222 writel(val, USB1_CTRL); 223 } 224 #endif /* CONFIG_AM437X_USB2PHY2_HOST */ 225 226 void omap_reset_usb_phy(struct dwc3 *dwc3_reg) 227 { 228 /* Assert USB3 PHY reset */ 229 setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 230 231 /* Assert USB2 PHY reset */ 232 setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 233 234 mdelay(100); 235 236 /* Clear USB3 PHY reset */ 237 clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); 238 239 /* Clear USB2 PHY reset */ 240 clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); 241 242 } 243 244 void omap_enable_phy(struct omap_xhci *omap) 245 { 246 #ifdef CONFIG_OMAP_USB2PHY2_HOST 247 omap_enable_usb2_phy2(omap); 248 #endif 249 250 #ifdef CONFIG_AM437X_USB2PHY2_HOST 251 am437x_enable_usb2_phy2(omap); 252 #endif 253 254 #ifdef CONFIG_OMAP_USB3PHY1_HOST 255 omap_enable_usb3_phy(omap); 256 omap_usb3_phy_init(omap->usb3_phy); 257 #endif 258 } 259