1 /* 2 * Mentor USB OTG Core host controller driver. 3 * 4 * Copyright (c) 2008 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 * 21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments 22 */ 23 24 #include <common.h> 25 #include "musb_hcd.h" 26 27 /* MSC control transfers */ 28 #define USB_MSC_BBB_RESET 0xFF 29 #define USB_MSC_BBB_GET_MAX_LUN 0xFE 30 31 /* Endpoint configuration information */ 32 static struct musb_epinfo epinfo[3] = { 33 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ 34 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ 35 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ 36 }; 37 38 /* 39 * This function writes the data toggle value. 40 */ 41 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) 42 { 43 u16 toggle = usb_gettoggle(dev, ep, dir_out); 44 u16 csr; 45 46 if (dir_out) { 47 if (!toggle) 48 writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); 49 else { 50 csr = readw(&musbr->txcsr); 51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; 52 writew(csr, &musbr->txcsr); 53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); 54 writew(csr, &musbr->txcsr); 55 } 56 } else { 57 if (!toggle) 58 writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); 59 else { 60 csr = readw(&musbr->rxcsr); 61 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; 62 writew(csr, &musbr->rxcsr); 63 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); 64 writew(csr, &musbr->rxcsr); 65 } 66 } 67 } 68 69 /* 70 * This function checks if RxStall has occured on the endpoint. If a RxStall 71 * has occured, the RxStall is cleared and 1 is returned. If RxStall has 72 * not occured, 0 is returned. 73 */ 74 static u8 check_stall(u8 ep, u8 dir_out) 75 { 76 u16 csr; 77 78 /* For endpoint 0 */ 79 if (!ep) { 80 csr = readw(&musbr->txcsr); 81 if (csr & MUSB_CSR0_H_RXSTALL) { 82 csr &= ~MUSB_CSR0_H_RXSTALL; 83 writew(csr, &musbr->txcsr); 84 return 1; 85 } 86 } else { /* For non-ep0 */ 87 if (dir_out) { /* is it tx ep */ 88 csr = readw(&musbr->txcsr); 89 if (csr & MUSB_TXCSR_H_RXSTALL) { 90 csr &= ~MUSB_TXCSR_H_RXSTALL; 91 writew(csr, &musbr->txcsr); 92 return 1; 93 } 94 } else { /* is it rx ep */ 95 csr = readw(&musbr->rxcsr); 96 if (csr & MUSB_RXCSR_H_RXSTALL) { 97 csr &= ~MUSB_RXCSR_H_RXSTALL; 98 writew(csr, &musbr->rxcsr); 99 return 1; 100 } 101 } 102 } 103 return 0; 104 } 105 106 /* 107 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout 108 * error and -2 for stall. 109 */ 110 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) 111 { 112 u16 csr; 113 int result = 1; 114 int timeout = CONFIG_MUSB_TIMEOUT; 115 116 while (result > 0) { 117 csr = readw(&musbr->txcsr); 118 if (csr & MUSB_CSR0_H_ERROR) { 119 csr &= ~MUSB_CSR0_H_ERROR; 120 writew(csr, &musbr->txcsr); 121 dev->status = USB_ST_CRC_ERR; 122 result = -1; 123 break; 124 } 125 126 switch (bit_mask) { 127 case MUSB_CSR0_TXPKTRDY: 128 if (!(csr & MUSB_CSR0_TXPKTRDY)) { 129 if (check_stall(MUSB_CONTROL_EP, 0)) { 130 dev->status = USB_ST_STALLED; 131 result = -2; 132 } else 133 result = 0; 134 } 135 break; 136 137 case MUSB_CSR0_RXPKTRDY: 138 if (check_stall(MUSB_CONTROL_EP, 0)) { 139 dev->status = USB_ST_STALLED; 140 result = -2; 141 } else 142 if (csr & MUSB_CSR0_RXPKTRDY) 143 result = 0; 144 break; 145 146 case MUSB_CSR0_H_REQPKT: 147 if (!(csr & MUSB_CSR0_H_REQPKT)) { 148 if (check_stall(MUSB_CONTROL_EP, 0)) { 149 dev->status = USB_ST_STALLED; 150 result = -2; 151 } else 152 result = 0; 153 } 154 break; 155 } 156 157 /* Check the timeout */ 158 if (--timeout) 159 udelay(1); 160 else { 161 dev->status = USB_ST_CRC_ERR; 162 result = -1; 163 break; 164 } 165 } 166 167 return result; 168 } 169 170 /* 171 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. 172 */ 173 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) 174 { 175 u16 csr; 176 int timeout = CONFIG_MUSB_TIMEOUT; 177 178 do { 179 if (check_stall(ep, 1)) { 180 dev->status = USB_ST_STALLED; 181 return 0; 182 } 183 184 csr = readw(&musbr->txcsr); 185 if (csr & MUSB_TXCSR_H_ERROR) { 186 dev->status = USB_ST_CRC_ERR; 187 return 0; 188 } 189 190 /* Check the timeout */ 191 if (--timeout) 192 udelay(1); 193 else { 194 dev->status = USB_ST_CRC_ERR; 195 return -1; 196 } 197 198 } while (csr & MUSB_TXCSR_TXPKTRDY); 199 return 1; 200 } 201 202 /* 203 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. 204 */ 205 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) 206 { 207 u16 csr; 208 int timeout = CONFIG_MUSB_TIMEOUT; 209 210 do { 211 if (check_stall(ep, 0)) { 212 dev->status = USB_ST_STALLED; 213 return 0; 214 } 215 216 csr = readw(&musbr->rxcsr); 217 if (csr & MUSB_RXCSR_H_ERROR) { 218 dev->status = USB_ST_CRC_ERR; 219 return 0; 220 } 221 222 /* Check the timeout */ 223 if (--timeout) 224 udelay(1); 225 else { 226 dev->status = USB_ST_CRC_ERR; 227 return -1; 228 } 229 230 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); 231 return 1; 232 } 233 234 /* 235 * This function performs the setup phase of the control transfer 236 */ 237 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) 238 { 239 int result; 240 u16 csr; 241 242 /* write the control request to ep0 fifo */ 243 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); 244 245 /* enable transfer of setup packet */ 246 csr = readw(&musbr->txcsr); 247 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); 248 writew(csr, &musbr->txcsr); 249 250 /* wait until the setup packet is transmitted */ 251 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 252 dev->act_len = 0; 253 return result; 254 } 255 256 /* 257 * This function handles the control transfer in data phase 258 */ 259 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) 260 { 261 u16 csr; 262 u32 rxlen = 0; 263 u32 nextlen = 0; 264 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 265 u8 *rxbuff = (u8 *)buffer; 266 u8 rxedlength; 267 int result; 268 269 while (rxlen < len) { 270 /* Determine the next read length */ 271 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); 272 273 /* Set the ReqPkt bit */ 274 csr = readw(&musbr->txcsr); 275 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); 276 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); 277 if (result < 0) 278 return result; 279 280 /* Actual number of bytes received by usb */ 281 rxedlength = readb(&musbr->rxcount); 282 283 /* Read the data from the RxFIFO */ 284 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); 285 286 /* Clear the RxPktRdy Bit */ 287 csr = readw(&musbr->txcsr); 288 csr &= ~MUSB_CSR0_RXPKTRDY; 289 writew(csr, &musbr->txcsr); 290 291 /* short packet? */ 292 if (rxedlength != nextlen) { 293 dev->act_len += rxedlength; 294 break; 295 } 296 rxlen += nextlen; 297 dev->act_len = rxlen; 298 } 299 return 0; 300 } 301 302 /* 303 * This function handles the control transfer out data phase 304 */ 305 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) 306 { 307 u16 csr; 308 u32 txlen = 0; 309 u32 nextlen = 0; 310 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 311 u8 *txbuff = (u8 *)buffer; 312 int result = 0; 313 314 while (txlen < len) { 315 /* Determine the next write length */ 316 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); 317 318 /* Load the data to send in FIFO */ 319 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); 320 321 /* Set TXPKTRDY bit */ 322 csr = readw(&musbr->txcsr); 323 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, 324 &musbr->txcsr); 325 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 326 if (result < 0) 327 break; 328 329 txlen += nextlen; 330 dev->act_len = txlen; 331 } 332 return result; 333 } 334 335 /* 336 * This function handles the control transfer out status phase 337 */ 338 static int ctrlreq_out_status_phase(struct usb_device *dev) 339 { 340 u16 csr; 341 int result; 342 343 /* Set the StatusPkt bit */ 344 csr = readw(&musbr->txcsr); 345 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | 346 MUSB_CSR0_H_STATUSPKT); 347 writew(csr, &musbr->txcsr); 348 349 /* Wait until TXPKTRDY bit is cleared */ 350 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 351 return result; 352 } 353 354 /* 355 * This function handles the control transfer in status phase 356 */ 357 static int ctrlreq_in_status_phase(struct usb_device *dev) 358 { 359 u16 csr; 360 int result; 361 362 /* Set the StatusPkt bit and ReqPkt bit */ 363 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; 364 writew(csr, &musbr->txcsr); 365 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); 366 367 /* clear StatusPkt bit and RxPktRdy bit */ 368 csr = readw(&musbr->txcsr); 369 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); 370 writew(csr, &musbr->txcsr); 371 return result; 372 } 373 374 /* 375 * determines the speed of the device (High/Full/Slow) 376 */ 377 static u8 get_dev_speed(struct usb_device *dev) 378 { 379 return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : 380 ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : 381 MUSB_TYPE_SPEED_FULL); 382 } 383 384 /* 385 * configure the hub address and the port address. 386 */ 387 static void config_hub_port(struct usb_device *dev, u8 ep) 388 { 389 u8 chid; 390 u8 hub; 391 392 /* Find out the nearest parent which is high speed */ 393 while (dev->parent->parent != NULL) 394 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) 395 dev = dev->parent; 396 else 397 break; 398 399 /* determine the port address at that hub */ 400 hub = dev->parent->devnum; 401 for (chid = 0; chid < USB_MAXCHILDREN; chid++) 402 if (dev->parent->children[chid] == dev) 403 break; 404 405 /* configure the hub address and the port address */ 406 writeb(hub, &musbr->tar[ep].txhubaddr); 407 writeb((chid + 1), &musbr->tar[ep].txhubport); 408 writeb(hub, &musbr->tar[ep].rxhubaddr); 409 writeb((chid + 1), &musbr->tar[ep].rxhubport); 410 } 411 412 /* 413 * do a control transfer 414 */ 415 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 416 int len, struct devrequest *setup) 417 { 418 int devnum = usb_pipedevice(pipe); 419 u16 csr; 420 u8 devspeed; 421 422 /* select control endpoint */ 423 writeb(MUSB_CONTROL_EP, &musbr->index); 424 csr = readw(&musbr->txcsr); 425 426 /* target addr and (for multipoint) hub addr/port */ 427 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); 428 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); 429 430 /* configure the hub address and the port number as required */ 431 devspeed = get_dev_speed(dev); 432 if ((musb_ishighspeed()) && (dev->parent != NULL) && 433 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 434 config_hub_port(dev, MUSB_CONTROL_EP); 435 writeb(devspeed << 6, &musbr->txtype); 436 } else { 437 writeb(musb_cfg.musb_speed << 6, &musbr->txtype); 438 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); 439 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); 440 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); 441 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); 442 } 443 444 /* Control transfer setup phase */ 445 if (ctrlreq_setup_phase(dev, setup) < 0) 446 return 0; 447 448 switch (setup->request) { 449 case USB_REQ_GET_DESCRIPTOR: 450 case USB_REQ_GET_CONFIGURATION: 451 case USB_REQ_GET_INTERFACE: 452 case USB_REQ_GET_STATUS: 453 case USB_MSC_BBB_GET_MAX_LUN: 454 /* control transfer in-data-phase */ 455 if (ctrlreq_in_data_phase(dev, len, buffer) < 0) 456 return 0; 457 /* control transfer out-status-phase */ 458 if (ctrlreq_out_status_phase(dev) < 0) 459 return 0; 460 break; 461 462 case USB_REQ_SET_ADDRESS: 463 case USB_REQ_SET_CONFIGURATION: 464 case USB_REQ_SET_FEATURE: 465 case USB_REQ_SET_INTERFACE: 466 case USB_REQ_CLEAR_FEATURE: 467 case USB_MSC_BBB_RESET: 468 /* control transfer in status phase */ 469 if (ctrlreq_in_status_phase(dev) < 0) 470 return 0; 471 break; 472 473 case USB_REQ_SET_DESCRIPTOR: 474 /* control transfer out data phase */ 475 if (ctrlreq_out_data_phase(dev, len, buffer) < 0) 476 return 0; 477 /* control transfer in status phase */ 478 if (ctrlreq_in_status_phase(dev) < 0) 479 return 0; 480 break; 481 482 default: 483 /* unhandled control transfer */ 484 return -1; 485 } 486 487 dev->status = 0; 488 dev->act_len = len; 489 return len; 490 } 491 492 /* 493 * do a bulk transfer 494 */ 495 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 496 void *buffer, int len) 497 { 498 int dir_out = usb_pipeout(pipe); 499 int ep = usb_pipeendpoint(pipe); 500 int devnum = usb_pipedevice(pipe); 501 u8 type; 502 u16 csr; 503 u32 txlen = 0; 504 u32 nextlen = 0; 505 u8 devspeed; 506 507 /* select bulk endpoint */ 508 writeb(MUSB_BULK_EP, &musbr->index); 509 510 /* write the address of the device */ 511 if (dir_out) 512 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); 513 else 514 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); 515 516 /* configure the hub address and the port number as required */ 517 devspeed = get_dev_speed(dev); 518 if ((musb_ishighspeed()) && (dev->parent != NULL) && 519 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 520 /* 521 * MUSB is in high speed and the destination device is full 522 * speed device. So configure the hub address and port 523 * address registers. 524 */ 525 config_hub_port(dev, MUSB_BULK_EP); 526 } else { 527 if (dir_out) { 528 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); 529 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); 530 } else { 531 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); 532 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); 533 } 534 devspeed = musb_cfg.musb_speed; 535 } 536 537 /* Write the saved toggle bit value */ 538 write_toggle(dev, ep, dir_out); 539 540 if (dir_out) { /* bulk-out transfer */ 541 /* Program the TxType register */ 542 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 543 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 544 (ep & MUSB_TYPE_REMOTE_END); 545 writeb(type, &musbr->txtype); 546 547 /* Write maximum packet size to the TxMaxp register */ 548 writew(dev->epmaxpacketout[ep], &musbr->txmaxp); 549 while (txlen < len) { 550 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? 551 (len-txlen) : dev->epmaxpacketout[ep]; 552 553 /* Write the data to the FIFO */ 554 write_fifo(MUSB_BULK_EP, nextlen, 555 (void *)(((u8 *)buffer) + txlen)); 556 557 /* Set the TxPktRdy bit */ 558 csr = readw(&musbr->txcsr); 559 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); 560 561 /* Wait until the TxPktRdy bit is cleared */ 562 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { 563 readw(&musbr->txcsr); 564 usb_settoggle(dev, ep, dir_out, 565 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 566 dev->act_len = txlen; 567 return 0; 568 } 569 txlen += nextlen; 570 } 571 572 /* Keep a copy of the data toggle bit */ 573 csr = readw(&musbr->txcsr); 574 usb_settoggle(dev, ep, dir_out, 575 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 576 } else { /* bulk-in transfer */ 577 /* Write the saved toggle bit value */ 578 write_toggle(dev, ep, dir_out); 579 580 /* Program the RxType register */ 581 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 582 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 583 (ep & MUSB_TYPE_REMOTE_END); 584 writeb(type, &musbr->rxtype); 585 586 /* Write the maximum packet size to the RxMaxp register */ 587 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 588 while (txlen < len) { 589 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 590 (len-txlen) : dev->epmaxpacketin[ep]; 591 592 /* Set the ReqPkt bit */ 593 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 594 595 /* Wait until the RxPktRdy bit is set */ 596 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { 597 csr = readw(&musbr->rxcsr); 598 usb_settoggle(dev, ep, dir_out, 599 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 600 csr &= ~MUSB_RXCSR_RXPKTRDY; 601 writew(csr, &musbr->rxcsr); 602 dev->act_len = txlen; 603 return 0; 604 } 605 606 /* Read the data from the FIFO */ 607 read_fifo(MUSB_BULK_EP, nextlen, 608 (void *)(((u8 *)buffer) + txlen)); 609 610 /* Clear the RxPktRdy bit */ 611 csr = readw(&musbr->rxcsr); 612 csr &= ~MUSB_RXCSR_RXPKTRDY; 613 writew(csr, &musbr->rxcsr); 614 txlen += nextlen; 615 } 616 617 /* Keep a copy of the data toggle bit */ 618 csr = readw(&musbr->rxcsr); 619 usb_settoggle(dev, ep, dir_out, 620 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 621 } 622 623 /* bulk transfer is complete */ 624 dev->status = 0; 625 dev->act_len = len; 626 return 0; 627 } 628 629 /* 630 * This function initializes the usb controller module. 631 */ 632 int usb_lowlevel_init(void) 633 { 634 u8 power; 635 u32 timeout; 636 637 if (musb_platform_init() == -1) 638 return -1; 639 640 /* Configure all the endpoint FIFO's and start usb controller */ 641 musbr = musb_cfg.regs; 642 musb_configure_ep(&epinfo[0], 643 sizeof(epinfo) / sizeof(struct musb_epinfo)); 644 musb_start(); 645 646 /* 647 * Wait until musb is enabled in host mode with a timeout. There 648 * should be a usb device connected. 649 */ 650 timeout = musb_cfg.timeout; 651 while (timeout--) 652 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) 653 break; 654 655 /* if musb core is not in host mode, then return */ 656 if (!timeout) 657 return -1; 658 659 /* start usb bus reset */ 660 power = readb(&musbr->power); 661 writeb(power | MUSB_POWER_RESET, &musbr->power); 662 663 /* After initiating a usb reset, wait for about 20ms to 30ms */ 664 udelay(30000); 665 666 /* stop usb bus reset */ 667 power = readb(&musbr->power); 668 power &= ~MUSB_POWER_RESET; 669 writeb(power, &musbr->power); 670 671 /* Determine if the connected device is a high/full/low speed device */ 672 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? 673 MUSB_TYPE_SPEED_HIGH : 674 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? 675 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); 676 return 0; 677 } 678 679 /* 680 * This function stops the operation of the davinci usb module. 681 */ 682 int usb_lowlevel_stop(void) 683 { 684 /* Reset the USB module */ 685 musb_platform_deinit(); 686 writeb(0, &musbr->devctl); 687 return 0; 688 } 689 690 /* 691 * This function supports usb interrupt transfers. Currently, usb interrupt 692 * transfers are not supported. 693 */ 694 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 695 void *buffer, int len, int interval) 696 { 697 int dir_out = usb_pipeout(pipe); 698 int ep = usb_pipeendpoint(pipe); 699 int devnum = usb_pipedevice(pipe); 700 u8 type; 701 u16 csr; 702 u32 txlen = 0; 703 u32 nextlen = 0; 704 u8 devspeed; 705 706 /* select interrupt endpoint */ 707 writeb(MUSB_INTR_EP, &musbr->index); 708 709 /* write the address of the device */ 710 if (dir_out) 711 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); 712 else 713 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); 714 715 /* configure the hub address and the port number as required */ 716 devspeed = get_dev_speed(dev); 717 if ((musb_ishighspeed()) && (dev->parent != NULL) && 718 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 719 /* 720 * MUSB is in high speed and the destination device is full 721 * speed device. So configure the hub address and port 722 * address registers. 723 */ 724 config_hub_port(dev, MUSB_INTR_EP); 725 } else { 726 if (dir_out) { 727 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); 728 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); 729 } else { 730 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); 731 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); 732 } 733 devspeed = musb_cfg.musb_speed; 734 } 735 736 /* Write the saved toggle bit value */ 737 write_toggle(dev, ep, dir_out); 738 739 if (!dir_out) { /* intrrupt-in transfer */ 740 /* Write the saved toggle bit value */ 741 write_toggle(dev, ep, dir_out); 742 writeb(interval, &musbr->rxinterval); 743 744 /* Program the RxType register */ 745 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 746 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | 747 (ep & MUSB_TYPE_REMOTE_END); 748 writeb(type, &musbr->rxtype); 749 750 /* Write the maximum packet size to the RxMaxp register */ 751 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 752 753 while (txlen < len) { 754 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 755 (len-txlen) : dev->epmaxpacketin[ep]; 756 757 /* Set the ReqPkt bit */ 758 writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 759 760 /* Wait until the RxPktRdy bit is set */ 761 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { 762 csr = readw(&musbr->rxcsr); 763 usb_settoggle(dev, ep, dir_out, 764 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 765 csr &= ~MUSB_RXCSR_RXPKTRDY; 766 writew(csr, &musbr->rxcsr); 767 dev->act_len = txlen; 768 return 0; 769 } 770 771 /* Read the data from the FIFO */ 772 read_fifo(MUSB_INTR_EP, nextlen, 773 (void *)(((u8 *)buffer) + txlen)); 774 775 /* Clear the RxPktRdy bit */ 776 csr = readw(&musbr->rxcsr); 777 csr &= ~MUSB_RXCSR_RXPKTRDY; 778 writew(csr, &musbr->rxcsr); 779 txlen += nextlen; 780 } 781 782 /* Keep a copy of the data toggle bit */ 783 csr = readw(&musbr->rxcsr); 784 usb_settoggle(dev, ep, dir_out, 785 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 786 } 787 788 /* interrupt transfer is complete */ 789 dev->irq_status = 0; 790 dev->irq_act_len = len; 791 dev->irq_handle(dev); 792 dev->status = 0; 793 dev->act_len = len; 794 return 0; 795 } 796 797 798 #ifdef CONFIG_SYS_USB_EVENT_POLL 799 /* 800 * This function polls for USB keyboard data. 801 */ 802 void usb_event_poll() 803 { 804 struct stdio_dev *dev; 805 struct usb_device *usb_kbd_dev; 806 struct usb_interface_descriptor *iface; 807 struct usb_endpoint_descriptor *ep; 808 int pipe; 809 int maxp; 810 811 /* Get the pointer to USB Keyboard device pointer */ 812 dev = stdio_get_by_name("usbkbd"); 813 usb_kbd_dev = (struct usb_device *)dev->priv; 814 iface = &usb_kbd_dev->config.if_desc[0]; 815 ep = &iface->ep_desc[0]; 816 pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); 817 818 /* Submit a interrupt transfer request */ 819 maxp = usb_maxpacket(usb_kbd_dev, pipe); 820 usb_submit_int_msg(usb_kbd_dev, pipe, &new[0], 821 maxp > 8 ? 8 : maxp, ep->bInterval); 822 } 823 #endif /* CONFIG_SYS_USB_EVENT_POLL */ 824