1 /* 2 * Mentor USB OTG Core host controller driver. 3 * 4 * Copyright (c) 2008 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 * 21 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments 22 */ 23 24 #include <common.h> 25 #include "musb_hcd.h" 26 27 /* MSC control transfers */ 28 #define USB_MSC_BBB_RESET 0xFF 29 #define USB_MSC_BBB_GET_MAX_LUN 0xFE 30 31 /* Endpoint configuration information */ 32 static const struct musb_epinfo epinfo[3] = { 33 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ 34 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ 35 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ 36 }; 37 38 /* --- Virtual Root Hub ---------------------------------------------------- */ 39 #ifdef MUSB_NO_MULTIPOINT 40 static int rh_devnum; 41 static u32 port_status; 42 43 /* Device descriptor */ 44 static const u8 root_hub_dev_des[] = { 45 0x12, /* __u8 bLength; */ 46 0x01, /* __u8 bDescriptorType; Device */ 47 0x00, /* __u16 bcdUSB; v1.1 */ 48 0x02, 49 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ 50 0x00, /* __u8 bDeviceSubClass; */ 51 0x00, /* __u8 bDeviceProtocol; */ 52 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ 53 0x00, /* __u16 idVendor; */ 54 0x00, 55 0x00, /* __u16 idProduct; */ 56 0x00, 57 0x00, /* __u16 bcdDevice; */ 58 0x00, 59 0x00, /* __u8 iManufacturer; */ 60 0x01, /* __u8 iProduct; */ 61 0x00, /* __u8 iSerialNumber; */ 62 0x01 /* __u8 bNumConfigurations; */ 63 }; 64 65 /* Configuration descriptor */ 66 static const u8 root_hub_config_des[] = { 67 0x09, /* __u8 bLength; */ 68 0x02, /* __u8 bDescriptorType; Configuration */ 69 0x19, /* __u16 wTotalLength; */ 70 0x00, 71 0x01, /* __u8 bNumInterfaces; */ 72 0x01, /* __u8 bConfigurationValue; */ 73 0x00, /* __u8 iConfiguration; */ 74 0x40, /* __u8 bmAttributes; 75 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ 76 0x00, /* __u8 MaxPower; */ 77 78 /* interface */ 79 0x09, /* __u8 if_bLength; */ 80 0x04, /* __u8 if_bDescriptorType; Interface */ 81 0x00, /* __u8 if_bInterfaceNumber; */ 82 0x00, /* __u8 if_bAlternateSetting; */ 83 0x01, /* __u8 if_bNumEndpoints; */ 84 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ 85 0x00, /* __u8 if_bInterfaceSubClass; */ 86 0x00, /* __u8 if_bInterfaceProtocol; */ 87 0x00, /* __u8 if_iInterface; */ 88 89 /* endpoint */ 90 0x07, /* __u8 ep_bLength; */ 91 0x05, /* __u8 ep_bDescriptorType; Endpoint */ 92 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ 93 0x03, /* __u8 ep_bmAttributes; Interrupt */ 94 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ 95 0x02, 96 0xff /* __u8 ep_bInterval; 255 ms */ 97 }; 98 99 static const unsigned char root_hub_str_index0[] = { 100 0x04, /* __u8 bLength; */ 101 0x03, /* __u8 bDescriptorType; String-descriptor */ 102 0x09, /* __u8 lang ID */ 103 0x04, /* __u8 lang ID */ 104 }; 105 106 static const unsigned char root_hub_str_index1[] = { 107 0x1c, /* __u8 bLength; */ 108 0x03, /* __u8 bDescriptorType; String-descriptor */ 109 'M', /* __u8 Unicode */ 110 0, /* __u8 Unicode */ 111 'U', /* __u8 Unicode */ 112 0, /* __u8 Unicode */ 113 'S', /* __u8 Unicode */ 114 0, /* __u8 Unicode */ 115 'B', /* __u8 Unicode */ 116 0, /* __u8 Unicode */ 117 ' ', /* __u8 Unicode */ 118 0, /* __u8 Unicode */ 119 'R', /* __u8 Unicode */ 120 0, /* __u8 Unicode */ 121 'o', /* __u8 Unicode */ 122 0, /* __u8 Unicode */ 123 'o', /* __u8 Unicode */ 124 0, /* __u8 Unicode */ 125 't', /* __u8 Unicode */ 126 0, /* __u8 Unicode */ 127 ' ', /* __u8 Unicode */ 128 0, /* __u8 Unicode */ 129 'H', /* __u8 Unicode */ 130 0, /* __u8 Unicode */ 131 'u', /* __u8 Unicode */ 132 0, /* __u8 Unicode */ 133 'b', /* __u8 Unicode */ 134 0, /* __u8 Unicode */ 135 }; 136 #endif 137 138 /* 139 * This function writes the data toggle value. 140 */ 141 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) 142 { 143 u16 toggle = usb_gettoggle(dev, ep, dir_out); 144 u16 csr; 145 146 if (dir_out) { 147 csr = readw(&musbr->txcsr); 148 if (!toggle) { 149 if (csr & MUSB_TXCSR_MODE) 150 csr = MUSB_TXCSR_CLRDATATOG; 151 else 152 csr = 0; 153 writew(csr, &musbr->txcsr); 154 } else { 155 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; 156 writew(csr, &musbr->txcsr); 157 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); 158 writew(csr, &musbr->txcsr); 159 } 160 } else { 161 if (!toggle) { 162 csr = readw(&musbr->txcsr); 163 if (csr & MUSB_TXCSR_MODE) 164 csr = MUSB_RXCSR_CLRDATATOG; 165 else 166 csr = 0; 167 writew(csr, &musbr->rxcsr); 168 } else { 169 csr = readw(&musbr->rxcsr); 170 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; 171 writew(csr, &musbr->rxcsr); 172 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); 173 writew(csr, &musbr->rxcsr); 174 } 175 } 176 } 177 178 /* 179 * This function checks if RxStall has occured on the endpoint. If a RxStall 180 * has occured, the RxStall is cleared and 1 is returned. If RxStall has 181 * not occured, 0 is returned. 182 */ 183 static u8 check_stall(u8 ep, u8 dir_out) 184 { 185 u16 csr; 186 187 /* For endpoint 0 */ 188 if (!ep) { 189 csr = readw(&musbr->txcsr); 190 if (csr & MUSB_CSR0_H_RXSTALL) { 191 csr &= ~MUSB_CSR0_H_RXSTALL; 192 writew(csr, &musbr->txcsr); 193 return 1; 194 } 195 } else { /* For non-ep0 */ 196 if (dir_out) { /* is it tx ep */ 197 csr = readw(&musbr->txcsr); 198 if (csr & MUSB_TXCSR_H_RXSTALL) { 199 csr &= ~MUSB_TXCSR_H_RXSTALL; 200 writew(csr, &musbr->txcsr); 201 return 1; 202 } 203 } else { /* is it rx ep */ 204 csr = readw(&musbr->rxcsr); 205 if (csr & MUSB_RXCSR_H_RXSTALL) { 206 csr &= ~MUSB_RXCSR_H_RXSTALL; 207 writew(csr, &musbr->rxcsr); 208 return 1; 209 } 210 } 211 } 212 return 0; 213 } 214 215 /* 216 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout 217 * error and -2 for stall. 218 */ 219 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) 220 { 221 u16 csr; 222 int result = 1; 223 int timeout = CONFIG_MUSB_TIMEOUT; 224 225 while (result > 0) { 226 csr = readw(&musbr->txcsr); 227 if (csr & MUSB_CSR0_H_ERROR) { 228 csr &= ~MUSB_CSR0_H_ERROR; 229 writew(csr, &musbr->txcsr); 230 dev->status = USB_ST_CRC_ERR; 231 result = -1; 232 break; 233 } 234 235 switch (bit_mask) { 236 case MUSB_CSR0_TXPKTRDY: 237 if (!(csr & MUSB_CSR0_TXPKTRDY)) { 238 if (check_stall(MUSB_CONTROL_EP, 0)) { 239 dev->status = USB_ST_STALLED; 240 result = -2; 241 } else 242 result = 0; 243 } 244 break; 245 246 case MUSB_CSR0_RXPKTRDY: 247 if (check_stall(MUSB_CONTROL_EP, 0)) { 248 dev->status = USB_ST_STALLED; 249 result = -2; 250 } else 251 if (csr & MUSB_CSR0_RXPKTRDY) 252 result = 0; 253 break; 254 255 case MUSB_CSR0_H_REQPKT: 256 if (!(csr & MUSB_CSR0_H_REQPKT)) { 257 if (check_stall(MUSB_CONTROL_EP, 0)) { 258 dev->status = USB_ST_STALLED; 259 result = -2; 260 } else 261 result = 0; 262 } 263 break; 264 } 265 266 /* Check the timeout */ 267 if (--timeout) 268 udelay(1); 269 else { 270 dev->status = USB_ST_CRC_ERR; 271 result = -1; 272 break; 273 } 274 } 275 276 return result; 277 } 278 279 /* 280 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. 281 */ 282 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) 283 { 284 u16 csr; 285 int timeout = CONFIG_MUSB_TIMEOUT; 286 287 do { 288 if (check_stall(ep, 1)) { 289 dev->status = USB_ST_STALLED; 290 return 0; 291 } 292 293 csr = readw(&musbr->txcsr); 294 if (csr & MUSB_TXCSR_H_ERROR) { 295 dev->status = USB_ST_CRC_ERR; 296 return 0; 297 } 298 299 /* Check the timeout */ 300 if (--timeout) 301 udelay(1); 302 else { 303 dev->status = USB_ST_CRC_ERR; 304 return -1; 305 } 306 307 } while (csr & MUSB_TXCSR_TXPKTRDY); 308 return 1; 309 } 310 311 /* 312 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. 313 */ 314 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) 315 { 316 u16 csr; 317 int timeout = CONFIG_MUSB_TIMEOUT; 318 319 do { 320 if (check_stall(ep, 0)) { 321 dev->status = USB_ST_STALLED; 322 return 0; 323 } 324 325 csr = readw(&musbr->rxcsr); 326 if (csr & MUSB_RXCSR_H_ERROR) { 327 dev->status = USB_ST_CRC_ERR; 328 return 0; 329 } 330 331 /* Check the timeout */ 332 if (--timeout) 333 udelay(1); 334 else { 335 dev->status = USB_ST_CRC_ERR; 336 return -1; 337 } 338 339 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); 340 return 1; 341 } 342 343 /* 344 * This function performs the setup phase of the control transfer 345 */ 346 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) 347 { 348 int result; 349 u16 csr; 350 351 /* write the control request to ep0 fifo */ 352 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); 353 354 /* enable transfer of setup packet */ 355 csr = readw(&musbr->txcsr); 356 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); 357 writew(csr, &musbr->txcsr); 358 359 /* wait until the setup packet is transmitted */ 360 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 361 dev->act_len = 0; 362 return result; 363 } 364 365 /* 366 * This function handles the control transfer in data phase 367 */ 368 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) 369 { 370 u16 csr; 371 u32 rxlen = 0; 372 u32 nextlen = 0; 373 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 374 u8 *rxbuff = (u8 *)buffer; 375 u8 rxedlength; 376 int result; 377 378 while (rxlen < len) { 379 /* Determine the next read length */ 380 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); 381 382 /* Set the ReqPkt bit */ 383 csr = readw(&musbr->txcsr); 384 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); 385 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); 386 if (result < 0) 387 return result; 388 389 /* Actual number of bytes received by usb */ 390 rxedlength = readb(&musbr->rxcount); 391 392 /* Read the data from the RxFIFO */ 393 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); 394 395 /* Clear the RxPktRdy Bit */ 396 csr = readw(&musbr->txcsr); 397 csr &= ~MUSB_CSR0_RXPKTRDY; 398 writew(csr, &musbr->txcsr); 399 400 /* short packet? */ 401 if (rxedlength != nextlen) { 402 dev->act_len += rxedlength; 403 break; 404 } 405 rxlen += nextlen; 406 dev->act_len = rxlen; 407 } 408 return 0; 409 } 410 411 /* 412 * This function handles the control transfer out data phase 413 */ 414 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) 415 { 416 u16 csr; 417 u32 txlen = 0; 418 u32 nextlen = 0; 419 u8 maxpktsize = (1 << dev->maxpacketsize) * 8; 420 u8 *txbuff = (u8 *)buffer; 421 int result = 0; 422 423 while (txlen < len) { 424 /* Determine the next write length */ 425 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); 426 427 /* Load the data to send in FIFO */ 428 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); 429 430 /* Set TXPKTRDY bit */ 431 csr = readw(&musbr->txcsr); 432 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, 433 &musbr->txcsr); 434 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 435 if (result < 0) 436 break; 437 438 txlen += nextlen; 439 dev->act_len = txlen; 440 } 441 return result; 442 } 443 444 /* 445 * This function handles the control transfer out status phase 446 */ 447 static int ctrlreq_out_status_phase(struct usb_device *dev) 448 { 449 u16 csr; 450 int result; 451 452 /* Set the StatusPkt bit */ 453 csr = readw(&musbr->txcsr); 454 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | 455 MUSB_CSR0_H_STATUSPKT); 456 writew(csr, &musbr->txcsr); 457 458 /* Wait until TXPKTRDY bit is cleared */ 459 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); 460 return result; 461 } 462 463 /* 464 * This function handles the control transfer in status phase 465 */ 466 static int ctrlreq_in_status_phase(struct usb_device *dev) 467 { 468 u16 csr; 469 int result; 470 471 /* Set the StatusPkt bit and ReqPkt bit */ 472 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; 473 writew(csr, &musbr->txcsr); 474 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); 475 476 /* clear StatusPkt bit and RxPktRdy bit */ 477 csr = readw(&musbr->txcsr); 478 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); 479 writew(csr, &musbr->txcsr); 480 return result; 481 } 482 483 /* 484 * determines the speed of the device (High/Full/Slow) 485 */ 486 static u8 get_dev_speed(struct usb_device *dev) 487 { 488 return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : 489 ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : 490 MUSB_TYPE_SPEED_FULL); 491 } 492 493 /* 494 * configure the hub address and the port address. 495 */ 496 static void config_hub_port(struct usb_device *dev, u8 ep) 497 { 498 u8 chid; 499 u8 hub; 500 501 /* Find out the nearest parent which is high speed */ 502 while (dev->parent->parent != NULL) 503 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) 504 dev = dev->parent; 505 else 506 break; 507 508 /* determine the port address at that hub */ 509 hub = dev->parent->devnum; 510 for (chid = 0; chid < USB_MAXCHILDREN; chid++) 511 if (dev->parent->children[chid] == dev) 512 break; 513 514 #ifndef MUSB_NO_MULTIPOINT 515 /* configure the hub address and the port address */ 516 writeb(hub, &musbr->tar[ep].txhubaddr); 517 writeb((chid + 1), &musbr->tar[ep].txhubport); 518 writeb(hub, &musbr->tar[ep].rxhubaddr); 519 writeb((chid + 1), &musbr->tar[ep].rxhubport); 520 #endif 521 } 522 523 #ifdef MUSB_NO_MULTIPOINT 524 525 static void musb_port_reset(int do_reset) 526 { 527 u8 power = readb(&musbr->power); 528 529 if (do_reset) { 530 power &= 0xf0; 531 writeb(power | MUSB_POWER_RESET, &musbr->power); 532 port_status |= USB_PORT_STAT_RESET; 533 port_status &= ~USB_PORT_STAT_ENABLE; 534 udelay(30000); 535 } else { 536 writeb(power & ~MUSB_POWER_RESET, &musbr->power); 537 538 power = readb(&musbr->power); 539 if (power & MUSB_POWER_HSMODE) 540 port_status |= USB_PORT_STAT_HIGH_SPEED; 541 542 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16)); 543 port_status |= USB_PORT_STAT_ENABLE 544 | (USB_PORT_STAT_C_RESET << 16) 545 | (USB_PORT_STAT_C_ENABLE << 16); 546 } 547 } 548 549 /* 550 * root hub control 551 */ 552 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe, 553 void *buffer, int transfer_len, 554 struct devrequest *cmd) 555 { 556 int leni = transfer_len; 557 int len = 0; 558 int stat = 0; 559 u32 datab[4]; 560 const u8 *data_buf = (u8 *) datab; 561 u16 bmRType_bReq; 562 u16 wValue; 563 u16 wIndex; 564 u16 wLength; 565 u16 int_usb; 566 567 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { 568 debug("Root-Hub submit IRQ: NOT implemented\n"); 569 return 0; 570 } 571 572 bmRType_bReq = cmd->requesttype | (cmd->request << 8); 573 wValue = swap_16(cmd->value); 574 wIndex = swap_16(cmd->index); 575 wLength = swap_16(cmd->length); 576 577 debug("--- HUB ----------------------------------------\n"); 578 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n", 579 bmRType_bReq, wValue, wIndex, wLength); 580 debug("------------------------------------------------\n"); 581 582 switch (bmRType_bReq) { 583 case RH_GET_STATUS: 584 debug("RH_GET_STATUS\n"); 585 586 *(__u16 *) data_buf = swap_16(1); 587 len = 2; 588 break; 589 590 case RH_GET_STATUS | RH_INTERFACE: 591 debug("RH_GET_STATUS | RH_INTERFACE\n"); 592 593 *(__u16 *) data_buf = swap_16(0); 594 len = 2; 595 break; 596 597 case RH_GET_STATUS | RH_ENDPOINT: 598 debug("RH_GET_STATUS | RH_ENDPOINT\n"); 599 600 *(__u16 *) data_buf = swap_16(0); 601 len = 2; 602 break; 603 604 case RH_GET_STATUS | RH_CLASS: 605 debug("RH_GET_STATUS | RH_CLASS\n"); 606 607 *(__u32 *) data_buf = swap_32(0); 608 len = 4; 609 break; 610 611 case RH_GET_STATUS | RH_OTHER | RH_CLASS: 612 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n"); 613 614 int_usb = readw(&musbr->intrusb); 615 if (int_usb & MUSB_INTR_CONNECT) { 616 port_status |= USB_PORT_STAT_CONNECTION 617 | (USB_PORT_STAT_C_CONNECTION << 16); 618 port_status |= USB_PORT_STAT_HIGH_SPEED 619 | USB_PORT_STAT_ENABLE; 620 } 621 622 if (port_status & USB_PORT_STAT_RESET) 623 musb_port_reset(0); 624 625 *(__u32 *) data_buf = swap_32(port_status); 626 len = 4; 627 break; 628 629 case RH_CLEAR_FEATURE | RH_ENDPOINT: 630 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n"); 631 632 switch (wValue) { 633 case RH_ENDPOINT_STALL: 634 debug("C_HUB_ENDPOINT_STALL\n"); 635 len = 0; 636 break; 637 } 638 port_status &= ~(1 << wValue); 639 break; 640 641 case RH_CLEAR_FEATURE | RH_CLASS: 642 debug("RH_CLEAR_FEATURE | RH_CLASS\n"); 643 644 switch (wValue) { 645 case RH_C_HUB_LOCAL_POWER: 646 debug("C_HUB_LOCAL_POWER\n"); 647 len = 0; 648 break; 649 650 case RH_C_HUB_OVER_CURRENT: 651 debug("C_HUB_OVER_CURRENT\n"); 652 len = 0; 653 break; 654 } 655 port_status &= ~(1 << wValue); 656 break; 657 658 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: 659 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n"); 660 661 switch (wValue) { 662 case RH_PORT_ENABLE: 663 len = 0; 664 break; 665 666 case RH_PORT_SUSPEND: 667 len = 0; 668 break; 669 670 case RH_PORT_POWER: 671 len = 0; 672 break; 673 674 case RH_C_PORT_CONNECTION: 675 len = 0; 676 break; 677 678 case RH_C_PORT_ENABLE: 679 len = 0; 680 break; 681 682 case RH_C_PORT_SUSPEND: 683 len = 0; 684 break; 685 686 case RH_C_PORT_OVER_CURRENT: 687 len = 0; 688 break; 689 690 case RH_C_PORT_RESET: 691 len = 0; 692 break; 693 694 default: 695 debug("invalid wValue\n"); 696 stat = USB_ST_STALLED; 697 } 698 699 port_status &= ~(1 << wValue); 700 break; 701 702 case RH_SET_FEATURE | RH_OTHER | RH_CLASS: 703 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n"); 704 705 switch (wValue) { 706 case RH_PORT_SUSPEND: 707 len = 0; 708 break; 709 710 case RH_PORT_RESET: 711 musb_port_reset(1); 712 len = 0; 713 break; 714 715 case RH_PORT_POWER: 716 len = 0; 717 break; 718 719 case RH_PORT_ENABLE: 720 len = 0; 721 break; 722 723 default: 724 debug("invalid wValue\n"); 725 stat = USB_ST_STALLED; 726 } 727 728 port_status |= 1 << wValue; 729 break; 730 731 case RH_SET_ADDRESS: 732 debug("RH_SET_ADDRESS\n"); 733 734 rh_devnum = wValue; 735 len = 0; 736 break; 737 738 case RH_GET_DESCRIPTOR: 739 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength); 740 741 switch (wValue) { 742 case (USB_DT_DEVICE << 8): /* device descriptor */ 743 len = min_t(unsigned int, 744 leni, min_t(unsigned int, 745 sizeof(root_hub_dev_des), 746 wLength)); 747 data_buf = root_hub_dev_des; 748 break; 749 750 case (USB_DT_CONFIG << 8): /* configuration descriptor */ 751 len = min_t(unsigned int, 752 leni, min_t(unsigned int, 753 sizeof(root_hub_config_des), 754 wLength)); 755 data_buf = root_hub_config_des; 756 break; 757 758 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */ 759 len = min_t(unsigned int, 760 leni, min_t(unsigned int, 761 sizeof(root_hub_str_index0), 762 wLength)); 763 data_buf = root_hub_str_index0; 764 break; 765 766 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */ 767 len = min_t(unsigned int, 768 leni, min_t(unsigned int, 769 sizeof(root_hub_str_index1), 770 wLength)); 771 data_buf = root_hub_str_index1; 772 break; 773 774 default: 775 debug("invalid wValue\n"); 776 stat = USB_ST_STALLED; 777 } 778 779 break; 780 781 case RH_GET_DESCRIPTOR | RH_CLASS: { 782 u8 *_data_buf = (u8 *) datab; 783 debug("RH_GET_DESCRIPTOR | RH_CLASS\n"); 784 785 _data_buf[0] = 0x09; /* min length; */ 786 _data_buf[1] = 0x29; 787 _data_buf[2] = 0x1; /* 1 port */ 788 _data_buf[3] = 0x01; /* per-port power switching */ 789 _data_buf[3] |= 0x10; /* no overcurrent reporting */ 790 791 /* Corresponds to data_buf[4-7] */ 792 _data_buf[4] = 0; 793 _data_buf[5] = 5; 794 _data_buf[6] = 0; 795 _data_buf[7] = 0x02; 796 _data_buf[8] = 0xff; 797 798 len = min_t(unsigned int, leni, 799 min_t(unsigned int, data_buf[0], wLength)); 800 break; 801 } 802 803 case RH_GET_CONFIGURATION: 804 debug("RH_GET_CONFIGURATION\n"); 805 806 *(__u8 *) data_buf = 0x01; 807 len = 1; 808 break; 809 810 case RH_SET_CONFIGURATION: 811 debug("RH_SET_CONFIGURATION\n"); 812 813 len = 0; 814 break; 815 816 default: 817 debug("*** *** *** unsupported root hub command *** *** ***\n"); 818 stat = USB_ST_STALLED; 819 } 820 821 len = min_t(int, len, leni); 822 if (buffer != data_buf) 823 memcpy(buffer, data_buf, len); 824 825 dev->act_len = len; 826 dev->status = stat; 827 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status); 828 829 return stat; 830 } 831 832 static void musb_rh_init(void) 833 { 834 rh_devnum = 0; 835 port_status = 0; 836 } 837 838 #else 839 840 static void musb_rh_init(void) {} 841 842 #endif 843 844 /* 845 * do a control transfer 846 */ 847 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, 848 int len, struct devrequest *setup) 849 { 850 int devnum = usb_pipedevice(pipe); 851 u8 devspeed; 852 853 #ifdef MUSB_NO_MULTIPOINT 854 /* Control message is for the HUB? */ 855 if (devnum == rh_devnum) { 856 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup); 857 if (stat) 858 return stat; 859 } 860 #endif 861 862 /* select control endpoint */ 863 writeb(MUSB_CONTROL_EP, &musbr->index); 864 readw(&musbr->txcsr); 865 866 #ifndef MUSB_NO_MULTIPOINT 867 /* target addr and (for multipoint) hub addr/port */ 868 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); 869 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); 870 #endif 871 872 /* configure the hub address and the port number as required */ 873 devspeed = get_dev_speed(dev); 874 if ((musb_ishighspeed()) && (dev->parent != NULL) && 875 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 876 config_hub_port(dev, MUSB_CONTROL_EP); 877 writeb(devspeed << 6, &musbr->txtype); 878 } else { 879 writeb(musb_cfg.musb_speed << 6, &musbr->txtype); 880 #ifndef MUSB_NO_MULTIPOINT 881 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); 882 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); 883 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); 884 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); 885 #endif 886 } 887 888 /* Control transfer setup phase */ 889 if (ctrlreq_setup_phase(dev, setup) < 0) 890 return 0; 891 892 switch (setup->request) { 893 case USB_REQ_GET_DESCRIPTOR: 894 case USB_REQ_GET_CONFIGURATION: 895 case USB_REQ_GET_INTERFACE: 896 case USB_REQ_GET_STATUS: 897 case USB_MSC_BBB_GET_MAX_LUN: 898 /* control transfer in-data-phase */ 899 if (ctrlreq_in_data_phase(dev, len, buffer) < 0) 900 return 0; 901 /* control transfer out-status-phase */ 902 if (ctrlreq_out_status_phase(dev) < 0) 903 return 0; 904 break; 905 906 case USB_REQ_SET_ADDRESS: 907 case USB_REQ_SET_CONFIGURATION: 908 case USB_REQ_SET_FEATURE: 909 case USB_REQ_SET_INTERFACE: 910 case USB_REQ_CLEAR_FEATURE: 911 case USB_MSC_BBB_RESET: 912 /* control transfer in status phase */ 913 if (ctrlreq_in_status_phase(dev) < 0) 914 return 0; 915 break; 916 917 case USB_REQ_SET_DESCRIPTOR: 918 /* control transfer out data phase */ 919 if (ctrlreq_out_data_phase(dev, len, buffer) < 0) 920 return 0; 921 /* control transfer in status phase */ 922 if (ctrlreq_in_status_phase(dev) < 0) 923 return 0; 924 break; 925 926 default: 927 /* unhandled control transfer */ 928 return -1; 929 } 930 931 dev->status = 0; 932 dev->act_len = len; 933 934 #ifdef MUSB_NO_MULTIPOINT 935 /* Set device address to USB_FADDR register */ 936 if (setup->request == USB_REQ_SET_ADDRESS) 937 writeb(dev->devnum, &musbr->faddr); 938 #endif 939 940 return len; 941 } 942 943 /* 944 * do a bulk transfer 945 */ 946 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, 947 void *buffer, int len) 948 { 949 int dir_out = usb_pipeout(pipe); 950 int ep = usb_pipeendpoint(pipe); 951 #ifndef MUSB_NO_MULTIPOINT 952 int devnum = usb_pipedevice(pipe); 953 #endif 954 u8 type; 955 u16 csr; 956 u32 txlen = 0; 957 u32 nextlen = 0; 958 u8 devspeed; 959 960 /* select bulk endpoint */ 961 writeb(MUSB_BULK_EP, &musbr->index); 962 963 #ifndef MUSB_NO_MULTIPOINT 964 /* write the address of the device */ 965 if (dir_out) 966 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); 967 else 968 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); 969 #endif 970 971 /* configure the hub address and the port number as required */ 972 devspeed = get_dev_speed(dev); 973 if ((musb_ishighspeed()) && (dev->parent != NULL) && 974 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 975 /* 976 * MUSB is in high speed and the destination device is full 977 * speed device. So configure the hub address and port 978 * address registers. 979 */ 980 config_hub_port(dev, MUSB_BULK_EP); 981 } else { 982 #ifndef MUSB_NO_MULTIPOINT 983 if (dir_out) { 984 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); 985 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); 986 } else { 987 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); 988 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); 989 } 990 #endif 991 devspeed = musb_cfg.musb_speed; 992 } 993 994 /* Write the saved toggle bit value */ 995 write_toggle(dev, ep, dir_out); 996 997 if (dir_out) { /* bulk-out transfer */ 998 /* Program the TxType register */ 999 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 1000 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 1001 (ep & MUSB_TYPE_REMOTE_END); 1002 writeb(type, &musbr->txtype); 1003 1004 /* Write maximum packet size to the TxMaxp register */ 1005 writew(dev->epmaxpacketout[ep], &musbr->txmaxp); 1006 while (txlen < len) { 1007 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? 1008 (len-txlen) : dev->epmaxpacketout[ep]; 1009 1010 #ifdef CONFIG_USB_BLACKFIN 1011 /* Set the transfer data size */ 1012 writew(nextlen, &musbr->txcount); 1013 #endif 1014 1015 /* Write the data to the FIFO */ 1016 write_fifo(MUSB_BULK_EP, nextlen, 1017 (void *)(((u8 *)buffer) + txlen)); 1018 1019 /* Set the TxPktRdy bit */ 1020 csr = readw(&musbr->txcsr); 1021 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); 1022 1023 /* Wait until the TxPktRdy bit is cleared */ 1024 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { 1025 readw(&musbr->txcsr); 1026 usb_settoggle(dev, ep, dir_out, 1027 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 1028 dev->act_len = txlen; 1029 return 0; 1030 } 1031 txlen += nextlen; 1032 } 1033 1034 /* Keep a copy of the data toggle bit */ 1035 csr = readw(&musbr->txcsr); 1036 usb_settoggle(dev, ep, dir_out, 1037 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); 1038 } else { /* bulk-in transfer */ 1039 /* Write the saved toggle bit value */ 1040 write_toggle(dev, ep, dir_out); 1041 1042 /* Program the RxType register */ 1043 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 1044 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | 1045 (ep & MUSB_TYPE_REMOTE_END); 1046 writeb(type, &musbr->rxtype); 1047 1048 /* Write the maximum packet size to the RxMaxp register */ 1049 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 1050 while (txlen < len) { 1051 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 1052 (len-txlen) : dev->epmaxpacketin[ep]; 1053 1054 /* Set the ReqPkt bit */ 1055 csr = readw(&musbr->rxcsr); 1056 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 1057 1058 /* Wait until the RxPktRdy bit is set */ 1059 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { 1060 csr = readw(&musbr->rxcsr); 1061 usb_settoggle(dev, ep, dir_out, 1062 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 1063 csr &= ~MUSB_RXCSR_RXPKTRDY; 1064 writew(csr, &musbr->rxcsr); 1065 dev->act_len = txlen; 1066 return 0; 1067 } 1068 1069 /* Read the data from the FIFO */ 1070 read_fifo(MUSB_BULK_EP, nextlen, 1071 (void *)(((u8 *)buffer) + txlen)); 1072 1073 /* Clear the RxPktRdy bit */ 1074 csr = readw(&musbr->rxcsr); 1075 csr &= ~MUSB_RXCSR_RXPKTRDY; 1076 writew(csr, &musbr->rxcsr); 1077 txlen += nextlen; 1078 } 1079 1080 /* Keep a copy of the data toggle bit */ 1081 csr = readw(&musbr->rxcsr); 1082 usb_settoggle(dev, ep, dir_out, 1083 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 1084 } 1085 1086 /* bulk transfer is complete */ 1087 dev->status = 0; 1088 dev->act_len = len; 1089 return 0; 1090 } 1091 1092 /* 1093 * This function initializes the usb controller module. 1094 */ 1095 int usb_lowlevel_init(void) 1096 { 1097 u8 power; 1098 u32 timeout; 1099 1100 musb_rh_init(); 1101 1102 if (musb_platform_init() == -1) 1103 return -1; 1104 1105 /* Configure all the endpoint FIFO's and start usb controller */ 1106 musbr = musb_cfg.regs; 1107 musb_configure_ep(&epinfo[0], 1108 sizeof(epinfo) / sizeof(struct musb_epinfo)); 1109 musb_start(); 1110 1111 /* 1112 * Wait until musb is enabled in host mode with a timeout. There 1113 * should be a usb device connected. 1114 */ 1115 timeout = musb_cfg.timeout; 1116 while (timeout--) 1117 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) 1118 break; 1119 1120 /* if musb core is not in host mode, then return */ 1121 if (!timeout) 1122 return -1; 1123 1124 /* start usb bus reset */ 1125 power = readb(&musbr->power); 1126 writeb(power | MUSB_POWER_RESET, &musbr->power); 1127 1128 /* After initiating a usb reset, wait for about 20ms to 30ms */ 1129 udelay(30000); 1130 1131 /* stop usb bus reset */ 1132 power = readb(&musbr->power); 1133 power &= ~MUSB_POWER_RESET; 1134 writeb(power, &musbr->power); 1135 1136 /* Determine if the connected device is a high/full/low speed device */ 1137 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? 1138 MUSB_TYPE_SPEED_HIGH : 1139 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? 1140 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); 1141 return 0; 1142 } 1143 1144 /* 1145 * This function stops the operation of the davinci usb module. 1146 */ 1147 int usb_lowlevel_stop(void) 1148 { 1149 /* Reset the USB module */ 1150 musb_platform_deinit(); 1151 writeb(0, &musbr->devctl); 1152 return 0; 1153 } 1154 1155 /* 1156 * This function supports usb interrupt transfers. Currently, usb interrupt 1157 * transfers are not supported. 1158 */ 1159 int submit_int_msg(struct usb_device *dev, unsigned long pipe, 1160 void *buffer, int len, int interval) 1161 { 1162 int dir_out = usb_pipeout(pipe); 1163 int ep = usb_pipeendpoint(pipe); 1164 #ifndef MUSB_NO_MULTIPOINT 1165 int devnum = usb_pipedevice(pipe); 1166 #endif 1167 u8 type; 1168 u16 csr; 1169 u32 txlen = 0; 1170 u32 nextlen = 0; 1171 u8 devspeed; 1172 1173 /* select interrupt endpoint */ 1174 writeb(MUSB_INTR_EP, &musbr->index); 1175 1176 #ifndef MUSB_NO_MULTIPOINT 1177 /* write the address of the device */ 1178 if (dir_out) 1179 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); 1180 else 1181 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); 1182 #endif 1183 1184 /* configure the hub address and the port number as required */ 1185 devspeed = get_dev_speed(dev); 1186 if ((musb_ishighspeed()) && (dev->parent != NULL) && 1187 (devspeed != MUSB_TYPE_SPEED_HIGH)) { 1188 /* 1189 * MUSB is in high speed and the destination device is full 1190 * speed device. So configure the hub address and port 1191 * address registers. 1192 */ 1193 config_hub_port(dev, MUSB_INTR_EP); 1194 } else { 1195 #ifndef MUSB_NO_MULTIPOINT 1196 if (dir_out) { 1197 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); 1198 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); 1199 } else { 1200 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); 1201 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); 1202 } 1203 #endif 1204 devspeed = musb_cfg.musb_speed; 1205 } 1206 1207 /* Write the saved toggle bit value */ 1208 write_toggle(dev, ep, dir_out); 1209 1210 if (!dir_out) { /* intrrupt-in transfer */ 1211 /* Write the saved toggle bit value */ 1212 write_toggle(dev, ep, dir_out); 1213 writeb(interval, &musbr->rxinterval); 1214 1215 /* Program the RxType register */ 1216 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | 1217 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | 1218 (ep & MUSB_TYPE_REMOTE_END); 1219 writeb(type, &musbr->rxtype); 1220 1221 /* Write the maximum packet size to the RxMaxp register */ 1222 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); 1223 1224 while (txlen < len) { 1225 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? 1226 (len-txlen) : dev->epmaxpacketin[ep]; 1227 1228 /* Set the ReqPkt bit */ 1229 csr = readw(&musbr->rxcsr); 1230 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); 1231 1232 /* Wait until the RxPktRdy bit is set */ 1233 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { 1234 csr = readw(&musbr->rxcsr); 1235 usb_settoggle(dev, ep, dir_out, 1236 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 1237 csr &= ~MUSB_RXCSR_RXPKTRDY; 1238 writew(csr, &musbr->rxcsr); 1239 dev->act_len = txlen; 1240 return 0; 1241 } 1242 1243 /* Read the data from the FIFO */ 1244 read_fifo(MUSB_INTR_EP, nextlen, 1245 (void *)(((u8 *)buffer) + txlen)); 1246 1247 /* Clear the RxPktRdy bit */ 1248 csr = readw(&musbr->rxcsr); 1249 csr &= ~MUSB_RXCSR_RXPKTRDY; 1250 writew(csr, &musbr->rxcsr); 1251 txlen += nextlen; 1252 } 1253 1254 /* Keep a copy of the data toggle bit */ 1255 csr = readw(&musbr->rxcsr); 1256 usb_settoggle(dev, ep, dir_out, 1257 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); 1258 } 1259 1260 /* interrupt transfer is complete */ 1261 dev->irq_status = 0; 1262 dev->irq_act_len = len; 1263 dev->irq_handle(dev); 1264 dev->status = 0; 1265 dev->act_len = len; 1266 return 0; 1267 } 1268