1 /****************************************************************** 2 * Copyright 2008 Mentor Graphics Corporation 3 * Copyright (C) 2008 by Texas Instruments 4 * 5 * This file is part of the Inventra Controller Driver for Linux. 6 * 7 * The Inventra Controller Driver for Linux is free software; you 8 * can redistribute it and/or modify it under the terms of the GNU 9 * General Public License version 2 as published by the Free Software 10 * Foundation. 11 * 12 * The Inventra Controller Driver for Linux is distributed in 13 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 14 * without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 * License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with The Inventra Controller Driver for Linux ; if not, 20 * write to the Free Software Foundation, Inc., 59 Temple Place, 21 * Suite 330, Boston, MA 02111-1307 USA 22 * 23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION 24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE 25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS 26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. 27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES 28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND 29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT 30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR 31 * GRAPHICS SUPPORT CUSTOMER. 32 ******************************************************************/ 33 34 #ifndef __MUSB_HDRC_DEFS_H__ 35 #define __MUSB_HDRC_DEFS_H__ 36 37 #include <usb.h> 38 #include <usb_defs.h> 39 #include <asm/io.h> 40 41 #ifdef CONFIG_USB_BLACKFIN 42 # include "blackfin_usb.h" 43 #endif 44 45 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 46 47 /* EP0 */ 48 struct musb_ep0_regs { 49 u16 reserved4; 50 u16 csr0; 51 u16 reserved5; 52 u16 reserved6; 53 u16 count0; 54 u8 host_type0; 55 u8 host_naklimit0; 56 u8 reserved7; 57 u8 reserved8; 58 u8 reserved9; 59 u8 configdata; 60 }; 61 62 /* EP 1-15 */ 63 struct musb_epN_regs { 64 u16 txmaxp; 65 u16 txcsr; 66 u16 rxmaxp; 67 u16 rxcsr; 68 u16 rxcount; 69 u8 txtype; 70 u8 txinterval; 71 u8 rxtype; 72 u8 rxinterval; 73 u8 reserved0; 74 u8 fifosize; 75 }; 76 77 /* Mentor USB core register overlay structure */ 78 #ifndef musb_regs 79 struct musb_regs { 80 /* common registers */ 81 u8 faddr; 82 u8 power; 83 u16 intrtx; 84 u16 intrrx; 85 u16 intrtxe; 86 u16 intrrxe; 87 u8 intrusb; 88 u8 intrusbe; 89 u16 frame; 90 u8 index; 91 u8 testmode; 92 /* indexed registers */ 93 u16 txmaxp; 94 u16 txcsr; 95 u16 rxmaxp; 96 u16 rxcsr; 97 u16 rxcount; 98 u8 txtype; 99 u8 txinterval; 100 u8 rxtype; 101 u8 rxinterval; 102 u8 reserved0; 103 u8 fifosize; 104 /* fifo */ 105 u32 fifox[16]; 106 /* OTG, dynamic FIFO, version & vendor registers */ 107 u8 devctl; 108 u8 reserved1; 109 u8 txfifosz; 110 u8 rxfifosz; 111 u16 txfifoadd; 112 u16 rxfifoadd; 113 u32 vcontrol; 114 u16 hwvers; 115 u16 reserved2a[1]; 116 u8 ulpi_busctl; 117 u8 reserved2b[1]; 118 u16 reserved2[3]; 119 u8 epinfo; 120 u8 raminfo; 121 u8 linkinfo; 122 u8 vplen; 123 u8 hseof1; 124 u8 fseof1; 125 u8 lseof1; 126 u8 reserved3; 127 /* target address registers */ 128 struct musb_tar_regs { 129 u8 txfuncaddr; 130 u8 reserved0; 131 u8 txhubaddr; 132 u8 txhubport; 133 u8 rxfuncaddr; 134 u8 reserved1; 135 u8 rxhubaddr; 136 u8 rxhubport; 137 } tar[16]; 138 /* 139 * endpoint registers 140 * ep0 elements are valid when array index is 0 141 * otherwise epN is valid 142 */ 143 union musb_ep_regs { 144 struct musb_ep0_regs ep0; 145 struct musb_epN_regs epN; 146 } ep[16]; 147 148 } __attribute__((packed, aligned(USB_DMA_MINALIGN))); 149 #endif 150 151 /* 152 * MUSB Register bits 153 */ 154 155 /* POWER */ 156 #define MUSB_POWER_ISOUPDATE 0x80 157 #define MUSB_POWER_SOFTCONN 0x40 158 #define MUSB_POWER_HSENAB 0x20 159 #define MUSB_POWER_HSMODE 0x10 160 #define MUSB_POWER_RESET 0x08 161 #define MUSB_POWER_RESUME 0x04 162 #define MUSB_POWER_SUSPENDM 0x02 163 #define MUSB_POWER_ENSUSPEND 0x01 164 #define MUSB_POWER_HSMODE_SHIFT 4 165 166 /* INTRUSB */ 167 #define MUSB_INTR_SUSPEND 0x01 168 #define MUSB_INTR_RESUME 0x02 169 #define MUSB_INTR_RESET 0x04 170 #define MUSB_INTR_BABBLE 0x04 171 #define MUSB_INTR_SOF 0x08 172 #define MUSB_INTR_CONNECT 0x10 173 #define MUSB_INTR_DISCONNECT 0x20 174 #define MUSB_INTR_SESSREQ 0x40 175 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 176 177 /* DEVCTL */ 178 #define MUSB_DEVCTL_BDEVICE 0x80 179 #define MUSB_DEVCTL_FSDEV 0x40 180 #define MUSB_DEVCTL_LSDEV 0x20 181 #define MUSB_DEVCTL_VBUS 0x18 182 #define MUSB_DEVCTL_VBUS_SHIFT 3 183 #define MUSB_DEVCTL_HM 0x04 184 #define MUSB_DEVCTL_HR 0x02 185 #define MUSB_DEVCTL_SESSION 0x01 186 187 /* ULPI VBUSCONTROL */ 188 #define ULPI_USE_EXTVBUS 0x01 189 #define ULPI_USE_EXTVBUSIND 0x02 190 191 /* TESTMODE */ 192 #define MUSB_TEST_FORCE_HOST 0x80 193 #define MUSB_TEST_FIFO_ACCESS 0x40 194 #define MUSB_TEST_FORCE_FS 0x20 195 #define MUSB_TEST_FORCE_HS 0x10 196 #define MUSB_TEST_PACKET 0x08 197 #define MUSB_TEST_K 0x04 198 #define MUSB_TEST_J 0x02 199 #define MUSB_TEST_SE0_NAK 0x01 200 201 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 202 #define MUSB_FIFOSZ_DPB 0x10 203 /* Allocation size (8, 16, 32, ... 4096) */ 204 #define MUSB_FIFOSZ_SIZE 0x0f 205 206 /* CSR0 */ 207 #define MUSB_CSR0_FLUSHFIFO 0x0100 208 #define MUSB_CSR0_TXPKTRDY 0x0002 209 #define MUSB_CSR0_RXPKTRDY 0x0001 210 211 /* CSR0 in Peripheral mode */ 212 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 213 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 214 #define MUSB_CSR0_P_SENDSTALL 0x0020 215 #define MUSB_CSR0_P_SETUPEND 0x0010 216 #define MUSB_CSR0_P_DATAEND 0x0008 217 #define MUSB_CSR0_P_SENTSTALL 0x0004 218 219 /* CSR0 in Host mode */ 220 #define MUSB_CSR0_H_DIS_PING 0x0800 221 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 222 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 223 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 224 #define MUSB_CSR0_H_STATUSPKT 0x0040 225 #define MUSB_CSR0_H_REQPKT 0x0020 226 #define MUSB_CSR0_H_ERROR 0x0010 227 #define MUSB_CSR0_H_SETUPPKT 0x0008 228 #define MUSB_CSR0_H_RXSTALL 0x0004 229 230 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 231 #define MUSB_CSR0_P_WZC_BITS \ 232 (MUSB_CSR0_P_SENTSTALL) 233 #define MUSB_CSR0_H_WZC_BITS \ 234 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 235 | MUSB_CSR0_RXPKTRDY) 236 237 /* TxType/RxType */ 238 #define MUSB_TYPE_SPEED 0xc0 239 #define MUSB_TYPE_SPEED_SHIFT 6 240 #define MUSB_TYPE_SPEED_HIGH 1 241 #define MUSB_TYPE_SPEED_FULL 2 242 #define MUSB_TYPE_SPEED_LOW 3 243 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 244 #define MUSB_TYPE_PROTO_SHIFT 4 245 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 246 #define MUSB_TYPE_PROTO_BULK 2 247 #define MUSB_TYPE_PROTO_INTR 3 248 249 /* CONFIGDATA */ 250 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 251 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 252 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 253 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 254 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 255 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 256 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 257 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 258 259 /* TXCSR in Peripheral and Host mode */ 260 #define MUSB_TXCSR_AUTOSET 0x8000 261 #define MUSB_TXCSR_MODE 0x2000 262 #define MUSB_TXCSR_DMAENAB 0x1000 263 #define MUSB_TXCSR_FRCDATATOG 0x0800 264 #define MUSB_TXCSR_DMAMODE 0x0400 265 #define MUSB_TXCSR_CLRDATATOG 0x0040 266 #define MUSB_TXCSR_FLUSHFIFO 0x0008 267 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 268 #define MUSB_TXCSR_TXPKTRDY 0x0001 269 270 /* TXCSR in Peripheral mode */ 271 #define MUSB_TXCSR_P_ISO 0x4000 272 #define MUSB_TXCSR_P_INCOMPTX 0x0080 273 #define MUSB_TXCSR_P_SENTSTALL 0x0020 274 #define MUSB_TXCSR_P_SENDSTALL 0x0010 275 #define MUSB_TXCSR_P_UNDERRUN 0x0004 276 277 /* TXCSR in Host mode */ 278 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 279 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 280 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 281 #define MUSB_TXCSR_H_RXSTALL 0x0020 282 #define MUSB_TXCSR_H_ERROR 0x0004 283 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 284 285 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 286 #define MUSB_TXCSR_P_WZC_BITS \ 287 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 288 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 289 #define MUSB_TXCSR_H_WZC_BITS \ 290 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 291 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 292 293 /* RXCSR in Peripheral and Host mode */ 294 #define MUSB_RXCSR_AUTOCLEAR 0x8000 295 #define MUSB_RXCSR_DMAENAB 0x2000 296 #define MUSB_RXCSR_DISNYET 0x1000 297 #define MUSB_RXCSR_PID_ERR 0x1000 298 #define MUSB_RXCSR_DMAMODE 0x0800 299 #define MUSB_RXCSR_INCOMPRX 0x0100 300 #define MUSB_RXCSR_CLRDATATOG 0x0080 301 #define MUSB_RXCSR_FLUSHFIFO 0x0010 302 #define MUSB_RXCSR_DATAERROR 0x0008 303 #define MUSB_RXCSR_FIFOFULL 0x0002 304 #define MUSB_RXCSR_RXPKTRDY 0x0001 305 306 /* RXCSR in Peripheral mode */ 307 #define MUSB_RXCSR_P_ISO 0x4000 308 #define MUSB_RXCSR_P_SENTSTALL 0x0040 309 #define MUSB_RXCSR_P_SENDSTALL 0x0020 310 #define MUSB_RXCSR_P_OVERRUN 0x0004 311 312 /* RXCSR in Host mode */ 313 #define MUSB_RXCSR_H_AUTOREQ 0x4000 314 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 315 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 316 #define MUSB_RXCSR_H_RXSTALL 0x0040 317 #define MUSB_RXCSR_H_REQPKT 0x0020 318 #define MUSB_RXCSR_H_ERROR 0x0004 319 #define MUSB_S_RXCSR_H_DATATOGGLE 9 320 321 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 322 #define MUSB_RXCSR_P_WZC_BITS \ 323 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 324 | MUSB_RXCSR_RXPKTRDY) 325 #define MUSB_RXCSR_H_WZC_BITS \ 326 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 327 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 328 329 /* HUBADDR */ 330 #define MUSB_HUBADDR_MULTI_TT 0x80 331 332 /* Endpoint configuration information. Note: The value of endpoint fifo size 333 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other 334 * values are not supported 335 */ 336 struct musb_epinfo { 337 u8 epnum; /* endpoint number */ 338 u8 epdir; /* endpoint direction */ 339 u16 epsize; /* endpoint FIFO size */ 340 }; 341 342 /* 343 * Platform specific MUSB configuration. Any platform using the musb 344 * functionality should create one instance of this structure in the 345 * platform specific file. 346 */ 347 struct musb_config { 348 struct musb_regs *regs; 349 u32 timeout; 350 u8 musb_speed; 351 u8 extvbus; 352 }; 353 354 /* externally defined data */ 355 extern struct musb_config musb_cfg; 356 extern struct musb_regs *musbr; 357 358 /* exported functions */ 359 extern void musb_start(void); 360 extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt); 361 extern void write_fifo(u8 ep, u32 length, void *fifo_data); 362 extern void read_fifo(u8 ep, u32 length, void *fifo_data); 363 364 #if defined(CONFIG_USB_BLACKFIN) 365 /* Every USB register is accessed as a 16-bit even if the value itself 366 * is only 8-bits in size. Fun stuff. 367 */ 368 # undef readb 369 # define readb(addr) (u8)bfin_read16(addr) 370 # undef writeb 371 # define writeb(b, addr) bfin_write16(addr, b) 372 # undef MUSB_TXCSR_MODE /* not supported */ 373 # define MUSB_TXCSR_MODE 0 374 /* 375 * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY. 376 * However, it has no ULPI support - so there are no registers at all. 377 * That means accesses to ULPI_BUSCONTROL have to be abstracted away. 378 */ 379 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr) 380 { 381 return 0; 382 } 383 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val) 384 {} 385 #else 386 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr) 387 { 388 return readb(&musbr->ulpi_busctl); 389 } 390 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val) 391 { 392 writeb(val, &musbr->ulpi_busctl); 393 } 394 #endif 395 396 #endif /* __MUSB_HDRC_DEFS_H__ */ 397