1 /****************************************************************** 2 * Copyright 2008 Mentor Graphics Corporation 3 * Copyright (C) 2008 by Texas Instruments 4 * 5 * This file is part of the Inventra Controller Driver for Linux. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 ******************************************************************/ 9 10 #ifndef __MUSB_HDRC_DEFS_H__ 11 #define __MUSB_HDRC_DEFS_H__ 12 13 #include <usb_defs.h> 14 #include <asm/io.h> 15 16 #ifdef CONFIG_USB_BLACKFIN 17 # include "blackfin_usb.h" 18 #endif 19 20 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 21 22 /* EP0 */ 23 struct musb_ep0_regs { 24 u16 reserved4; 25 u16 csr0; 26 u16 reserved5; 27 u16 reserved6; 28 u16 count0; 29 u8 host_type0; 30 u8 host_naklimit0; 31 u8 reserved7; 32 u8 reserved8; 33 u8 reserved9; 34 u8 configdata; 35 }; 36 37 /* EP 1-15 */ 38 struct musb_epN_regs { 39 u16 txmaxp; 40 u16 txcsr; 41 u16 rxmaxp; 42 u16 rxcsr; 43 u16 rxcount; 44 u8 txtype; 45 u8 txinterval; 46 u8 rxtype; 47 u8 rxinterval; 48 u8 reserved0; 49 u8 fifosize; 50 }; 51 52 /* Mentor USB core register overlay structure */ 53 #ifndef musb_regs 54 struct musb_regs { 55 /* common registers */ 56 u8 faddr; 57 u8 power; 58 u16 intrtx; 59 u16 intrrx; 60 u16 intrtxe; 61 u16 intrrxe; 62 u8 intrusb; 63 u8 intrusbe; 64 u16 frame; 65 u8 index; 66 u8 testmode; 67 /* indexed registers */ 68 u16 txmaxp; 69 u16 txcsr; 70 u16 rxmaxp; 71 u16 rxcsr; 72 u16 rxcount; 73 u8 txtype; 74 u8 txinterval; 75 u8 rxtype; 76 u8 rxinterval; 77 u8 reserved0; 78 u8 fifosize; 79 /* fifo */ 80 u32 fifox[16]; 81 /* OTG, dynamic FIFO, version & vendor registers */ 82 u8 devctl; 83 u8 reserved1; 84 u8 txfifosz; 85 u8 rxfifosz; 86 u16 txfifoadd; 87 u16 rxfifoadd; 88 u32 vcontrol; 89 u16 hwvers; 90 u16 reserved2a[1]; 91 u8 ulpi_busctl; 92 u8 reserved2b[1]; 93 u16 reserved2[3]; 94 u8 epinfo; 95 u8 raminfo; 96 u8 linkinfo; 97 u8 vplen; 98 u8 hseof1; 99 u8 fseof1; 100 u8 lseof1; 101 u8 reserved3; 102 /* target address registers */ 103 struct musb_tar_regs { 104 u8 txfuncaddr; 105 u8 reserved0; 106 u8 txhubaddr; 107 u8 txhubport; 108 u8 rxfuncaddr; 109 u8 reserved1; 110 u8 rxhubaddr; 111 u8 rxhubport; 112 } tar[16]; 113 /* 114 * endpoint registers 115 * ep0 elements are valid when array index is 0 116 * otherwise epN is valid 117 */ 118 union musb_ep_regs { 119 struct musb_ep0_regs ep0; 120 struct musb_epN_regs epN; 121 } ep[16]; 122 123 } __attribute__((packed)); 124 #endif 125 126 /* 127 * MUSB Register bits 128 */ 129 130 /* POWER */ 131 #define MUSB_POWER_ISOUPDATE 0x80 132 #define MUSB_POWER_SOFTCONN 0x40 133 #define MUSB_POWER_HSENAB 0x20 134 #define MUSB_POWER_HSMODE 0x10 135 #define MUSB_POWER_RESET 0x08 136 #define MUSB_POWER_RESUME 0x04 137 #define MUSB_POWER_SUSPENDM 0x02 138 #define MUSB_POWER_ENSUSPEND 0x01 139 #define MUSB_POWER_HSMODE_SHIFT 4 140 141 /* INTRUSB */ 142 #define MUSB_INTR_SUSPEND 0x01 143 #define MUSB_INTR_RESUME 0x02 144 #define MUSB_INTR_RESET 0x04 145 #define MUSB_INTR_BABBLE 0x04 146 #define MUSB_INTR_SOF 0x08 147 #define MUSB_INTR_CONNECT 0x10 148 #define MUSB_INTR_DISCONNECT 0x20 149 #define MUSB_INTR_SESSREQ 0x40 150 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 151 152 /* DEVCTL */ 153 #define MUSB_DEVCTL_BDEVICE 0x80 154 #define MUSB_DEVCTL_FSDEV 0x40 155 #define MUSB_DEVCTL_LSDEV 0x20 156 #define MUSB_DEVCTL_VBUS 0x18 157 #define MUSB_DEVCTL_VBUS_SHIFT 3 158 #define MUSB_DEVCTL_HM 0x04 159 #define MUSB_DEVCTL_HR 0x02 160 #define MUSB_DEVCTL_SESSION 0x01 161 162 /* ULPI VBUSCONTROL */ 163 #define ULPI_USE_EXTVBUS 0x01 164 #define ULPI_USE_EXTVBUSIND 0x02 165 166 /* TESTMODE */ 167 #define MUSB_TEST_FORCE_HOST 0x80 168 #define MUSB_TEST_FIFO_ACCESS 0x40 169 #define MUSB_TEST_FORCE_FS 0x20 170 #define MUSB_TEST_FORCE_HS 0x10 171 #define MUSB_TEST_PACKET 0x08 172 #define MUSB_TEST_K 0x04 173 #define MUSB_TEST_J 0x02 174 #define MUSB_TEST_SE0_NAK 0x01 175 176 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 177 #define MUSB_FIFOSZ_DPB 0x10 178 /* Allocation size (8, 16, 32, ... 4096) */ 179 #define MUSB_FIFOSZ_SIZE 0x0f 180 181 /* CSR0 */ 182 #define MUSB_CSR0_FLUSHFIFO 0x0100 183 #define MUSB_CSR0_TXPKTRDY 0x0002 184 #define MUSB_CSR0_RXPKTRDY 0x0001 185 186 /* CSR0 in Peripheral mode */ 187 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 188 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 189 #define MUSB_CSR0_P_SENDSTALL 0x0020 190 #define MUSB_CSR0_P_SETUPEND 0x0010 191 #define MUSB_CSR0_P_DATAEND 0x0008 192 #define MUSB_CSR0_P_SENTSTALL 0x0004 193 194 /* CSR0 in Host mode */ 195 #define MUSB_CSR0_H_DIS_PING 0x0800 196 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 197 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 198 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 199 #define MUSB_CSR0_H_STATUSPKT 0x0040 200 #define MUSB_CSR0_H_REQPKT 0x0020 201 #define MUSB_CSR0_H_ERROR 0x0010 202 #define MUSB_CSR0_H_SETUPPKT 0x0008 203 #define MUSB_CSR0_H_RXSTALL 0x0004 204 205 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 206 #define MUSB_CSR0_P_WZC_BITS \ 207 (MUSB_CSR0_P_SENTSTALL) 208 #define MUSB_CSR0_H_WZC_BITS \ 209 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 210 | MUSB_CSR0_RXPKTRDY) 211 212 /* TxType/RxType */ 213 #define MUSB_TYPE_SPEED 0xc0 214 #define MUSB_TYPE_SPEED_SHIFT 6 215 #define MUSB_TYPE_SPEED_HIGH 1 216 #define MUSB_TYPE_SPEED_FULL 2 217 #define MUSB_TYPE_SPEED_LOW 3 218 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 219 #define MUSB_TYPE_PROTO_SHIFT 4 220 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 221 #define MUSB_TYPE_PROTO_BULK 2 222 #define MUSB_TYPE_PROTO_INTR 3 223 224 /* CONFIGDATA */ 225 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 226 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 227 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 228 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 229 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 230 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 231 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 232 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 233 234 /* TXCSR in Peripheral and Host mode */ 235 #define MUSB_TXCSR_AUTOSET 0x8000 236 #define MUSB_TXCSR_MODE 0x2000 237 #define MUSB_TXCSR_DMAENAB 0x1000 238 #define MUSB_TXCSR_FRCDATATOG 0x0800 239 #define MUSB_TXCSR_DMAMODE 0x0400 240 #define MUSB_TXCSR_CLRDATATOG 0x0040 241 #define MUSB_TXCSR_FLUSHFIFO 0x0008 242 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 243 #define MUSB_TXCSR_TXPKTRDY 0x0001 244 245 /* TXCSR in Peripheral mode */ 246 #define MUSB_TXCSR_P_ISO 0x4000 247 #define MUSB_TXCSR_P_INCOMPTX 0x0080 248 #define MUSB_TXCSR_P_SENTSTALL 0x0020 249 #define MUSB_TXCSR_P_SENDSTALL 0x0010 250 #define MUSB_TXCSR_P_UNDERRUN 0x0004 251 252 /* TXCSR in Host mode */ 253 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 254 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 255 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 256 #define MUSB_TXCSR_H_RXSTALL 0x0020 257 #define MUSB_TXCSR_H_ERROR 0x0004 258 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 259 260 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 261 #define MUSB_TXCSR_P_WZC_BITS \ 262 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 263 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 264 #define MUSB_TXCSR_H_WZC_BITS \ 265 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 266 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 267 268 /* RXCSR in Peripheral and Host mode */ 269 #define MUSB_RXCSR_AUTOCLEAR 0x8000 270 #define MUSB_RXCSR_DMAENAB 0x2000 271 #define MUSB_RXCSR_DISNYET 0x1000 272 #define MUSB_RXCSR_PID_ERR 0x1000 273 #define MUSB_RXCSR_DMAMODE 0x0800 274 #define MUSB_RXCSR_INCOMPRX 0x0100 275 #define MUSB_RXCSR_CLRDATATOG 0x0080 276 #define MUSB_RXCSR_FLUSHFIFO 0x0010 277 #define MUSB_RXCSR_DATAERROR 0x0008 278 #define MUSB_RXCSR_FIFOFULL 0x0002 279 #define MUSB_RXCSR_RXPKTRDY 0x0001 280 281 /* RXCSR in Peripheral mode */ 282 #define MUSB_RXCSR_P_ISO 0x4000 283 #define MUSB_RXCSR_P_SENTSTALL 0x0040 284 #define MUSB_RXCSR_P_SENDSTALL 0x0020 285 #define MUSB_RXCSR_P_OVERRUN 0x0004 286 287 /* RXCSR in Host mode */ 288 #define MUSB_RXCSR_H_AUTOREQ 0x4000 289 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 290 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 291 #define MUSB_RXCSR_H_RXSTALL 0x0040 292 #define MUSB_RXCSR_H_REQPKT 0x0020 293 #define MUSB_RXCSR_H_ERROR 0x0004 294 #define MUSB_S_RXCSR_H_DATATOGGLE 9 295 296 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 297 #define MUSB_RXCSR_P_WZC_BITS \ 298 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 299 | MUSB_RXCSR_RXPKTRDY) 300 #define MUSB_RXCSR_H_WZC_BITS \ 301 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 302 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 303 304 /* HUBADDR */ 305 #define MUSB_HUBADDR_MULTI_TT 0x80 306 307 /* Endpoint configuration information. Note: The value of endpoint fifo size 308 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other 309 * values are not supported 310 */ 311 struct musb_epinfo { 312 u8 epnum; /* endpoint number */ 313 u8 epdir; /* endpoint direction */ 314 u16 epsize; /* endpoint FIFO size */ 315 }; 316 317 /* 318 * Platform specific MUSB configuration. Any platform using the musb 319 * functionality should create one instance of this structure in the 320 * platform specific file. 321 */ 322 struct musb_config { 323 struct musb_regs *regs; 324 u32 timeout; 325 u8 musb_speed; 326 u8 extvbus; 327 }; 328 329 /* externally defined data */ 330 extern struct musb_config musb_cfg; 331 extern struct musb_regs *musbr; 332 333 /* exported functions */ 334 extern void musb_start(void); 335 extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt); 336 extern void write_fifo(u8 ep, u32 length, void *fifo_data); 337 extern void read_fifo(u8 ep, u32 length, void *fifo_data); 338 339 #if defined(CONFIG_USB_BLACKFIN) 340 /* Every USB register is accessed as a 16-bit even if the value itself 341 * is only 8-bits in size. Fun stuff. 342 */ 343 # undef readb 344 # define readb(addr) (u8)bfin_read16(addr) 345 # undef writeb 346 # define writeb(b, addr) bfin_write16(addr, b) 347 # undef MUSB_TXCSR_MODE /* not supported */ 348 # define MUSB_TXCSR_MODE 0 349 /* 350 * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY. 351 * However, it has no ULPI support - so there are no registers at all. 352 * That means accesses to ULPI_BUSCONTROL have to be abstracted away. 353 */ 354 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr) 355 { 356 return 0; 357 } 358 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val) 359 {} 360 #else 361 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr) 362 { 363 return readb(&musbr->ulpi_busctl); 364 } 365 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val) 366 { 367 writeb(val, &musbr->ulpi_busctl); 368 } 369 #endif 370 371 #endif /* __MUSB_HDRC_DEFS_H__ */ 372