1 /****************************************************************** 2 * Copyright 2008 Mentor Graphics Corporation 3 * Copyright (C) 2008 by Texas Instruments 4 * 5 * This file is part of the Inventra Controller Driver for Linux. 6 * 7 * The Inventra Controller Driver for Linux is free software; you 8 * can redistribute it and/or modify it under the terms of the GNU 9 * General Public License version 2 as published by the Free Software 10 * Foundation. 11 * 12 * The Inventra Controller Driver for Linux is distributed in 13 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 14 * without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 * License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with The Inventra Controller Driver for Linux ; if not, 20 * write to the Free Software Foundation, Inc., 59 Temple Place, 21 * Suite 330, Boston, MA 02111-1307 USA 22 * 23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION 24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE 25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS 26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. 27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES 28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND 29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT 30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR 31 * GRAPHICS SUPPORT CUSTOMER. 32 ******************************************************************/ 33 34 #ifndef __MUSB_HDRC_DEFS_H__ 35 #define __MUSB_HDRC_DEFS_H__ 36 37 #include <usb.h> 38 #include <usb_defs.h> 39 #include <asm/io.h> 40 41 #ifdef CONFIG_USB_BLACKFIN 42 # include "blackfin_usb.h" 43 #endif 44 45 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 46 47 /* EP0 */ 48 struct musb_ep0_regs { 49 u16 reserved4; 50 u16 csr0; 51 u16 reserved5; 52 u16 reserved6; 53 u16 count0; 54 u8 host_type0; 55 u8 host_naklimit0; 56 u8 reserved7; 57 u8 reserved8; 58 u8 reserved9; 59 u8 configdata; 60 }; 61 62 /* EP 1-15 */ 63 struct musb_epN_regs { 64 u16 txmaxp; 65 u16 txcsr; 66 u16 rxmaxp; 67 u16 rxcsr; 68 u16 rxcount; 69 u8 txtype; 70 u8 txinterval; 71 u8 rxtype; 72 u8 rxinterval; 73 u8 reserved0; 74 u8 fifosize; 75 }; 76 77 /* Mentor USB core register overlay structure */ 78 #ifndef musb_regs 79 struct musb_regs { 80 /* common registers */ 81 u8 faddr; 82 u8 power; 83 u16 intrtx; 84 u16 intrrx; 85 u16 intrtxe; 86 u16 intrrxe; 87 u8 intrusb; 88 u8 intrusbe; 89 u16 frame; 90 u8 index; 91 u8 testmode; 92 /* indexed registers */ 93 u16 txmaxp; 94 u16 txcsr; 95 u16 rxmaxp; 96 u16 rxcsr; 97 u16 rxcount; 98 u8 txtype; 99 u8 txinterval; 100 u8 rxtype; 101 u8 rxinterval; 102 u8 reserved0; 103 u8 fifosize; 104 /* fifo */ 105 u32 fifox[16]; 106 /* OTG, dynamic FIFO, version & vendor registers */ 107 u8 devctl; 108 u8 reserved1; 109 u8 txfifosz; 110 u8 rxfifosz; 111 u16 txfifoadd; 112 u16 rxfifoadd; 113 u32 vcontrol; 114 u16 hwvers; 115 u16 reserved2[5]; 116 u8 epinfo; 117 u8 raminfo; 118 u8 linkinfo; 119 u8 vplen; 120 u8 hseof1; 121 u8 fseof1; 122 u8 lseof1; 123 u8 reserved3; 124 /* target address registers */ 125 struct musb_tar_regs { 126 u8 txfuncaddr; 127 u8 reserved0; 128 u8 txhubaddr; 129 u8 txhubport; 130 u8 rxfuncaddr; 131 u8 reserved1; 132 u8 rxhubaddr; 133 u8 rxhubport; 134 } tar[16]; 135 /* 136 * endpoint registers 137 * ep0 elements are valid when array index is 0 138 * otherwise epN is valid 139 */ 140 union musb_ep_regs { 141 struct musb_ep0_regs ep0; 142 struct musb_epN_regs epN; 143 } ep[16]; 144 145 } __attribute__((packed, aligned(32))); 146 #endif 147 148 /* 149 * MUSB Register bits 150 */ 151 152 /* POWER */ 153 #define MUSB_POWER_ISOUPDATE 0x80 154 #define MUSB_POWER_SOFTCONN 0x40 155 #define MUSB_POWER_HSENAB 0x20 156 #define MUSB_POWER_HSMODE 0x10 157 #define MUSB_POWER_RESET 0x08 158 #define MUSB_POWER_RESUME 0x04 159 #define MUSB_POWER_SUSPENDM 0x02 160 #define MUSB_POWER_ENSUSPEND 0x01 161 #define MUSB_POWER_HSMODE_SHIFT 4 162 163 /* INTRUSB */ 164 #define MUSB_INTR_SUSPEND 0x01 165 #define MUSB_INTR_RESUME 0x02 166 #define MUSB_INTR_RESET 0x04 167 #define MUSB_INTR_BABBLE 0x04 168 #define MUSB_INTR_SOF 0x08 169 #define MUSB_INTR_CONNECT 0x10 170 #define MUSB_INTR_DISCONNECT 0x20 171 #define MUSB_INTR_SESSREQ 0x40 172 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 173 174 /* DEVCTL */ 175 #define MUSB_DEVCTL_BDEVICE 0x80 176 #define MUSB_DEVCTL_FSDEV 0x40 177 #define MUSB_DEVCTL_LSDEV 0x20 178 #define MUSB_DEVCTL_VBUS 0x18 179 #define MUSB_DEVCTL_VBUS_SHIFT 3 180 #define MUSB_DEVCTL_HM 0x04 181 #define MUSB_DEVCTL_HR 0x02 182 #define MUSB_DEVCTL_SESSION 0x01 183 184 /* TESTMODE */ 185 #define MUSB_TEST_FORCE_HOST 0x80 186 #define MUSB_TEST_FIFO_ACCESS 0x40 187 #define MUSB_TEST_FORCE_FS 0x20 188 #define MUSB_TEST_FORCE_HS 0x10 189 #define MUSB_TEST_PACKET 0x08 190 #define MUSB_TEST_K 0x04 191 #define MUSB_TEST_J 0x02 192 #define MUSB_TEST_SE0_NAK 0x01 193 194 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 195 #define MUSB_FIFOSZ_DPB 0x10 196 /* Allocation size (8, 16, 32, ... 4096) */ 197 #define MUSB_FIFOSZ_SIZE 0x0f 198 199 /* CSR0 */ 200 #define MUSB_CSR0_FLUSHFIFO 0x0100 201 #define MUSB_CSR0_TXPKTRDY 0x0002 202 #define MUSB_CSR0_RXPKTRDY 0x0001 203 204 /* CSR0 in Peripheral mode */ 205 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 206 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 207 #define MUSB_CSR0_P_SENDSTALL 0x0020 208 #define MUSB_CSR0_P_SETUPEND 0x0010 209 #define MUSB_CSR0_P_DATAEND 0x0008 210 #define MUSB_CSR0_P_SENTSTALL 0x0004 211 212 /* CSR0 in Host mode */ 213 #define MUSB_CSR0_H_DIS_PING 0x0800 214 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 215 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 216 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 217 #define MUSB_CSR0_H_STATUSPKT 0x0040 218 #define MUSB_CSR0_H_REQPKT 0x0020 219 #define MUSB_CSR0_H_ERROR 0x0010 220 #define MUSB_CSR0_H_SETUPPKT 0x0008 221 #define MUSB_CSR0_H_RXSTALL 0x0004 222 223 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 224 #define MUSB_CSR0_P_WZC_BITS \ 225 (MUSB_CSR0_P_SENTSTALL) 226 #define MUSB_CSR0_H_WZC_BITS \ 227 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 228 | MUSB_CSR0_RXPKTRDY) 229 230 /* TxType/RxType */ 231 #define MUSB_TYPE_SPEED 0xc0 232 #define MUSB_TYPE_SPEED_SHIFT 6 233 #define MUSB_TYPE_SPEED_HIGH 1 234 #define MUSB_TYPE_SPEED_FULL 2 235 #define MUSB_TYPE_SPEED_LOW 3 236 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 237 #define MUSB_TYPE_PROTO_SHIFT 4 238 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 239 #define MUSB_TYPE_PROTO_BULK 2 240 #define MUSB_TYPE_PROTO_INTR 3 241 242 /* CONFIGDATA */ 243 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 244 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 245 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 246 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 247 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 248 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 249 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 250 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 251 252 /* TXCSR in Peripheral and Host mode */ 253 #define MUSB_TXCSR_AUTOSET 0x8000 254 #define MUSB_TXCSR_MODE 0x2000 255 #define MUSB_TXCSR_DMAENAB 0x1000 256 #define MUSB_TXCSR_FRCDATATOG 0x0800 257 #define MUSB_TXCSR_DMAMODE 0x0400 258 #define MUSB_TXCSR_CLRDATATOG 0x0040 259 #define MUSB_TXCSR_FLUSHFIFO 0x0008 260 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 261 #define MUSB_TXCSR_TXPKTRDY 0x0001 262 263 /* TXCSR in Peripheral mode */ 264 #define MUSB_TXCSR_P_ISO 0x4000 265 #define MUSB_TXCSR_P_INCOMPTX 0x0080 266 #define MUSB_TXCSR_P_SENTSTALL 0x0020 267 #define MUSB_TXCSR_P_SENDSTALL 0x0010 268 #define MUSB_TXCSR_P_UNDERRUN 0x0004 269 270 /* TXCSR in Host mode */ 271 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 272 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 273 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 274 #define MUSB_TXCSR_H_RXSTALL 0x0020 275 #define MUSB_TXCSR_H_ERROR 0x0004 276 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 277 278 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 279 #define MUSB_TXCSR_P_WZC_BITS \ 280 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 281 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 282 #define MUSB_TXCSR_H_WZC_BITS \ 283 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 284 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 285 286 /* RXCSR in Peripheral and Host mode */ 287 #define MUSB_RXCSR_AUTOCLEAR 0x8000 288 #define MUSB_RXCSR_DMAENAB 0x2000 289 #define MUSB_RXCSR_DISNYET 0x1000 290 #define MUSB_RXCSR_PID_ERR 0x1000 291 #define MUSB_RXCSR_DMAMODE 0x0800 292 #define MUSB_RXCSR_INCOMPRX 0x0100 293 #define MUSB_RXCSR_CLRDATATOG 0x0080 294 #define MUSB_RXCSR_FLUSHFIFO 0x0010 295 #define MUSB_RXCSR_DATAERROR 0x0008 296 #define MUSB_RXCSR_FIFOFULL 0x0002 297 #define MUSB_RXCSR_RXPKTRDY 0x0001 298 299 /* RXCSR in Peripheral mode */ 300 #define MUSB_RXCSR_P_ISO 0x4000 301 #define MUSB_RXCSR_P_SENTSTALL 0x0040 302 #define MUSB_RXCSR_P_SENDSTALL 0x0020 303 #define MUSB_RXCSR_P_OVERRUN 0x0004 304 305 /* RXCSR in Host mode */ 306 #define MUSB_RXCSR_H_AUTOREQ 0x4000 307 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 308 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 309 #define MUSB_RXCSR_H_RXSTALL 0x0040 310 #define MUSB_RXCSR_H_REQPKT 0x0020 311 #define MUSB_RXCSR_H_ERROR 0x0004 312 #define MUSB_S_RXCSR_H_DATATOGGLE 9 313 314 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 315 #define MUSB_RXCSR_P_WZC_BITS \ 316 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 317 | MUSB_RXCSR_RXPKTRDY) 318 #define MUSB_RXCSR_H_WZC_BITS \ 319 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 320 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 321 322 /* HUBADDR */ 323 #define MUSB_HUBADDR_MULTI_TT 0x80 324 325 /* Endpoint configuration information. Note: The value of endpoint fifo size 326 * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other 327 * values are not supported 328 */ 329 struct musb_epinfo { 330 u8 epnum; /* endpoint number */ 331 u8 epdir; /* endpoint direction */ 332 u16 epsize; /* endpoint FIFO size */ 333 }; 334 335 /* 336 * Platform specific MUSB configuration. Any platform using the musb 337 * functionality should create one instance of this structure in the 338 * platform specific file. 339 */ 340 struct musb_config { 341 struct musb_regs *regs; 342 u32 timeout; 343 u8 musb_speed; 344 }; 345 346 /* externally defined data */ 347 extern struct musb_config musb_cfg; 348 extern struct musb_regs *musbr; 349 350 /* exported functions */ 351 extern void musb_start(void); 352 extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); 353 extern void write_fifo(u8 ep, u32 length, void *fifo_data); 354 extern void read_fifo(u8 ep, u32 length, void *fifo_data); 355 356 #if defined(CONFIG_USB_BLACKFIN) 357 /* Every USB register is accessed as a 16-bit even if the value itself 358 * is only 8-bits in size. Fun stuff. 359 */ 360 # undef readb 361 # define readb(addr) (u8)bfin_read16(addr) 362 # undef writeb 363 # define writeb(b, addr) bfin_write16(addr, b) 364 #endif 365 366 #endif /* __MUSB_HDRC_DEFS_H__ */ 367