1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Allwinner SUNXI "glue layer" 4 * 5 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com> 6 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi> 7 * 8 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code. 9 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd. 10 * javen <javen@allwinnertech.com> 11 * 12 * Based on the DA8xx "glue layer" code. 13 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 14 * Copyright (C) 2005-2006 by Texas Instruments 15 * 16 * This file is part of the Inventra Controller Driver for Linux. 17 */ 18 #include <common.h> 19 #include <dm.h> 20 #include <generic-phy.h> 21 #include <phy-sun4i-usb.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/clock.h> 24 #include <asm/arch/gpio.h> 25 #include <asm-generic/gpio.h> 26 #include <dm/lists.h> 27 #include <dm/root.h> 28 #include <linux/usb/musb.h> 29 #include "linux-compat.h" 30 #include "musb_core.h" 31 #include "musb_uboot.h" 32 33 /****************************************************************************** 34 ****************************************************************************** 35 * From the Allwinner driver 36 ****************************************************************************** 37 ******************************************************************************/ 38 39 /****************************************************************************** 40 * From include/sunxi_usb_bsp.h 41 ******************************************************************************/ 42 43 /* reg offsets */ 44 #define USBC_REG_o_ISCR 0x0400 45 #define USBC_REG_o_PHYCTL 0x0404 46 #define USBC_REG_o_PHYBIST 0x0408 47 #define USBC_REG_o_PHYTUNE 0x040c 48 49 #define USBC_REG_o_VEND0 0x0043 50 51 /* Interface Status and Control */ 52 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30 53 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29 54 #define USBC_BP_ISCR_EXT_ID_STATUS 28 55 #define USBC_BP_ISCR_EXT_DM_STATUS 27 56 #define USBC_BP_ISCR_EXT_DP_STATUS 26 57 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25 58 #define USBC_BP_ISCR_MERGED_ID_STATUS 24 59 60 #define USBC_BP_ISCR_ID_PULLUP_EN 17 61 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16 62 #define USBC_BP_ISCR_FORCE_ID 14 63 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12 64 #define USBC_BP_ISCR_VBUS_VALID_SRC 10 65 66 #define USBC_BP_ISCR_HOSC_EN 7 67 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6 68 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5 69 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4 70 #define USBC_BP_ISCR_IRQ_ENABLE 3 71 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2 72 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1 73 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0 74 75 /****************************************************************************** 76 * From usbc/usbc.c 77 ******************************************************************************/ 78 79 #define OFF_SUN6I_AHB_RESET0 0x2c0 80 81 struct sunxi_musb_config { 82 struct musb_hdrc_config *config; 83 bool has_reset; 84 u8 rst_bit; 85 u8 clkgate_bit; 86 u32 off_reset0; 87 }; 88 89 struct sunxi_glue { 90 struct musb_host_data mdata; 91 struct sunxi_ccm_reg *ccm; 92 u32 *reg_reset0; 93 struct sunxi_musb_config *cfg; 94 struct device dev; 95 struct phy phy; 96 }; 97 #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev) 98 99 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val) 100 { 101 u32 temp = reg_val; 102 103 temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT); 104 temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT); 105 temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT); 106 107 return temp; 108 } 109 110 static void USBC_EnableIdPullUp(__iomem void *base) 111 { 112 u32 reg_val; 113 114 reg_val = musb_readl(base, USBC_REG_o_ISCR); 115 reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN); 116 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 117 musb_writel(base, USBC_REG_o_ISCR, reg_val); 118 } 119 120 static void USBC_EnableDpDmPullUp(__iomem void *base) 121 { 122 u32 reg_val; 123 124 reg_val = musb_readl(base, USBC_REG_o_ISCR); 125 reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN); 126 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 127 musb_writel(base, USBC_REG_o_ISCR, reg_val); 128 } 129 130 static void USBC_ForceIdToLow(__iomem void *base) 131 { 132 u32 reg_val; 133 134 reg_val = musb_readl(base, USBC_REG_o_ISCR); 135 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID); 136 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID); 137 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 138 musb_writel(base, USBC_REG_o_ISCR, reg_val); 139 } 140 141 static void USBC_ForceIdToHigh(__iomem void *base) 142 { 143 u32 reg_val; 144 145 reg_val = musb_readl(base, USBC_REG_o_ISCR); 146 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID); 147 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID); 148 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 149 musb_writel(base, USBC_REG_o_ISCR, reg_val); 150 } 151 152 static void USBC_ForceVbusValidToLow(__iomem void *base) 153 { 154 u32 reg_val; 155 156 reg_val = musb_readl(base, USBC_REG_o_ISCR); 157 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); 158 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID); 159 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 160 musb_writel(base, USBC_REG_o_ISCR, reg_val); 161 } 162 163 static void USBC_ForceVbusValidToHigh(__iomem void *base) 164 { 165 u32 reg_val; 166 167 reg_val = musb_readl(base, USBC_REG_o_ISCR); 168 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); 169 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID); 170 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val); 171 musb_writel(base, USBC_REG_o_ISCR, reg_val); 172 } 173 174 static void USBC_ConfigFIFO_Base(void) 175 { 176 u32 reg_value; 177 178 /* config usb fifo, 8kb mode */ 179 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); 180 reg_value &= ~(0x03 << 0); 181 reg_value |= BIT(0); 182 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); 183 } 184 185 /****************************************************************************** 186 * Needed for the DFU polling magic 187 ******************************************************************************/ 188 189 static u8 last_int_usb; 190 191 bool dfu_usb_get_reset(void) 192 { 193 return !!(last_int_usb & MUSB_INTR_RESET); 194 } 195 196 /****************************************************************************** 197 * MUSB Glue code 198 ******************************************************************************/ 199 200 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 201 { 202 struct musb *musb = __hci; 203 irqreturn_t retval = IRQ_NONE; 204 205 /* read and flush interrupts */ 206 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 207 last_int_usb = musb->int_usb; 208 if (musb->int_usb) 209 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); 210 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 211 if (musb->int_tx) 212 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); 213 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 214 if (musb->int_rx) 215 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); 216 217 if (musb->int_usb || musb->int_tx || musb->int_rx) 218 retval |= musb_interrupt(musb); 219 220 return retval; 221 } 222 223 /* musb_core does not call enable / disable in a balanced manner <sigh> */ 224 static bool enabled = false; 225 226 static int sunxi_musb_enable(struct musb *musb) 227 { 228 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 229 int ret; 230 231 pr_debug("%s():\n", __func__); 232 233 musb_ep_select(musb->mregs, 0); 234 musb_writeb(musb->mregs, MUSB_FADDR, 0); 235 236 if (enabled) 237 return 0; 238 239 /* select PIO mode */ 240 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0); 241 242 if (is_host_enabled(musb)) { 243 ret = sun4i_usb_phy_vbus_detect(&glue->phy); 244 if (ret == 1) { 245 printf("A charger is plugged into the OTG: "); 246 return -ENODEV; 247 } 248 249 ret = sun4i_usb_phy_id_detect(&glue->phy); 250 if (ret == 1) { 251 printf("No host cable detected: "); 252 return -ENODEV; 253 } 254 255 ret = generic_phy_power_on(&glue->phy); 256 if (ret) { 257 pr_err("failed to power on USB PHY\n"); 258 return ret; 259 } 260 } 261 262 USBC_ForceVbusValidToHigh(musb->mregs); 263 264 enabled = true; 265 return 0; 266 } 267 268 static void sunxi_musb_disable(struct musb *musb) 269 { 270 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 271 int ret; 272 273 pr_debug("%s():\n", __func__); 274 275 if (!enabled) 276 return; 277 278 if (is_host_enabled(musb)) { 279 ret = generic_phy_power_off(&glue->phy); 280 if (ret) { 281 pr_err("failed to power off USB PHY\n"); 282 return; 283 } 284 } 285 286 USBC_ForceVbusValidToLow(musb->mregs); 287 mdelay(200); /* Wait for the current session to timeout */ 288 289 enabled = false; 290 } 291 292 static int sunxi_musb_init(struct musb *musb) 293 { 294 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 295 int ret; 296 297 pr_debug("%s():\n", __func__); 298 299 ret = generic_phy_init(&glue->phy); 300 if (ret) { 301 pr_err("failed to init USB PHY\n"); 302 return ret; 303 } 304 305 musb->isr = sunxi_musb_interrupt; 306 307 setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); 308 if (glue->cfg->clkgate_bit) 309 setbits_le32(&glue->ccm->ahb_gate0, 310 BIT(glue->cfg->clkgate_bit)); 311 312 if (glue->cfg->has_reset) 313 setbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0)); 314 315 if (glue->cfg->rst_bit) 316 setbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit)); 317 318 USBC_ConfigFIFO_Base(); 319 USBC_EnableDpDmPullUp(musb->mregs); 320 USBC_EnableIdPullUp(musb->mregs); 321 322 if (is_host_enabled(musb)) { 323 /* Host mode */ 324 USBC_ForceIdToLow(musb->mregs); 325 } else { 326 /* Peripheral mode */ 327 USBC_ForceIdToHigh(musb->mregs); 328 } 329 USBC_ForceVbusValidToHigh(musb->mregs); 330 331 return 0; 332 } 333 334 static int sunxi_musb_exit(struct musb *musb) 335 { 336 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 337 int ret = 0; 338 339 if (generic_phy_valid(&glue->phy)) { 340 ret = generic_phy_exit(&glue->phy); 341 if (ret) { 342 dev_err(dev, "failed to power off usb phy\n"); 343 return ret; 344 } 345 } 346 347 if (glue->cfg->has_reset) 348 clrbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0)); 349 350 if (glue->cfg->rst_bit) 351 clrbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit)); 352 353 clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); 354 if (glue->cfg->clkgate_bit) 355 clrbits_le32(&glue->ccm->ahb_gate0, 356 BIT(glue->cfg->clkgate_bit)); 357 358 return 0; 359 } 360 361 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 362 { 363 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 364 365 sun4i_usb_phy_set_squelch_detect(&glue->phy, false); 366 } 367 368 static void sunxi_musb_post_root_reset_end(struct musb *musb) 369 { 370 struct sunxi_glue *glue = to_sunxi_glue(musb->controller); 371 372 sun4i_usb_phy_set_squelch_detect(&glue->phy, true); 373 } 374 375 static const struct musb_platform_ops sunxi_musb_ops = { 376 .init = sunxi_musb_init, 377 .exit = sunxi_musb_exit, 378 .enable = sunxi_musb_enable, 379 .disable = sunxi_musb_disable, 380 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 381 .post_root_reset_end = sunxi_musb_post_root_reset_end, 382 }; 383 384 /* Allwinner OTG supports up to 5 endpoints */ 385 #define SUNXI_MUSB_MAX_EP_NUM 6 386 #define SUNXI_MUSB_RAM_BITS 11 387 388 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { 389 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 390 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 391 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 392 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 393 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 394 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 395 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 396 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 397 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 398 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 399 }; 400 401 /* H3/V3s OTG supports only 4 endpoints */ 402 #define SUNXI_MUSB_MAX_EP_NUM_H3 5 403 404 static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = { 405 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 406 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 407 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 408 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 409 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 410 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 411 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 412 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 413 }; 414 415 static struct musb_hdrc_config musb_config = { 416 .fifo_cfg = sunxi_musb_mode_cfg, 417 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), 418 .multipoint = true, 419 .dyn_fifo = true, 420 .num_eps = SUNXI_MUSB_MAX_EP_NUM, 421 .ram_bits = SUNXI_MUSB_RAM_BITS, 422 }; 423 424 static struct musb_hdrc_config musb_config_h3 = { 425 .fifo_cfg = sunxi_musb_mode_cfg_h3, 426 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3), 427 .multipoint = true, 428 .dyn_fifo = true, 429 .soft_con = true, 430 .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3, 431 .ram_bits = SUNXI_MUSB_RAM_BITS, 432 }; 433 434 static int musb_usb_probe(struct udevice *dev) 435 { 436 struct sunxi_glue *glue = dev_get_priv(dev); 437 struct musb_host_data *host = &glue->mdata; 438 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 439 struct musb_hdrc_platform_data pdata; 440 void *base = dev_read_addr_ptr(dev); 441 int ret; 442 443 if (!base) 444 return -EINVAL; 445 446 glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev); 447 if (!glue->cfg) 448 return -EINVAL; 449 450 glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 451 if (IS_ERR(glue->ccm)) 452 return PTR_ERR(glue->ccm); 453 454 glue->reg_reset0 = (void *)glue->ccm + glue->cfg->off_reset0; 455 456 ret = generic_phy_get_by_name(dev, "usb", &glue->phy); 457 if (ret) { 458 pr_err("failed to get usb PHY\n"); 459 return ret; 460 } 461 462 priv->desc_before_addr = true; 463 464 memset(&pdata, 0, sizeof(pdata)); 465 pdata.power = 250; 466 pdata.platform_ops = &sunxi_musb_ops; 467 pdata.config = glue->cfg->config; 468 469 #ifdef CONFIG_USB_MUSB_HOST 470 pdata.mode = MUSB_HOST; 471 host->host = musb_init_controller(&pdata, &glue->dev, base); 472 if (!host->host) 473 return -EIO; 474 475 ret = musb_lowlevel_init(host); 476 if (!ret) 477 printf("Allwinner mUSB OTG (Host)\n"); 478 #else 479 pdata.mode = MUSB_PERIPHERAL; 480 host->host = musb_register(&pdata, &glue->dev, base); 481 if (!host->host) 482 return -EIO; 483 484 printf("Allwinner mUSB OTG (Peripheral)\n"); 485 #endif 486 487 return ret; 488 } 489 490 static int musb_usb_remove(struct udevice *dev) 491 { 492 struct sunxi_glue *glue = dev_get_priv(dev); 493 struct musb_host_data *host = &glue->mdata; 494 495 musb_stop(host->host); 496 free(host->host); 497 host->host = NULL; 498 499 return 0; 500 } 501 502 static const struct sunxi_musb_config sun4i_a10_cfg = { 503 .config = &musb_config, 504 .has_reset = false, 505 }; 506 507 static const struct sunxi_musb_config sun6i_a31_cfg = { 508 .config = &musb_config, 509 .has_reset = true, 510 .off_reset0 = OFF_SUN6I_AHB_RESET0, 511 }; 512 513 static const struct sunxi_musb_config sun8i_h3_cfg = { 514 .config = &musb_config_h3, 515 .has_reset = true, 516 .rst_bit = 23, 517 .clkgate_bit = 23, 518 .off_reset0 = OFF_SUN6I_AHB_RESET0, 519 }; 520 521 static const struct udevice_id sunxi_musb_ids[] = { 522 { .compatible = "allwinner,sun4i-a10-musb", 523 .data = (ulong)&sun4i_a10_cfg }, 524 { .compatible = "allwinner,sun6i-a31-musb", 525 .data = (ulong)&sun6i_a31_cfg }, 526 { .compatible = "allwinner,sun8i-a33-musb", 527 .data = (ulong)&sun6i_a31_cfg }, 528 { .compatible = "allwinner,sun8i-h3-musb", 529 .data = (ulong)&sun8i_h3_cfg }, 530 { } 531 }; 532 533 U_BOOT_DRIVER(usb_musb) = { 534 .name = "sunxi-musb", 535 #ifdef CONFIG_USB_MUSB_HOST 536 .id = UCLASS_USB, 537 #else 538 .id = UCLASS_USB_DEV_GENERIC, 539 #endif 540 .of_match = sunxi_musb_ids, 541 .probe = musb_usb_probe, 542 .remove = musb_usb_remove, 543 #ifdef CONFIG_USB_MUSB_HOST 544 .ops = &musb_usb_ops, 545 #endif 546 .platdata_auto_alloc_size = sizeof(struct usb_platdata), 547 .priv_auto_alloc_size = sizeof(struct sunxi_glue), 548 }; 549