1 /* 2 * MUSB OTG driver register defines 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #ifndef __MUSB_REGS_H__ 12 #define __MUSB_REGS_H__ 13 14 #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ 15 16 /* 17 * MUSB Register bits 18 */ 19 20 /* POWER */ 21 #define MUSB_POWER_ISOUPDATE 0x80 22 #define MUSB_POWER_SOFTCONN 0x40 23 #define MUSB_POWER_HSENAB 0x20 24 #define MUSB_POWER_HSMODE 0x10 25 #define MUSB_POWER_RESET 0x08 26 #define MUSB_POWER_RESUME 0x04 27 #define MUSB_POWER_SUSPENDM 0x02 28 #define MUSB_POWER_ENSUSPEND 0x01 29 30 /* INTRUSB */ 31 #define MUSB_INTR_SUSPEND 0x01 32 #define MUSB_INTR_RESUME 0x02 33 #define MUSB_INTR_RESET 0x04 34 #define MUSB_INTR_BABBLE 0x04 35 #define MUSB_INTR_SOF 0x08 36 #define MUSB_INTR_CONNECT 0x10 37 #define MUSB_INTR_DISCONNECT 0x20 38 #define MUSB_INTR_SESSREQ 0x40 39 #define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ 40 41 /* DEVCTL */ 42 #define MUSB_DEVCTL_BDEVICE 0x80 43 #define MUSB_DEVCTL_FSDEV 0x40 44 #define MUSB_DEVCTL_LSDEV 0x20 45 #define MUSB_DEVCTL_VBUS 0x18 46 #define MUSB_DEVCTL_VBUS_SHIFT 3 47 #define MUSB_DEVCTL_HM 0x04 48 #define MUSB_DEVCTL_HR 0x02 49 #define MUSB_DEVCTL_SESSION 0x01 50 51 /* MUSB ULPI VBUSCONTROL */ 52 #define MUSB_ULPI_USE_EXTVBUS 0x01 53 #define MUSB_ULPI_USE_EXTVBUSIND 0x02 54 /* ULPI_REG_CONTROL */ 55 #define MUSB_ULPI_REG_REQ (1 << 0) 56 #define MUSB_ULPI_REG_CMPLT (1 << 1) 57 #define MUSB_ULPI_RDN_WR (1 << 2) 58 59 /* TESTMODE */ 60 #define MUSB_TEST_FORCE_HOST 0x80 61 #define MUSB_TEST_FIFO_ACCESS 0x40 62 #define MUSB_TEST_FORCE_FS 0x20 63 #define MUSB_TEST_FORCE_HS 0x10 64 #define MUSB_TEST_PACKET 0x08 65 #define MUSB_TEST_K 0x04 66 #define MUSB_TEST_J 0x02 67 #define MUSB_TEST_SE0_NAK 0x01 68 69 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ 70 #define MUSB_FIFOSZ_DPB 0x10 71 /* Allocation size (8, 16, 32, ... 4096) */ 72 #define MUSB_FIFOSZ_SIZE 0x0f 73 74 /* CSR0 */ 75 #define MUSB_CSR0_FLUSHFIFO 0x0100 76 #define MUSB_CSR0_TXPKTRDY 0x0002 77 #define MUSB_CSR0_RXPKTRDY 0x0001 78 79 /* CSR0 in Peripheral mode */ 80 #define MUSB_CSR0_P_SVDSETUPEND 0x0080 81 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 82 #define MUSB_CSR0_P_SENDSTALL 0x0020 83 #define MUSB_CSR0_P_SETUPEND 0x0010 84 #define MUSB_CSR0_P_DATAEND 0x0008 85 #define MUSB_CSR0_P_SENTSTALL 0x0004 86 87 /* CSR0 in Host mode */ 88 #define MUSB_CSR0_H_DIS_PING 0x0800 89 #define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ 90 #define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ 91 #define MUSB_CSR0_H_NAKTIMEOUT 0x0080 92 #define MUSB_CSR0_H_STATUSPKT 0x0040 93 #define MUSB_CSR0_H_REQPKT 0x0020 94 #define MUSB_CSR0_H_ERROR 0x0010 95 #define MUSB_CSR0_H_SETUPPKT 0x0008 96 #define MUSB_CSR0_H_RXSTALL 0x0004 97 98 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ 99 #define MUSB_CSR0_P_WZC_BITS \ 100 (MUSB_CSR0_P_SENTSTALL) 101 #define MUSB_CSR0_H_WZC_BITS \ 102 (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ 103 | MUSB_CSR0_RXPKTRDY) 104 105 /* TxType/RxType */ 106 #define MUSB_TYPE_SPEED 0xc0 107 #define MUSB_TYPE_SPEED_SHIFT 6 108 #define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ 109 #define MUSB_TYPE_PROTO_SHIFT 4 110 #define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ 111 112 /* CONFIGDATA */ 113 #define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ 114 #define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ 115 #define MUSB_CONFIGDATA_BIGENDIAN 0x20 116 #define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ 117 #define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ 118 #define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ 119 #define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ 120 #define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ 121 122 /* TXCSR in Peripheral and Host mode */ 123 #define MUSB_TXCSR_AUTOSET 0x8000 124 #define MUSB_TXCSR_DMAENAB 0x1000 125 #define MUSB_TXCSR_FRCDATATOG 0x0800 126 #define MUSB_TXCSR_DMAMODE 0x0400 127 #define MUSB_TXCSR_CLRDATATOG 0x0040 128 #define MUSB_TXCSR_FLUSHFIFO 0x0008 129 #define MUSB_TXCSR_FIFONOTEMPTY 0x0002 130 #define MUSB_TXCSR_TXPKTRDY 0x0001 131 132 /* TXCSR in Peripheral mode */ 133 #define MUSB_TXCSR_P_ISO 0x4000 134 #define MUSB_TXCSR_P_INCOMPTX 0x0080 135 #define MUSB_TXCSR_P_SENTSTALL 0x0020 136 #define MUSB_TXCSR_P_SENDSTALL 0x0010 137 #define MUSB_TXCSR_P_UNDERRUN 0x0004 138 139 /* TXCSR in Host mode */ 140 #define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 141 #define MUSB_TXCSR_H_DATATOGGLE 0x0100 142 #define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 143 #define MUSB_TXCSR_H_RXSTALL 0x0020 144 #define MUSB_TXCSR_H_ERROR 0x0004 145 146 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 147 #define MUSB_TXCSR_P_WZC_BITS \ 148 (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ 149 | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) 150 #define MUSB_TXCSR_H_WZC_BITS \ 151 (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ 152 | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) 153 154 /* RXCSR in Peripheral and Host mode */ 155 #define MUSB_RXCSR_AUTOCLEAR 0x8000 156 #define MUSB_RXCSR_DMAENAB 0x2000 157 #define MUSB_RXCSR_DISNYET 0x1000 158 #define MUSB_RXCSR_PID_ERR 0x1000 159 #define MUSB_RXCSR_DMAMODE 0x0800 160 #define MUSB_RXCSR_INCOMPRX 0x0100 161 #define MUSB_RXCSR_CLRDATATOG 0x0080 162 #define MUSB_RXCSR_FLUSHFIFO 0x0010 163 #define MUSB_RXCSR_DATAERROR 0x0008 164 #define MUSB_RXCSR_FIFOFULL 0x0002 165 #define MUSB_RXCSR_RXPKTRDY 0x0001 166 167 /* RXCSR in Peripheral mode */ 168 #define MUSB_RXCSR_P_ISO 0x4000 169 #define MUSB_RXCSR_P_SENTSTALL 0x0040 170 #define MUSB_RXCSR_P_SENDSTALL 0x0020 171 #define MUSB_RXCSR_P_OVERRUN 0x0004 172 173 /* RXCSR in Host mode */ 174 #define MUSB_RXCSR_H_AUTOREQ 0x4000 175 #define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 176 #define MUSB_RXCSR_H_DATATOGGLE 0x0200 177 #define MUSB_RXCSR_H_RXSTALL 0x0040 178 #define MUSB_RXCSR_H_REQPKT 0x0020 179 #define MUSB_RXCSR_H_ERROR 0x0004 180 181 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ 182 #define MUSB_RXCSR_P_WZC_BITS \ 183 (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ 184 | MUSB_RXCSR_RXPKTRDY) 185 #define MUSB_RXCSR_H_WZC_BITS \ 186 (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ 187 | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) 188 189 /* HUBADDR */ 190 #define MUSB_HUBADDR_MULTI_TT 0x80 191 192 193 #ifndef CONFIG_BLACKFIN 194 195 /* SUNXI has different reg addresses, but identical r/w functions */ 196 #ifndef CONFIG_ARCH_SUNXI 197 198 /* 199 * Common USB registers 200 */ 201 202 #define MUSB_FADDR 0x00 /* 8-bit */ 203 #define MUSB_POWER 0x01 /* 8-bit */ 204 205 #define MUSB_INTRTX 0x02 /* 16-bit */ 206 #define MUSB_INTRRX 0x04 207 #define MUSB_INTRTXE 0x06 208 #define MUSB_INTRRXE 0x08 209 #define MUSB_INTRUSB 0x0A /* 8 bit */ 210 #define MUSB_INTRUSBE 0x0B /* 8 bit */ 211 #define MUSB_FRAME 0x0C 212 #define MUSB_INDEX 0x0E /* 8 bit */ 213 #define MUSB_TESTMODE 0x0F /* 8 bit */ 214 215 /* Get offset for a given FIFO from musb->mregs */ 216 #if defined(CONFIG_USB_MUSB_TUSB6010) || \ 217 defined(CONFIG_USB_MUSB_TUSB6010_MODULE) 218 #define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20)) 219 #else 220 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4)) 221 #endif 222 223 /* 224 * Additional Control Registers 225 */ 226 227 #define MUSB_DEVCTL 0x60 /* 8 bit */ 228 229 /* These are always controlled through the INDEX register */ 230 #define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ 231 #define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ 232 #define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ 233 #define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ 234 235 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ 236 #define MUSB_HWVERS 0x6C /* 8 bit */ 237 #define MUSB_ULPI_BUSCONTROL 0x70 /* 8 bit */ 238 #define MUSB_ULPI_INT_MASK 0x72 /* 8 bit */ 239 #define MUSB_ULPI_INT_SRC 0x73 /* 8 bit */ 240 #define MUSB_ULPI_REG_DATA 0x74 /* 8 bit */ 241 #define MUSB_ULPI_REG_ADDR 0x75 /* 8 bit */ 242 #define MUSB_ULPI_REG_CONTROL 0x76 /* 8 bit */ 243 #define MUSB_ULPI_RAW_DATA 0x77 /* 8 bit */ 244 245 #define MUSB_EPINFO 0x78 /* 8 bit */ 246 #define MUSB_RAMINFO 0x79 /* 8 bit */ 247 #define MUSB_LINKINFO 0x7a /* 8 bit */ 248 #define MUSB_VPLEN 0x7b /* 8 bit */ 249 #define MUSB_HS_EOF1 0x7c /* 8 bit */ 250 #define MUSB_FS_EOF1 0x7d /* 8 bit */ 251 #define MUSB_LS_EOF1 0x7e /* 8 bit */ 252 253 /* Offsets to endpoint registers */ 254 #define MUSB_TXMAXP 0x00 255 #define MUSB_TXCSR 0x02 256 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ 257 #define MUSB_RXMAXP 0x04 258 #define MUSB_RXCSR 0x06 259 #define MUSB_RXCOUNT 0x08 260 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ 261 #define MUSB_TXTYPE 0x0A 262 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ 263 #define MUSB_TXINTERVAL 0x0B 264 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ 265 #define MUSB_RXTYPE 0x0C 266 #define MUSB_RXINTERVAL 0x0D 267 #define MUSB_FIFOSIZE 0x0F 268 #define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ 269 270 /* Offsets to endpoint registers in indexed model (using INDEX register) */ 271 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ 272 (0x10 + (_offset)) 273 274 /* Offsets to endpoint registers in flat models */ 275 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ 276 (0x100 + (0x10*(_epnum)) + (_offset)) 277 278 #if defined(CONFIG_USB_MUSB_TUSB6010) || \ 279 defined(CONFIG_USB_MUSB_TUSB6010_MODULE) 280 /* TUSB6010 EP0 configuration register is special */ 281 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ 282 (0x10 + _offset) 283 #include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */ 284 #endif 285 286 #define MUSB_TXCSR_MODE 0x2000 287 288 /* "bus control"/target registers, for host side multipoint (external hubs) */ 289 #define MUSB_TXFUNCADDR 0x00 290 #define MUSB_TXHUBADDR 0x02 291 #define MUSB_TXHUBPORT 0x03 292 293 #define MUSB_RXFUNCADDR 0x04 294 #define MUSB_RXHUBADDR 0x06 295 #define MUSB_RXHUBPORT 0x07 296 297 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ 298 (0x80 + (8*(_epnum)) + (_offset)) 299 300 #else /* CONFIG_ARCH_SUNXI */ 301 302 /* 303 * Common USB registers 304 */ 305 306 #define MUSB_FADDR 0x0098 307 #define MUSB_POWER 0x0040 308 309 #define MUSB_INTRTX 0x0044 310 #define MUSB_INTRRX 0x0046 311 #define MUSB_INTRTXE 0x0048 312 #define MUSB_INTRRXE 0x004A 313 #define MUSB_INTRUSB 0x004C 314 #define MUSB_INTRUSBE 0x0050 315 #define MUSB_FRAME 0x0054 316 #define MUSB_INDEX 0x0042 317 #define MUSB_TESTMODE 0x007C 318 319 /* Get offset for a given FIFO from musb->mregs */ 320 #define MUSB_FIFO_OFFSET(epnum) (0x00 + ((epnum) * 4)) 321 322 /* 323 * Additional Control Registers 324 */ 325 326 #define MUSB_DEVCTL 0x0041 327 328 /* These are always controlled through the INDEX register */ 329 #define MUSB_TXFIFOSZ 0x0090 330 #define MUSB_RXFIFOSZ 0x0094 331 #define MUSB_TXFIFOADD 0x0092 332 #define MUSB_RXFIFOADD 0x0096 333 334 #define MUSB_EPINFO 0x0078 335 #define MUSB_RAMINFO 0x0079 336 #define MUSB_LINKINFO 0x007A 337 #define MUSB_VPLEN 0x007B 338 #define MUSB_HS_EOF1 0x007C 339 #define MUSB_FS_EOF1 0x007D 340 #define MUSB_LS_EOF1 0x007E 341 342 /* Offsets to endpoint registers */ 343 #define MUSB_TXMAXP 0x0080 344 #define MUSB_TXCSR 0x0082 345 #define MUSB_CSR0 0x0082 346 #define MUSB_RXMAXP 0x0084 347 #define MUSB_RXCSR 0x0086 348 #define MUSB_RXCOUNT 0x0088 349 #define MUSB_COUNT0 0x0088 350 #define MUSB_TXTYPE 0x008C 351 #define MUSB_TYPE0 0x008C 352 #define MUSB_TXINTERVAL 0x008D 353 #define MUSB_NAKLIMIT0 0x008D 354 #define MUSB_RXTYPE 0x008E 355 #define MUSB_RXINTERVAL 0x008F 356 357 #define MUSB_CONFIGDATA 0x00b0 /* musb_read_configdata adds 0x10 ! */ 358 #define MUSB_FIFOSIZE 0x0090 359 360 /* Offsets to endpoint registers in indexed model (using INDEX register) */ 361 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) 362 363 #define MUSB_TXCSR_MODE 0x2000 364 365 /* "bus control"/target registers, for host side multipoint (external hubs) */ 366 #define MUSB_TXFUNCADDR 0x0098 367 #define MUSB_TXHUBADDR 0x009A 368 #define MUSB_TXHUBPORT 0x009B 369 370 #define MUSB_RXFUNCADDR 0x009C 371 #define MUSB_RXHUBADDR 0x009E 372 #define MUSB_RXHUBPORT 0x009F 373 374 /* Endpoint is selected with MUSB_INDEX. */ 375 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) 376 377 #endif /* CONFIG_ARCH_SUNXI */ 378 379 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) 380 { 381 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); 382 } 383 384 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off) 385 { 386 musb_writew(mbase, MUSB_TXFIFOADD, c_off); 387 } 388 389 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size) 390 { 391 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); 392 } 393 394 static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off) 395 { 396 musb_writew(mbase, MUSB_RXFIFOADD, c_off); 397 } 398 399 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val) 400 { 401 #ifndef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */ 402 musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val); 403 #endif 404 } 405 406 static inline u8 musb_read_txfifosz(void __iomem *mbase) 407 { 408 return musb_readb(mbase, MUSB_TXFIFOSZ); 409 } 410 411 static inline u16 musb_read_txfifoadd(void __iomem *mbase) 412 { 413 return musb_readw(mbase, MUSB_TXFIFOADD); 414 } 415 416 static inline u8 musb_read_rxfifosz(void __iomem *mbase) 417 { 418 return musb_readb(mbase, MUSB_RXFIFOSZ); 419 } 420 421 static inline u16 musb_read_rxfifoadd(void __iomem *mbase) 422 { 423 return musb_readw(mbase, MUSB_RXFIFOADD); 424 } 425 426 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) 427 { 428 #ifdef CONFIG_ARCH_SUNXI /* No ulpi on sunxi */ 429 return 0; 430 #else 431 return musb_readb(mbase, MUSB_ULPI_BUSCONTROL); 432 #endif 433 } 434 435 static inline u8 musb_read_configdata(void __iomem *mbase) 436 { 437 #if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T 438 /* <Sigh> allwinner saves a reg, and we need to hardcode this */ 439 return 0xde; 440 #else 441 musb_writeb(mbase, MUSB_INDEX, 0); 442 return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA); 443 #endif 444 } 445 446 static inline u16 musb_read_hwvers(void __iomem *mbase) 447 { 448 #ifdef CONFIG_ARCH_SUNXI 449 return 0; /* Unknown version */ 450 #else 451 return musb_readw(mbase, MUSB_HWVERS); 452 #endif 453 } 454 455 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase) 456 { 457 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase); 458 } 459 460 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, 461 u8 qh_addr_reg) 462 { 463 musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg); 464 } 465 466 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs, 467 u8 qh_h_addr_reg) 468 { 469 musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg); 470 } 471 472 static inline void musb_write_rxhubport(void __iomem *ep_target_regs, 473 u8 qh_h_port_reg) 474 { 475 musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg); 476 } 477 478 static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, 479 u8 qh_addr_reg) 480 { 481 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR), 482 qh_addr_reg); 483 } 484 485 static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, 486 u8 qh_addr_reg) 487 { 488 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR), 489 qh_addr_reg); 490 } 491 492 static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, 493 u8 qh_h_port_reg) 494 { 495 musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT), 496 qh_h_port_reg); 497 } 498 499 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum) 500 { 501 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXFUNCADDR)); 502 } 503 504 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum) 505 { 506 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBADDR)); 507 } 508 509 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum) 510 { 511 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_RXHUBPORT)); 512 } 513 514 static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum) 515 { 516 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR)); 517 } 518 519 static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum) 520 { 521 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR)); 522 } 523 524 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum) 525 { 526 return musb_readb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT)); 527 } 528 529 #else /* CONFIG_BLACKFIN */ 530 531 #define USB_BASE USB_FADDR 532 #define USB_OFFSET(reg) (reg - USB_BASE) 533 534 /* 535 * Common USB registers 536 */ 537 #define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */ 538 #define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */ 539 #define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */ 540 #define MUSB_INTRRX USB_OFFSET(USB_INTRRX) 541 #define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE) 542 #define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE) 543 #define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */ 544 #define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */ 545 #define MUSB_FRAME USB_OFFSET(USB_FRAME) 546 #define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */ 547 #define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */ 548 549 /* Get offset for a given FIFO from musb->mregs */ 550 #define MUSB_FIFO_OFFSET(epnum) \ 551 (USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8)) 552 553 /* 554 * Additional Control Registers 555 */ 556 557 #define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */ 558 559 #define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */ 560 #define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */ 561 #define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */ 562 #define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */ 563 #define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */ 564 565 /* Offsets to endpoint registers */ 566 #define MUSB_TXMAXP 0x00 567 #define MUSB_TXCSR 0x04 568 #define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ 569 #define MUSB_RXMAXP 0x08 570 #define MUSB_RXCSR 0x0C 571 #define MUSB_RXCOUNT 0x10 572 #define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ 573 #define MUSB_TXTYPE 0x14 574 #define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ 575 #define MUSB_TXINTERVAL 0x18 576 #define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ 577 #define MUSB_RXTYPE 0x1C 578 #define MUSB_RXINTERVAL 0x20 579 #define MUSB_TXCOUNT 0x28 580 581 /* Offsets to endpoint registers in indexed model (using INDEX register) */ 582 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ 583 (0x40 + (_offset)) 584 585 /* Offsets to endpoint registers in flat models */ 586 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ 587 (USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset)) 588 589 /* Not implemented - HW has separate Tx/Rx FIFO */ 590 #define MUSB_TXCSR_MODE 0x0000 591 592 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size) 593 { 594 } 595 596 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off) 597 { 598 } 599 600 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size) 601 { 602 } 603 604 static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off) 605 { 606 } 607 608 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val) 609 { 610 } 611 612 static inline u8 musb_read_txfifosz(void __iomem *mbase) 613 { 614 return 0; 615 } 616 617 static inline u16 musb_read_txfifoadd(void __iomem *mbase) 618 { 619 return 0; 620 } 621 622 static inline u8 musb_read_rxfifosz(void __iomem *mbase) 623 { 624 return 0; 625 } 626 627 static inline u16 musb_read_rxfifoadd(void __iomem *mbase) 628 { 629 return 0; 630 } 631 632 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) 633 { 634 return 0; 635 } 636 637 static inline u8 musb_read_configdata(void __iomem *mbase) 638 { 639 return 0; 640 } 641 642 static inline u16 musb_read_hwvers(void __iomem *mbase) 643 { 644 /* 645 * This register is invisible on Blackfin, actually the MUSB 646 * RTL version of Blackfin is 1.9, so just harcode its value. 647 */ 648 return MUSB_HWVERS_1900; 649 } 650 651 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase) 652 { 653 return NULL; 654 } 655 656 static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs, 657 u8 qh_addr_req) 658 { 659 } 660 661 static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs, 662 u8 qh_h_addr_reg) 663 { 664 } 665 666 static inline void musb_write_rxhubport(void __iomem *ep_target_regs, 667 u8 qh_h_port_reg) 668 { 669 } 670 671 static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum, 672 u8 qh_addr_reg) 673 { 674 } 675 676 static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum, 677 u8 qh_addr_reg) 678 { 679 } 680 681 static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum, 682 u8 qh_h_port_reg) 683 { 684 } 685 686 static inline u8 musb_read_rxfunaddr(void __iomem *mbase, u8 epnum) 687 { 688 return 0; 689 } 690 691 static inline u8 musb_read_rxhubaddr(void __iomem *mbase, u8 epnum) 692 { 693 return 0; 694 } 695 696 static inline u8 musb_read_rxhubport(void __iomem *mbase, u8 epnum) 697 { 698 return 0; 699 } 700 701 static inline u8 musb_read_txfunaddr(void __iomem *mbase, u8 epnum) 702 { 703 return 0; 704 } 705 706 static inline u8 musb_read_txhubaddr(void __iomem *mbase, u8 epnum) 707 { 708 return 0; 709 } 710 711 static inline u8 musb_read_txhubport(void __iomem *mbase, u8 epnum) 712 { 713 return 0; 714 } 715 716 #endif /* CONFIG_BLACKFIN */ 717 718 #endif /* __MUSB_REGS_H__ */ 719