1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MUSB OTG driver host support
4  *
5  * Copyright 2005 Mentor Graphics Corporation
6  * Copyright (C) 2005-2006 by Texas Instruments
7  * Copyright (C) 2006-2007 Nokia Corporation
8  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9  */
10 
11 #ifndef __UBOOT__
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
21 #else
22 #include <common.h>
23 #include <usb.h>
24 #include "linux-compat.h"
25 #include "usb-compat.h"
26 #endif
27 
28 #include "musb_core.h"
29 #include "musb_host.h"
30 
31 
32 /* MUSB HOST status 22-mar-2006
33  *
34  * - There's still lots of partial code duplication for fault paths, so
35  *   they aren't handled as consistently as they need to be.
36  *
37  * - PIO mostly behaved when last tested.
38  *     + including ep0, with all usbtest cases 9, 10
39  *     + usbtest 14 (ep0out) doesn't seem to run at all
40  *     + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
41  *       configurations, but otherwise double buffering passes basic tests.
42  *     + for 2.6.N, for N > ~10, needs API changes for hcd framework.
43  *
44  * - DMA (CPPI) ... partially behaves, not currently recommended
45  *     + about 1/15 the speed of typical EHCI implementations (PCI)
46  *     + RX, all too often reqpkt seems to misbehave after tx
47  *     + TX, no known issues (other than evident silicon issue)
48  *
49  * - DMA (Mentor/OMAP) ...has at least toggle update problems
50  *
51  * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
52  *   starvation ... nothing yet for TX, interrupt, or bulk.
53  *
54  * - Not tested with HNP, but some SRP paths seem to behave.
55  *
56  * NOTE 24-August-2006:
57  *
58  * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
59  *   extra endpoint for periodic use enabling hub + keybd + mouse.  That
60  *   mostly works, except that with "usbnet" it's easy to trigger cases
61  *   with "ping" where RX loses.  (a) ping to davinci, even "ping -f",
62  *   fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
63  *   although ARP RX wins.  (That test was done with a full speed link.)
64  */
65 
66 
67 /*
68  * NOTE on endpoint usage:
69  *
70  * CONTROL transfers all go through ep0.  BULK ones go through dedicated IN
71  * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
72  * (Yes, bulk _could_ use more of the endpoints than that, and would even
73  * benefit from it.)
74  *
75  * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
76  * So far that scheduling is both dumb and optimistic:  the endpoint will be
77  * "claimed" until its software queue is no longer refilled.  No multiplexing
78  * of transfers between endpoints, or anything clever.
79  */
80 
81 
82 static void musb_ep_program(struct musb *musb, u8 epnum,
83 			struct urb *urb, int is_out,
84 			u8 *buf, u32 offset, u32 len);
85 
86 /*
87  * Clear TX fifo. Needed to avoid BABBLE errors.
88  */
89 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
90 {
91 	struct musb	*musb = ep->musb;
92 	void __iomem	*epio = ep->regs;
93 	u16		csr;
94 	u16		lastcsr = 0;
95 	int		retries = 1000;
96 
97 	csr = musb_readw(epio, MUSB_TXCSR);
98 	while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
99 		if (csr != lastcsr)
100 			dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
101 		lastcsr = csr;
102 		csr |= MUSB_TXCSR_FLUSHFIFO;
103 		musb_writew(epio, MUSB_TXCSR, csr);
104 		csr = musb_readw(epio, MUSB_TXCSR);
105 		if (WARN(retries-- < 1,
106 				"Could not flush host TX%d fifo: csr: %04x\n",
107 				ep->epnum, csr))
108 			return;
109 		mdelay(1);
110 	}
111 }
112 
113 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
114 {
115 	void __iomem	*epio = ep->regs;
116 	u16		csr;
117 	int		retries = 5;
118 
119 	/* scrub any data left in the fifo */
120 	do {
121 		csr = musb_readw(epio, MUSB_TXCSR);
122 		if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
123 			break;
124 		musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
125 		csr = musb_readw(epio, MUSB_TXCSR);
126 		udelay(10);
127 	} while (--retries);
128 
129 	WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
130 			ep->epnum, csr);
131 
132 	/* and reset for the next transfer */
133 	musb_writew(epio, MUSB_TXCSR, 0);
134 }
135 
136 /*
137  * Start transmit. Caller is responsible for locking shared resources.
138  * musb must be locked.
139  */
140 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
141 {
142 	u16	txcsr;
143 
144 	/* NOTE: no locks here; caller should lock and select EP */
145 	if (ep->epnum) {
146 		txcsr = musb_readw(ep->regs, MUSB_TXCSR);
147 		txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
148 		musb_writew(ep->regs, MUSB_TXCSR, txcsr);
149 	} else {
150 		txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
151 		musb_writew(ep->regs, MUSB_CSR0, txcsr);
152 	}
153 
154 }
155 
156 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
157 {
158 	u16	txcsr;
159 
160 	/* NOTE: no locks here; caller should lock and select EP */
161 	txcsr = musb_readw(ep->regs, MUSB_TXCSR);
162 	txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
163 	if (is_cppi_enabled())
164 		txcsr |= MUSB_TXCSR_DMAMODE;
165 	musb_writew(ep->regs, MUSB_TXCSR, txcsr);
166 }
167 
168 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
169 {
170 	if (is_in != 0 || ep->is_shared_fifo)
171 		ep->in_qh  = qh;
172 	if (is_in == 0 || ep->is_shared_fifo)
173 		ep->out_qh = qh;
174 }
175 
176 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
177 {
178 	return is_in ? ep->in_qh : ep->out_qh;
179 }
180 
181 /*
182  * Start the URB at the front of an endpoint's queue
183  * end must be claimed from the caller.
184  *
185  * Context: controller locked, irqs blocked
186  */
187 static void
188 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
189 {
190 	u16			frame;
191 	u32			len;
192 	void __iomem		*mbase =  musb->mregs;
193 	struct urb		*urb = next_urb(qh);
194 	void			*buf = urb->transfer_buffer;
195 	u32			offset = 0;
196 	struct musb_hw_ep	*hw_ep = qh->hw_ep;
197 	unsigned		pipe = urb->pipe;
198 	u8			address = usb_pipedevice(pipe);
199 	int			epnum = hw_ep->epnum;
200 
201 	/* initialize software qh state */
202 	qh->offset = 0;
203 	qh->segsize = 0;
204 
205 	/* gather right source of data */
206 	switch (qh->type) {
207 	case USB_ENDPOINT_XFER_CONTROL:
208 		/* control transfers always start with SETUP */
209 		is_in = 0;
210 		musb->ep0_stage = MUSB_EP0_START;
211 		buf = urb->setup_packet;
212 		len = 8;
213 		break;
214 #ifndef __UBOOT__
215 	case USB_ENDPOINT_XFER_ISOC:
216 		qh->iso_idx = 0;
217 		qh->frame = 0;
218 		offset = urb->iso_frame_desc[0].offset;
219 		len = urb->iso_frame_desc[0].length;
220 		break;
221 #endif
222 	default:		/* bulk, interrupt */
223 		/* actual_length may be nonzero on retry paths */
224 		buf = urb->transfer_buffer + urb->actual_length;
225 		len = urb->transfer_buffer_length - urb->actual_length;
226 	}
227 
228 	dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
229 			qh, urb, address, qh->epnum,
230 			is_in ? "in" : "out",
231 			({char *s; switch (qh->type) {
232 			case USB_ENDPOINT_XFER_CONTROL:	s = ""; break;
233 			case USB_ENDPOINT_XFER_BULK:	s = "-bulk"; break;
234 #ifndef __UBOOT__
235 			case USB_ENDPOINT_XFER_ISOC:	s = "-iso"; break;
236 #endif
237 			default:			s = "-intr"; break;
238 			}; s; }),
239 			epnum, buf + offset, len);
240 
241 	/* Configure endpoint */
242 	musb_ep_set_qh(hw_ep, is_in, qh);
243 	musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
244 
245 	/* transmit may have more work: start it when it is time */
246 	if (is_in)
247 		return;
248 
249 	/* determine if the time is right for a periodic transfer */
250 	switch (qh->type) {
251 #ifndef __UBOOT__
252 	case USB_ENDPOINT_XFER_ISOC:
253 #endif
254 	case USB_ENDPOINT_XFER_INT:
255 		dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
256 		frame = musb_readw(mbase, MUSB_FRAME);
257 		/* FIXME this doesn't implement that scheduling policy ...
258 		 * or handle framecounter wrapping
259 		 */
260 #ifndef __UBOOT__
261 		if ((urb->transfer_flags & URB_ISO_ASAP)
262 				|| (frame >= urb->start_frame)) {
263 			/* REVISIT the SOF irq handler shouldn't duplicate
264 			 * this code; and we don't init urb->start_frame...
265 			 */
266 			qh->frame = 0;
267 			goto start;
268 		} else {
269 #endif
270 			qh->frame = urb->start_frame;
271 			/* enable SOF interrupt so we can count down */
272 			dev_dbg(musb->controller, "SOF for %d\n", epnum);
273 #if 1 /* ifndef	CONFIG_ARCH_DAVINCI */
274 			musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
275 #endif
276 #ifndef __UBOOT__
277 		}
278 #endif
279 		break;
280 	default:
281 start:
282 		dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
283 			hw_ep->tx_channel ? "dma" : "pio");
284 
285 		if (!hw_ep->tx_channel)
286 			musb_h_tx_start(hw_ep);
287 		else if (is_cppi_enabled() || tusb_dma_omap())
288 			musb_h_tx_dma_start(hw_ep);
289 	}
290 }
291 
292 /* Context: caller owns controller lock, IRQs are blocked */
293 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
294 __releases(musb->lock)
295 __acquires(musb->lock)
296 {
297 	dev_dbg(musb->controller,
298 			"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
299 			urb, urb->complete, status,
300 			usb_pipedevice(urb->pipe),
301 			usb_pipeendpoint(urb->pipe),
302 			usb_pipein(urb->pipe) ? "in" : "out",
303 			urb->actual_length, urb->transfer_buffer_length
304 			);
305 
306 	usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
307 	spin_unlock(&musb->lock);
308 	usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
309 	spin_lock(&musb->lock);
310 }
311 
312 /* For bulk/interrupt endpoints only */
313 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
314 				    struct urb *urb)
315 {
316 	void __iomem		*epio = qh->hw_ep->regs;
317 	u16			csr;
318 
319 	/*
320 	 * FIXME: the current Mentor DMA code seems to have
321 	 * problems getting toggle correct.
322 	 */
323 
324 	if (is_in)
325 		csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
326 	else
327 		csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
328 
329 	usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
330 }
331 
332 /*
333  * Advance this hardware endpoint's queue, completing the specified URB and
334  * advancing to either the next URB queued to that qh, or else invalidating
335  * that qh and advancing to the next qh scheduled after the current one.
336  *
337  * Context: caller owns controller lock, IRQs are blocked
338  */
339 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
340 				  struct musb_hw_ep *hw_ep, int is_in)
341 {
342 	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, is_in);
343 	struct musb_hw_ep	*ep = qh->hw_ep;
344 	int			ready = qh->is_ready;
345 	int			status;
346 
347 	status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
348 
349 	/* save toggle eagerly, for paranoia */
350 	switch (qh->type) {
351 	case USB_ENDPOINT_XFER_BULK:
352 	case USB_ENDPOINT_XFER_INT:
353 		musb_save_toggle(qh, is_in, urb);
354 		break;
355 #ifndef __UBOOT__
356 	case USB_ENDPOINT_XFER_ISOC:
357 		if (status == 0 && urb->error_count)
358 			status = -EXDEV;
359 		break;
360 #endif
361 	}
362 
363 	qh->is_ready = 0;
364 	musb_giveback(musb, urb, status);
365 	qh->is_ready = ready;
366 
367 	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
368 	 * invalidate qh as soon as list_empty(&hep->urb_list)
369 	 */
370 	if (list_empty(&qh->hep->urb_list)) {
371 		struct list_head	*head;
372 		struct dma_controller	*dma = musb->dma_controller;
373 
374 		if (is_in) {
375 			ep->rx_reinit = 1;
376 			if (ep->rx_channel) {
377 				dma->channel_release(ep->rx_channel);
378 				ep->rx_channel = NULL;
379 			}
380 		} else {
381 			ep->tx_reinit = 1;
382 			if (ep->tx_channel) {
383 				dma->channel_release(ep->tx_channel);
384 				ep->tx_channel = NULL;
385 			}
386 		}
387 
388 		/* Clobber old pointers to this qh */
389 		musb_ep_set_qh(ep, is_in, NULL);
390 		qh->hep->hcpriv = NULL;
391 
392 		switch (qh->type) {
393 
394 		case USB_ENDPOINT_XFER_CONTROL:
395 		case USB_ENDPOINT_XFER_BULK:
396 			/* fifo policy for these lists, except that NAKing
397 			 * should rotate a qh to the end (for fairness).
398 			 */
399 			if (qh->mux == 1) {
400 				head = qh->ring.prev;
401 				list_del(&qh->ring);
402 				kfree(qh);
403 				qh = first_qh(head);
404 				break;
405 			}
406 
407 		case USB_ENDPOINT_XFER_ISOC:
408 		case USB_ENDPOINT_XFER_INT:
409 			/* this is where periodic bandwidth should be
410 			 * de-allocated if it's tracked and allocated;
411 			 * and where we'd update the schedule tree...
412 			 */
413 			kfree(qh);
414 			qh = NULL;
415 			break;
416 		}
417 	}
418 
419 	if (qh != NULL && qh->is_ready) {
420 		dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
421 		    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
422 		musb_start_urb(musb, is_in, qh);
423 	}
424 }
425 
426 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
427 {
428 	/* we don't want fifo to fill itself again;
429 	 * ignore dma (various models),
430 	 * leave toggle alone (may not have been saved yet)
431 	 */
432 	csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
433 	csr &= ~(MUSB_RXCSR_H_REQPKT
434 		| MUSB_RXCSR_H_AUTOREQ
435 		| MUSB_RXCSR_AUTOCLEAR);
436 
437 	/* write 2x to allow double buffering */
438 	musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
439 	musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
440 
441 	/* flush writebuffer */
442 	return musb_readw(hw_ep->regs, MUSB_RXCSR);
443 }
444 
445 /*
446  * PIO RX for a packet (or part of it).
447  */
448 static bool
449 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
450 {
451 	u16			rx_count;
452 	u8			*buf;
453 	u16			csr;
454 	bool			done = false;
455 	u32			length;
456 	int			do_flush = 0;
457 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
458 	void __iomem		*epio = hw_ep->regs;
459 	struct musb_qh		*qh = hw_ep->in_qh;
460 	int			pipe = urb->pipe;
461 	void			*buffer = urb->transfer_buffer;
462 
463 	/* musb_ep_select(mbase, epnum); */
464 	rx_count = musb_readw(epio, MUSB_RXCOUNT);
465 	dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
466 			urb->transfer_buffer, qh->offset,
467 			urb->transfer_buffer_length);
468 
469 	/* unload FIFO */
470 #ifndef __UBOOT__
471 	if (usb_pipeisoc(pipe)) {
472 		int					status = 0;
473 		struct usb_iso_packet_descriptor	*d;
474 
475 		if (iso_err) {
476 			status = -EILSEQ;
477 			urb->error_count++;
478 		}
479 
480 		d = urb->iso_frame_desc + qh->iso_idx;
481 		buf = buffer + d->offset;
482 		length = d->length;
483 		if (rx_count > length) {
484 			if (status == 0) {
485 				status = -EOVERFLOW;
486 				urb->error_count++;
487 			}
488 			dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
489 			do_flush = 1;
490 		} else
491 			length = rx_count;
492 		urb->actual_length += length;
493 		d->actual_length = length;
494 
495 		d->status = status;
496 
497 		/* see if we are done */
498 		done = (++qh->iso_idx >= urb->number_of_packets);
499 	} else {
500 #endif
501 		/* non-isoch */
502 		buf = buffer + qh->offset;
503 		length = urb->transfer_buffer_length - qh->offset;
504 		if (rx_count > length) {
505 			if (urb->status == -EINPROGRESS)
506 				urb->status = -EOVERFLOW;
507 			dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
508 			do_flush = 1;
509 		} else
510 			length = rx_count;
511 		urb->actual_length += length;
512 		qh->offset += length;
513 
514 		/* see if we are done */
515 		done = (urb->actual_length == urb->transfer_buffer_length)
516 			|| (rx_count < qh->maxpacket)
517 			|| (urb->status != -EINPROGRESS);
518 		if (done
519 				&& (urb->status == -EINPROGRESS)
520 				&& (urb->transfer_flags & URB_SHORT_NOT_OK)
521 				&& (urb->actual_length
522 					< urb->transfer_buffer_length))
523 			urb->status = -EREMOTEIO;
524 #ifndef __UBOOT__
525 	}
526 #endif
527 
528 	musb_read_fifo(hw_ep, length, buf);
529 
530 	csr = musb_readw(epio, MUSB_RXCSR);
531 	csr |= MUSB_RXCSR_H_WZC_BITS;
532 	if (unlikely(do_flush))
533 		musb_h_flush_rxfifo(hw_ep, csr);
534 	else {
535 		/* REVISIT this assumes AUTOCLEAR is never set */
536 		csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
537 		if (!done)
538 			csr |= MUSB_RXCSR_H_REQPKT;
539 		musb_writew(epio, MUSB_RXCSR, csr);
540 	}
541 
542 	return done;
543 }
544 
545 /* we don't always need to reinit a given side of an endpoint...
546  * when we do, use tx/rx reinit routine and then construct a new CSR
547  * to address data toggle, NYET, and DMA or PIO.
548  *
549  * it's possible that driver bugs (especially for DMA) or aborting a
550  * transfer might have left the endpoint busier than it should be.
551  * the busy/not-empty tests are basically paranoia.
552  */
553 static void
554 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
555 {
556 	u16	csr;
557 
558 	/* NOTE:  we know the "rx" fifo reinit never triggers for ep0.
559 	 * That always uses tx_reinit since ep0 repurposes TX register
560 	 * offsets; the initial SETUP packet is also a kind of OUT.
561 	 */
562 
563 	/* if programmed for Tx, put it in RX mode */
564 	if (ep->is_shared_fifo) {
565 		csr = musb_readw(ep->regs, MUSB_TXCSR);
566 		if (csr & MUSB_TXCSR_MODE) {
567 			musb_h_tx_flush_fifo(ep);
568 			csr = musb_readw(ep->regs, MUSB_TXCSR);
569 			musb_writew(ep->regs, MUSB_TXCSR,
570 				    csr | MUSB_TXCSR_FRCDATATOG);
571 		}
572 
573 		/*
574 		 * Clear the MODE bit (and everything else) to enable Rx.
575 		 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
576 		 */
577 		if (csr & MUSB_TXCSR_DMAMODE)
578 			musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
579 		musb_writew(ep->regs, MUSB_TXCSR, 0);
580 
581 	/* scrub all previous state, clearing toggle */
582 	} else {
583 		csr = musb_readw(ep->regs, MUSB_RXCSR);
584 		if (csr & MUSB_RXCSR_RXPKTRDY)
585 			WARNING("rx%d, packet/%d ready?\n", ep->epnum,
586 				musb_readw(ep->regs, MUSB_RXCOUNT));
587 
588 		musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
589 	}
590 
591 	/* target addr and (for multipoint) hub addr/port */
592 	if (musb->is_multipoint) {
593 		musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
594 		musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
595 		musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
596 
597 	} else
598 		musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
599 
600 	/* protocol/endpoint, interval/NAKlimit, i/o size */
601 	musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
602 	musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
603 	/* NOTE: bulk combining rewrites high bits of maxpacket */
604 	/* Set RXMAXP with the FIFO size of the endpoint
605 	 * to disable double buffer mode.
606 	 */
607 	if (musb->double_buffer_not_ok)
608 		musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
609 	else
610 		musb_writew(ep->regs, MUSB_RXMAXP,
611 				qh->maxpacket | ((qh->hb_mult - 1) << 11));
612 
613 	ep->rx_reinit = 0;
614 }
615 
616 static bool musb_tx_dma_program(struct dma_controller *dma,
617 		struct musb_hw_ep *hw_ep, struct musb_qh *qh,
618 		struct urb *urb, u32 offset, u32 length)
619 {
620 	struct dma_channel	*channel = hw_ep->tx_channel;
621 	void __iomem		*epio = hw_ep->regs;
622 	u16			pkt_size = qh->maxpacket;
623 	u16			csr;
624 	u8			mode;
625 
626 #ifdef	CONFIG_USB_INVENTRA_DMA
627 	if (length > channel->max_len)
628 		length = channel->max_len;
629 
630 	csr = musb_readw(epio, MUSB_TXCSR);
631 	if (length > pkt_size) {
632 		mode = 1;
633 		csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
634 		/* autoset shouldn't be set in high bandwidth */
635 		if (qh->hb_mult == 1)
636 			csr |= MUSB_TXCSR_AUTOSET;
637 	} else {
638 		mode = 0;
639 		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
640 		csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
641 	}
642 	channel->desired_mode = mode;
643 	musb_writew(epio, MUSB_TXCSR, csr);
644 #else
645 	if (!is_cppi_enabled() && !tusb_dma_omap())
646 		return false;
647 
648 	channel->actual_len = 0;
649 
650 	/*
651 	 * TX uses "RNDIS" mode automatically but needs help
652 	 * to identify the zero-length-final-packet case.
653 	 */
654 	mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
655 #endif
656 
657 	qh->segsize = length;
658 
659 	/*
660 	 * Ensure the data reaches to main memory before starting
661 	 * DMA transfer
662 	 */
663 	wmb();
664 
665 	if (!dma->channel_program(channel, pkt_size, mode,
666 			urb->transfer_dma + offset, length)) {
667 		dma->channel_release(channel);
668 		hw_ep->tx_channel = NULL;
669 
670 		csr = musb_readw(epio, MUSB_TXCSR);
671 		csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
672 		musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
673 		return false;
674 	}
675 	return true;
676 }
677 
678 /*
679  * Program an HDRC endpoint as per the given URB
680  * Context: irqs blocked, controller lock held
681  */
682 static void musb_ep_program(struct musb *musb, u8 epnum,
683 			struct urb *urb, int is_out,
684 			u8 *buf, u32 offset, u32 len)
685 {
686 	struct dma_controller	*dma_controller;
687 	struct dma_channel	*dma_channel;
688 	u8			dma_ok;
689 	void __iomem		*mbase = musb->mregs;
690 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
691 	void __iomem		*epio = hw_ep->regs;
692 	struct musb_qh		*qh = musb_ep_get_qh(hw_ep, !is_out);
693 	u16			packet_sz = qh->maxpacket;
694 
695 	dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
696 				"h_addr%02x h_port%02x bytes %d\n",
697 			is_out ? "-->" : "<--",
698 			epnum, urb, urb->dev->speed,
699 			qh->addr_reg, qh->epnum, is_out ? "out" : "in",
700 			qh->h_addr_reg, qh->h_port_reg,
701 			len);
702 
703 	musb_ep_select(mbase, epnum);
704 
705 	/* candidate for DMA? */
706 	dma_controller = musb->dma_controller;
707 	if (is_dma_capable() && epnum && dma_controller) {
708 		dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
709 		if (!dma_channel) {
710 			dma_channel = dma_controller->channel_alloc(
711 					dma_controller, hw_ep, is_out);
712 			if (is_out)
713 				hw_ep->tx_channel = dma_channel;
714 			else
715 				hw_ep->rx_channel = dma_channel;
716 		}
717 	} else
718 		dma_channel = NULL;
719 
720 	/* make sure we clear DMAEnab, autoSet bits from previous run */
721 
722 	/* OUT/transmit/EP0 or IN/receive? */
723 	if (is_out) {
724 		u16	csr;
725 		u16	int_txe;
726 		u16	load_count;
727 
728 		csr = musb_readw(epio, MUSB_TXCSR);
729 
730 		/* disable interrupt in case we flush */
731 		int_txe = musb_readw(mbase, MUSB_INTRTXE);
732 		musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
733 
734 		/* general endpoint setup */
735 		if (epnum) {
736 			/* flush all old state, set default */
737 			musb_h_tx_flush_fifo(hw_ep);
738 
739 			/*
740 			 * We must not clear the DMAMODE bit before or in
741 			 * the same cycle with the DMAENAB bit, so we clear
742 			 * the latter first...
743 			 */
744 			csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
745 					| MUSB_TXCSR_AUTOSET
746 					| MUSB_TXCSR_DMAENAB
747 					| MUSB_TXCSR_FRCDATATOG
748 					| MUSB_TXCSR_H_RXSTALL
749 					| MUSB_TXCSR_H_ERROR
750 					| MUSB_TXCSR_TXPKTRDY
751 					);
752 			csr |= MUSB_TXCSR_MODE;
753 
754 			if (usb_gettoggle(urb->dev, qh->epnum, 1))
755 				csr |= MUSB_TXCSR_H_WR_DATATOGGLE
756 					| MUSB_TXCSR_H_DATATOGGLE;
757 			else
758 				csr |= MUSB_TXCSR_CLRDATATOG;
759 
760 			musb_writew(epio, MUSB_TXCSR, csr);
761 			/* REVISIT may need to clear FLUSHFIFO ... */
762 			csr &= ~MUSB_TXCSR_DMAMODE;
763 			musb_writew(epio, MUSB_TXCSR, csr);
764 			csr = musb_readw(epio, MUSB_TXCSR);
765 		} else {
766 			/* endpoint 0: just flush */
767 			musb_h_ep0_flush_fifo(hw_ep);
768 		}
769 
770 		/* target addr and (for multipoint) hub addr/port */
771 		if (musb->is_multipoint) {
772 			musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
773 			musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
774 			musb_write_txhubport(mbase, epnum, qh->h_port_reg);
775 /* FIXME if !epnum, do the same for RX ... */
776 		} else
777 			musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
778 
779 		/* protocol/endpoint/interval/NAKlimit */
780 		if (epnum) {
781 			musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
782 			if (musb->double_buffer_not_ok)
783 				musb_writew(epio, MUSB_TXMAXP,
784 						hw_ep->max_packet_sz_tx);
785 			else if (can_bulk_split(musb, qh->type))
786 				musb_writew(epio, MUSB_TXMAXP, packet_sz
787 					| ((hw_ep->max_packet_sz_tx /
788 						packet_sz) - 1) << 11);
789 			else
790 				musb_writew(epio, MUSB_TXMAXP,
791 						qh->maxpacket |
792 						((qh->hb_mult - 1) << 11));
793 			musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
794 		} else {
795 			musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
796 			if (musb->is_multipoint)
797 				musb_writeb(epio, MUSB_TYPE0,
798 						qh->type_reg);
799 		}
800 
801 		if (can_bulk_split(musb, qh->type))
802 			load_count = min((u32) hw_ep->max_packet_sz_tx,
803 						len);
804 		else
805 			load_count = min((u32) packet_sz, len);
806 
807 		if (dma_channel && musb_tx_dma_program(dma_controller,
808 					hw_ep, qh, urb, offset, len))
809 			load_count = 0;
810 
811 		if (load_count) {
812 			/* PIO to load FIFO */
813 			qh->segsize = load_count;
814 			musb_write_fifo(hw_ep, load_count, buf);
815 		}
816 
817 		/* re-enable interrupt */
818 		musb_writew(mbase, MUSB_INTRTXE, int_txe);
819 
820 	/* IN/receive */
821 	} else {
822 		u16	csr;
823 
824 		if (hw_ep->rx_reinit) {
825 			musb_rx_reinit(musb, qh, hw_ep);
826 
827 			/* init new state: toggle and NYET, maybe DMA later */
828 			if (usb_gettoggle(urb->dev, qh->epnum, 0))
829 				csr = MUSB_RXCSR_H_WR_DATATOGGLE
830 					| MUSB_RXCSR_H_DATATOGGLE;
831 			else
832 				csr = 0;
833 			if (qh->type == USB_ENDPOINT_XFER_INT)
834 				csr |= MUSB_RXCSR_DISNYET;
835 
836 		} else {
837 			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
838 
839 			if (csr & (MUSB_RXCSR_RXPKTRDY
840 					| MUSB_RXCSR_DMAENAB
841 					| MUSB_RXCSR_H_REQPKT))
842 				ERR("broken !rx_reinit, ep%d csr %04x\n",
843 						hw_ep->epnum, csr);
844 
845 			/* scrub any stale state, leaving toggle alone */
846 			csr &= MUSB_RXCSR_DISNYET;
847 		}
848 
849 		/* kick things off */
850 
851 		if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
852 			/* Candidate for DMA */
853 			dma_channel->actual_len = 0L;
854 			qh->segsize = len;
855 
856 			/* AUTOREQ is in a DMA register */
857 			musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
858 			csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
859 
860 			/*
861 			 * Unless caller treats short RX transfers as
862 			 * errors, we dare not queue multiple transfers.
863 			 */
864 			dma_ok = dma_controller->channel_program(dma_channel,
865 					packet_sz, !(urb->transfer_flags &
866 						     URB_SHORT_NOT_OK),
867 					urb->transfer_dma + offset,
868 					qh->segsize);
869 			if (!dma_ok) {
870 				dma_controller->channel_release(dma_channel);
871 				hw_ep->rx_channel = dma_channel = NULL;
872 			} else
873 				csr |= MUSB_RXCSR_DMAENAB;
874 		}
875 
876 		csr |= MUSB_RXCSR_H_REQPKT;
877 		dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
878 		musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
879 		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
880 	}
881 }
882 
883 
884 /*
885  * Service the default endpoint (ep0) as host.
886  * Return true until it's time to start the status stage.
887  */
888 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
889 {
890 	bool			 more = false;
891 	u8			*fifo_dest = NULL;
892 	u16			fifo_count = 0;
893 	struct musb_hw_ep	*hw_ep = musb->control_ep;
894 	struct musb_qh		*qh = hw_ep->in_qh;
895 	struct usb_ctrlrequest	*request;
896 
897 	switch (musb->ep0_stage) {
898 	case MUSB_EP0_IN:
899 		fifo_dest = urb->transfer_buffer + urb->actual_length;
900 		fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
901 				   urb->actual_length);
902 		if (fifo_count < len)
903 			urb->status = -EOVERFLOW;
904 
905 		musb_read_fifo(hw_ep, fifo_count, fifo_dest);
906 
907 		urb->actual_length += fifo_count;
908 		if (len < qh->maxpacket) {
909 			/* always terminate on short read; it's
910 			 * rarely reported as an error.
911 			 */
912 		} else if (urb->actual_length <
913 				urb->transfer_buffer_length)
914 			more = true;
915 		break;
916 	case MUSB_EP0_START:
917 		request = (struct usb_ctrlrequest *) urb->setup_packet;
918 
919 		if (!request->wLength) {
920 			dev_dbg(musb->controller, "start no-DATA\n");
921 			break;
922 		} else if (request->bRequestType & USB_DIR_IN) {
923 			dev_dbg(musb->controller, "start IN-DATA\n");
924 			musb->ep0_stage = MUSB_EP0_IN;
925 			more = true;
926 			break;
927 		} else {
928 			dev_dbg(musb->controller, "start OUT-DATA\n");
929 			musb->ep0_stage = MUSB_EP0_OUT;
930 			more = true;
931 		}
932 		/* FALLTHROUGH */
933 	case MUSB_EP0_OUT:
934 		fifo_count = min_t(size_t, qh->maxpacket,
935 				   urb->transfer_buffer_length -
936 				   urb->actual_length);
937 		if (fifo_count) {
938 			fifo_dest = (u8 *) (urb->transfer_buffer
939 					+ urb->actual_length);
940 			dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
941 					fifo_count,
942 					(fifo_count == 1) ? "" : "s",
943 					fifo_dest);
944 			musb_write_fifo(hw_ep, fifo_count, fifo_dest);
945 
946 			urb->actual_length += fifo_count;
947 			more = true;
948 		}
949 		break;
950 	default:
951 		ERR("bogus ep0 stage %d\n", musb->ep0_stage);
952 		break;
953 	}
954 
955 	return more;
956 }
957 
958 /*
959  * Handle default endpoint interrupt as host. Only called in IRQ time
960  * from musb_interrupt().
961  *
962  * called with controller irqlocked
963  */
964 irqreturn_t musb_h_ep0_irq(struct musb *musb)
965 {
966 	struct urb		*urb;
967 	u16			csr, len;
968 	int			status = 0;
969 	void __iomem		*mbase = musb->mregs;
970 	struct musb_hw_ep	*hw_ep = musb->control_ep;
971 	void __iomem		*epio = hw_ep->regs;
972 	struct musb_qh		*qh = hw_ep->in_qh;
973 	bool			complete = false;
974 	irqreturn_t		retval = IRQ_NONE;
975 
976 	/* ep0 only has one queue, "in" */
977 	urb = next_urb(qh);
978 
979 	musb_ep_select(mbase, 0);
980 	csr = musb_readw(epio, MUSB_CSR0);
981 	len = (csr & MUSB_CSR0_RXPKTRDY)
982 			? musb_readb(epio, MUSB_COUNT0)
983 			: 0;
984 
985 	dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
986 		csr, qh, len, urb, musb->ep0_stage);
987 
988 	/* if we just did status stage, we are done */
989 	if (MUSB_EP0_STATUS == musb->ep0_stage) {
990 		retval = IRQ_HANDLED;
991 		complete = true;
992 	}
993 
994 	/* prepare status */
995 	if (csr & MUSB_CSR0_H_RXSTALL) {
996 		dev_dbg(musb->controller, "STALLING ENDPOINT\n");
997 		status = -EPIPE;
998 
999 	} else if (csr & MUSB_CSR0_H_ERROR) {
1000 		dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1001 		status = -EPROTO;
1002 
1003 	} else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1004 		dev_dbg(musb->controller, "control NAK timeout\n");
1005 
1006 		/* NOTE:  this code path would be a good place to PAUSE a
1007 		 * control transfer, if another one is queued, so that
1008 		 * ep0 is more likely to stay busy.  That's already done
1009 		 * for bulk RX transfers.
1010 		 *
1011 		 * if (qh->ring.next != &musb->control), then
1012 		 * we have a candidate... NAKing is *NOT* an error
1013 		 */
1014 		musb_writew(epio, MUSB_CSR0, 0);
1015 		retval = IRQ_HANDLED;
1016 	}
1017 
1018 	if (status) {
1019 		dev_dbg(musb->controller, "aborting\n");
1020 		retval = IRQ_HANDLED;
1021 		if (urb)
1022 			urb->status = status;
1023 		complete = true;
1024 
1025 		/* use the proper sequence to abort the transfer */
1026 		if (csr & MUSB_CSR0_H_REQPKT) {
1027 			csr &= ~MUSB_CSR0_H_REQPKT;
1028 			musb_writew(epio, MUSB_CSR0, csr);
1029 			csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1030 			musb_writew(epio, MUSB_CSR0, csr);
1031 		} else {
1032 			musb_h_ep0_flush_fifo(hw_ep);
1033 		}
1034 
1035 		musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1036 
1037 		/* clear it */
1038 		musb_writew(epio, MUSB_CSR0, 0);
1039 	}
1040 
1041 	if (unlikely(!urb)) {
1042 		/* stop endpoint since we have no place for its data, this
1043 		 * SHOULD NEVER HAPPEN! */
1044 		ERR("no URB for end 0\n");
1045 
1046 		musb_h_ep0_flush_fifo(hw_ep);
1047 		goto done;
1048 	}
1049 
1050 	if (!complete) {
1051 		/* call common logic and prepare response */
1052 		if (musb_h_ep0_continue(musb, len, urb)) {
1053 			/* more packets required */
1054 			csr = (MUSB_EP0_IN == musb->ep0_stage)
1055 				?  MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1056 		} else {
1057 			/* data transfer complete; perform status phase */
1058 			if (usb_pipeout(urb->pipe)
1059 					|| !urb->transfer_buffer_length)
1060 				csr = MUSB_CSR0_H_STATUSPKT
1061 					| MUSB_CSR0_H_REQPKT;
1062 			else
1063 				csr = MUSB_CSR0_H_STATUSPKT
1064 					| MUSB_CSR0_TXPKTRDY;
1065 
1066 			/* flag status stage */
1067 			musb->ep0_stage = MUSB_EP0_STATUS;
1068 
1069 			dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1070 
1071 		}
1072 		musb_writew(epio, MUSB_CSR0, csr);
1073 		retval = IRQ_HANDLED;
1074 	} else
1075 		musb->ep0_stage = MUSB_EP0_IDLE;
1076 
1077 	/* call completion handler if done */
1078 	if (complete)
1079 		musb_advance_schedule(musb, urb, hw_ep, 1);
1080 done:
1081 	return retval;
1082 }
1083 
1084 
1085 #ifdef CONFIG_USB_INVENTRA_DMA
1086 
1087 /* Host side TX (OUT) using Mentor DMA works as follows:
1088 	submit_urb ->
1089 		- if queue was empty, Program Endpoint
1090 		- ... which starts DMA to fifo in mode 1 or 0
1091 
1092 	DMA Isr (transfer complete) -> TxAvail()
1093 		- Stop DMA (~DmaEnab)	(<--- Alert ... currently happens
1094 					only in musb_cleanup_urb)
1095 		- TxPktRdy has to be set in mode 0 or for
1096 			short packets in mode 1.
1097 */
1098 
1099 #endif
1100 
1101 /* Service a Tx-Available or dma completion irq for the endpoint */
1102 void musb_host_tx(struct musb *musb, u8 epnum)
1103 {
1104 	int			pipe;
1105 	bool			done = false;
1106 	u16			tx_csr;
1107 	size_t			length = 0;
1108 	size_t			offset = 0;
1109 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
1110 	void __iomem		*epio = hw_ep->regs;
1111 	struct musb_qh		*qh = hw_ep->out_qh;
1112 	struct urb		*urb = next_urb(qh);
1113 	u32			status = 0;
1114 	void __iomem		*mbase = musb->mregs;
1115 	struct dma_channel	*dma;
1116 	bool			transfer_pending = false;
1117 
1118 	musb_ep_select(mbase, epnum);
1119 	tx_csr = musb_readw(epio, MUSB_TXCSR);
1120 
1121 	/* with CPPI, DMA sometimes triggers "extra" irqs */
1122 	if (!urb) {
1123 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1124 		return;
1125 	}
1126 
1127 	pipe = urb->pipe;
1128 	dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1129 	dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1130 			dma ? ", dma" : "");
1131 
1132 	/* check for errors */
1133 	if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1134 		/* dma was disabled, fifo flushed */
1135 		dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1136 
1137 		/* stall; record URB status */
1138 		status = -EPIPE;
1139 
1140 	} else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1141 		/* (NON-ISO) dma was disabled, fifo flushed */
1142 		dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1143 
1144 		status = -ETIMEDOUT;
1145 
1146 	} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1147 		dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
1148 
1149 		/* NOTE:  this code path would be a good place to PAUSE a
1150 		 * transfer, if there's some other (nonperiodic) tx urb
1151 		 * that could use this fifo.  (dma complicates it...)
1152 		 * That's already done for bulk RX transfers.
1153 		 *
1154 		 * if (bulk && qh->ring.next != &musb->out_bulk), then
1155 		 * we have a candidate... NAKing is *NOT* an error
1156 		 */
1157 		musb_ep_select(mbase, epnum);
1158 		musb_writew(epio, MUSB_TXCSR,
1159 				MUSB_TXCSR_H_WZC_BITS
1160 				| MUSB_TXCSR_TXPKTRDY);
1161 		return;
1162 	}
1163 
1164 	if (status) {
1165 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1166 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1167 			(void) musb->dma_controller->channel_abort(dma);
1168 		}
1169 
1170 		/* do the proper sequence to abort the transfer in the
1171 		 * usb core; the dma engine should already be stopped.
1172 		 */
1173 		musb_h_tx_flush_fifo(hw_ep);
1174 		tx_csr &= ~(MUSB_TXCSR_AUTOSET
1175 				| MUSB_TXCSR_DMAENAB
1176 				| MUSB_TXCSR_H_ERROR
1177 				| MUSB_TXCSR_H_RXSTALL
1178 				| MUSB_TXCSR_H_NAKTIMEOUT
1179 				);
1180 
1181 		musb_ep_select(mbase, epnum);
1182 		musb_writew(epio, MUSB_TXCSR, tx_csr);
1183 		/* REVISIT may need to clear FLUSHFIFO ... */
1184 		musb_writew(epio, MUSB_TXCSR, tx_csr);
1185 		musb_writeb(epio, MUSB_TXINTERVAL, 0);
1186 
1187 		done = true;
1188 	}
1189 
1190 	/* second cppi case */
1191 	if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1192 		dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1193 		return;
1194 	}
1195 
1196 	if (is_dma_capable() && dma && !status) {
1197 		/*
1198 		 * DMA has completed.  But if we're using DMA mode 1 (multi
1199 		 * packet DMA), we need a terminal TXPKTRDY interrupt before
1200 		 * we can consider this transfer completed, lest we trash
1201 		 * its last packet when writing the next URB's data.  So we
1202 		 * switch back to mode 0 to get that interrupt; we'll come
1203 		 * back here once it happens.
1204 		 */
1205 		if (tx_csr & MUSB_TXCSR_DMAMODE) {
1206 			/*
1207 			 * We shouldn't clear DMAMODE with DMAENAB set; so
1208 			 * clear them in a safe order.  That should be OK
1209 			 * once TXPKTRDY has been set (and I've never seen
1210 			 * it being 0 at this moment -- DMA interrupt latency
1211 			 * is significant) but if it hasn't been then we have
1212 			 * no choice but to stop being polite and ignore the
1213 			 * programmer's guide... :-)
1214 			 *
1215 			 * Note that we must write TXCSR with TXPKTRDY cleared
1216 			 * in order not to re-trigger the packet send (this bit
1217 			 * can't be cleared by CPU), and there's another caveat:
1218 			 * TXPKTRDY may be set shortly and then cleared in the
1219 			 * double-buffered FIFO mode, so we do an extra TXCSR
1220 			 * read for debouncing...
1221 			 */
1222 			tx_csr &= musb_readw(epio, MUSB_TXCSR);
1223 			if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1224 				tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1225 					    MUSB_TXCSR_TXPKTRDY);
1226 				musb_writew(epio, MUSB_TXCSR,
1227 					    tx_csr | MUSB_TXCSR_H_WZC_BITS);
1228 			}
1229 			tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1230 				    MUSB_TXCSR_TXPKTRDY);
1231 			musb_writew(epio, MUSB_TXCSR,
1232 				    tx_csr | MUSB_TXCSR_H_WZC_BITS);
1233 
1234 			/*
1235 			 * There is no guarantee that we'll get an interrupt
1236 			 * after clearing DMAMODE as we might have done this
1237 			 * too late (after TXPKTRDY was cleared by controller).
1238 			 * Re-read TXCSR as we have spoiled its previous value.
1239 			 */
1240 			tx_csr = musb_readw(epio, MUSB_TXCSR);
1241 		}
1242 
1243 		/*
1244 		 * We may get here from a DMA completion or TXPKTRDY interrupt.
1245 		 * In any case, we must check the FIFO status here and bail out
1246 		 * only if the FIFO still has data -- that should prevent the
1247 		 * "missed" TXPKTRDY interrupts and deal with double-buffered
1248 		 * FIFO mode too...
1249 		 */
1250 		if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1251 			dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1252 			    "CSR %04x\n", tx_csr);
1253 			return;
1254 		}
1255 	}
1256 
1257 	if (!status || dma || usb_pipeisoc(pipe)) {
1258 		if (dma)
1259 			length = dma->actual_len;
1260 		else
1261 			length = qh->segsize;
1262 		qh->offset += length;
1263 
1264 		if (usb_pipeisoc(pipe)) {
1265 #ifndef __UBOOT__
1266 			struct usb_iso_packet_descriptor	*d;
1267 
1268 			d = urb->iso_frame_desc + qh->iso_idx;
1269 			d->actual_length = length;
1270 			d->status = status;
1271 			if (++qh->iso_idx >= urb->number_of_packets) {
1272 				done = true;
1273 			} else {
1274 				d++;
1275 				offset = d->offset;
1276 				length = d->length;
1277 			}
1278 #endif
1279 		} else if (dma && urb->transfer_buffer_length == qh->offset) {
1280 			done = true;
1281 		} else {
1282 			/* see if we need to send more data, or ZLP */
1283 			if (qh->segsize < qh->maxpacket)
1284 				done = true;
1285 			else if (qh->offset == urb->transfer_buffer_length
1286 					&& !(urb->transfer_flags
1287 						& URB_ZERO_PACKET))
1288 				done = true;
1289 			if (!done) {
1290 				offset = qh->offset;
1291 				length = urb->transfer_buffer_length - offset;
1292 				transfer_pending = true;
1293 			}
1294 		}
1295 	}
1296 
1297 	/* urb->status != -EINPROGRESS means request has been faulted,
1298 	 * so we must abort this transfer after cleanup
1299 	 */
1300 	if (urb->status != -EINPROGRESS) {
1301 		done = true;
1302 		if (status == 0)
1303 			status = urb->status;
1304 	}
1305 
1306 	if (done) {
1307 		/* set status */
1308 		urb->status = status;
1309 		urb->actual_length = qh->offset;
1310 		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1311 		return;
1312 	} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1313 		if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1314 				offset, length)) {
1315 			if (is_cppi_enabled() || tusb_dma_omap())
1316 				musb_h_tx_dma_start(hw_ep);
1317 			return;
1318 		}
1319 	} else	if (tx_csr & MUSB_TXCSR_DMAENAB) {
1320 		dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1321 		return;
1322 	}
1323 
1324 	/*
1325 	 * PIO: start next packet in this URB.
1326 	 *
1327 	 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1328 	 * (and presumably, FIFO is not half-full) we should write *two*
1329 	 * packets before updating TXCSR; other docs disagree...
1330 	 */
1331 	if (length > qh->maxpacket)
1332 		length = qh->maxpacket;
1333 	/* Unmap the buffer so that CPU can use it */
1334 	usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1335 	musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1336 	qh->segsize = length;
1337 
1338 	musb_ep_select(mbase, epnum);
1339 	musb_writew(epio, MUSB_TXCSR,
1340 			MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1341 }
1342 
1343 
1344 #ifdef CONFIG_USB_INVENTRA_DMA
1345 
1346 /* Host side RX (IN) using Mentor DMA works as follows:
1347 	submit_urb ->
1348 		- if queue was empty, ProgramEndpoint
1349 		- first IN token is sent out (by setting ReqPkt)
1350 	LinuxIsr -> RxReady()
1351 	/\	=> first packet is received
1352 	|	- Set in mode 0 (DmaEnab, ~ReqPkt)
1353 	|		-> DMA Isr (transfer complete) -> RxReady()
1354 	|		    - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1355 	|		    - if urb not complete, send next IN token (ReqPkt)
1356 	|			   |		else complete urb.
1357 	|			   |
1358 	---------------------------
1359  *
1360  * Nuances of mode 1:
1361  *	For short packets, no ack (+RxPktRdy) is sent automatically
1362  *	(even if AutoClear is ON)
1363  *	For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1364  *	automatically => major problem, as collecting the next packet becomes
1365  *	difficult. Hence mode 1 is not used.
1366  *
1367  * REVISIT
1368  *	All we care about at this driver level is that
1369  *       (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1370  *       (b) termination conditions are: short RX, or buffer full;
1371  *       (c) fault modes include
1372  *           - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1373  *             (and that endpoint's dma queue stops immediately)
1374  *           - overflow (full, PLUS more bytes in the terminal packet)
1375  *
1376  *	So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1377  *	thus be a great candidate for using mode 1 ... for all but the
1378  *	last packet of one URB's transfer.
1379  */
1380 
1381 #endif
1382 
1383 /* Schedule next QH from musb->in_bulk and move the current qh to
1384  * the end; avoids starvation for other endpoints.
1385  */
1386 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1387 {
1388 	struct dma_channel	*dma;
1389 	struct urb		*urb;
1390 	void __iomem		*mbase = musb->mregs;
1391 	void __iomem		*epio = ep->regs;
1392 	struct musb_qh		*cur_qh, *next_qh;
1393 	u16			rx_csr;
1394 
1395 	musb_ep_select(mbase, ep->epnum);
1396 	dma = is_dma_capable() ? ep->rx_channel : NULL;
1397 
1398 	/* clear nak timeout bit */
1399 	rx_csr = musb_readw(epio, MUSB_RXCSR);
1400 	rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1401 	rx_csr &= ~MUSB_RXCSR_DATAERROR;
1402 	musb_writew(epio, MUSB_RXCSR, rx_csr);
1403 
1404 	cur_qh = first_qh(&musb->in_bulk);
1405 	if (cur_qh) {
1406 		urb = next_urb(cur_qh);
1407 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1408 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1409 			musb->dma_controller->channel_abort(dma);
1410 			urb->actual_length += dma->actual_len;
1411 			dma->actual_len = 0L;
1412 		}
1413 		musb_save_toggle(cur_qh, 1, urb);
1414 
1415 		/* move cur_qh to end of queue */
1416 		list_move_tail(&cur_qh->ring, &musb->in_bulk);
1417 
1418 		/* get the next qh from musb->in_bulk */
1419 		next_qh = first_qh(&musb->in_bulk);
1420 
1421 		/* set rx_reinit and schedule the next qh */
1422 		ep->rx_reinit = 1;
1423 		musb_start_urb(musb, 1, next_qh);
1424 	}
1425 }
1426 
1427 /*
1428  * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1429  * and high-bandwidth IN transfer cases.
1430  */
1431 void musb_host_rx(struct musb *musb, u8 epnum)
1432 {
1433 	struct urb		*urb;
1434 	struct musb_hw_ep	*hw_ep = musb->endpoints + epnum;
1435 	void __iomem		*epio = hw_ep->regs;
1436 	struct musb_qh		*qh = hw_ep->in_qh;
1437 	size_t			xfer_len;
1438 	void __iomem		*mbase = musb->mregs;
1439 	int			pipe;
1440 	u16			rx_csr, val;
1441 	bool			iso_err = false;
1442 	bool			done = false;
1443 	u32			status;
1444 	struct dma_channel	*dma;
1445 
1446 	musb_ep_select(mbase, epnum);
1447 
1448 	urb = next_urb(qh);
1449 	dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1450 	status = 0;
1451 	xfer_len = 0;
1452 
1453 	rx_csr = musb_readw(epio, MUSB_RXCSR);
1454 	val = rx_csr;
1455 
1456 	if (unlikely(!urb)) {
1457 		/* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1458 		 * usbtest #11 (unlinks) triggers it regularly, sometimes
1459 		 * with fifo full.  (Only with DMA??)
1460 		 */
1461 		dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1462 			musb_readw(epio, MUSB_RXCOUNT));
1463 		musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1464 		return;
1465 	}
1466 
1467 	pipe = urb->pipe;
1468 
1469 	dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1470 		epnum, rx_csr, urb->actual_length,
1471 		dma ? dma->actual_len : 0);
1472 
1473 	/* check for errors, concurrent stall & unlink is not really
1474 	 * handled yet! */
1475 	if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1476 		dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1477 
1478 		/* stall; record URB status */
1479 		status = -EPIPE;
1480 
1481 	} else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1482 		dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1483 
1484 		status = -EPROTO;
1485 		musb_writeb(epio, MUSB_RXINTERVAL, 0);
1486 
1487 	} else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1488 
1489 		if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1490 			dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1491 
1492 			/* NOTE: NAKing is *NOT* an error, so we want to
1493 			 * continue.  Except ... if there's a request for
1494 			 * another QH, use that instead of starving it.
1495 			 *
1496 			 * Devices like Ethernet and serial adapters keep
1497 			 * reads posted at all times, which will starve
1498 			 * other devices without this logic.
1499 			 */
1500 			if (usb_pipebulk(urb->pipe)
1501 					&& qh->mux == 1
1502 					&& !list_is_singular(&musb->in_bulk)) {
1503 				musb_bulk_rx_nak_timeout(musb, hw_ep);
1504 				return;
1505 			}
1506 			musb_ep_select(mbase, epnum);
1507 			rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1508 			rx_csr &= ~MUSB_RXCSR_DATAERROR;
1509 			musb_writew(epio, MUSB_RXCSR, rx_csr);
1510 
1511 			goto finish;
1512 		} else {
1513 			dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1514 			/* packet error reported later */
1515 			iso_err = true;
1516 		}
1517 	} else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1518 		dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1519 				epnum);
1520 		status = -EPROTO;
1521 	}
1522 
1523 	/* faults abort the transfer */
1524 	if (status) {
1525 		/* clean up dma and collect transfer count */
1526 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1527 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1528 			(void) musb->dma_controller->channel_abort(dma);
1529 			xfer_len = dma->actual_len;
1530 		}
1531 		musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1532 		musb_writeb(epio, MUSB_RXINTERVAL, 0);
1533 		done = true;
1534 		goto finish;
1535 	}
1536 
1537 	if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1538 		/* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1539 		ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1540 		goto finish;
1541 	}
1542 
1543 	/* thorough shutdown for now ... given more precise fault handling
1544 	 * and better queueing support, we might keep a DMA pipeline going
1545 	 * while processing this irq for earlier completions.
1546 	 */
1547 
1548 	/* FIXME this is _way_ too much in-line logic for Mentor DMA */
1549 
1550 #ifndef CONFIG_USB_INVENTRA_DMA
1551 	if (rx_csr & MUSB_RXCSR_H_REQPKT)  {
1552 		/* REVISIT this happened for a while on some short reads...
1553 		 * the cleanup still needs investigation... looks bad...
1554 		 * and also duplicates dma cleanup code above ... plus,
1555 		 * shouldn't this be the "half full" double buffer case?
1556 		 */
1557 		if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1558 			dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1559 			(void) musb->dma_controller->channel_abort(dma);
1560 			xfer_len = dma->actual_len;
1561 			done = true;
1562 		}
1563 
1564 		dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1565 				xfer_len, dma ? ", dma" : "");
1566 		rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1567 
1568 		musb_ep_select(mbase, epnum);
1569 		musb_writew(epio, MUSB_RXCSR,
1570 				MUSB_RXCSR_H_WZC_BITS | rx_csr);
1571 	}
1572 #endif
1573 	if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1574 		xfer_len = dma->actual_len;
1575 
1576 		val &= ~(MUSB_RXCSR_DMAENAB
1577 			| MUSB_RXCSR_H_AUTOREQ
1578 			| MUSB_RXCSR_AUTOCLEAR
1579 			| MUSB_RXCSR_RXPKTRDY);
1580 		musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1581 
1582 #ifdef CONFIG_USB_INVENTRA_DMA
1583 		if (usb_pipeisoc(pipe)) {
1584 			struct usb_iso_packet_descriptor *d;
1585 
1586 			d = urb->iso_frame_desc + qh->iso_idx;
1587 			d->actual_length = xfer_len;
1588 
1589 			/* even if there was an error, we did the dma
1590 			 * for iso_frame_desc->length
1591 			 */
1592 			if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1593 				d->status = 0;
1594 
1595 			if (++qh->iso_idx >= urb->number_of_packets)
1596 				done = true;
1597 			else
1598 				done = false;
1599 
1600 		} else  {
1601 		/* done if urb buffer is full or short packet is recd */
1602 		done = (urb->actual_length + xfer_len >=
1603 				urb->transfer_buffer_length
1604 			|| dma->actual_len < qh->maxpacket);
1605 		}
1606 
1607 		/* send IN token for next packet, without AUTOREQ */
1608 		if (!done) {
1609 			val |= MUSB_RXCSR_H_REQPKT;
1610 			musb_writew(epio, MUSB_RXCSR,
1611 				MUSB_RXCSR_H_WZC_BITS | val);
1612 		}
1613 
1614 		dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1615 			done ? "off" : "reset",
1616 			musb_readw(epio, MUSB_RXCSR),
1617 			musb_readw(epio, MUSB_RXCOUNT));
1618 #else
1619 		done = true;
1620 #endif
1621 	} else if (urb->status == -EINPROGRESS) {
1622 		/* if no errors, be sure a packet is ready for unloading */
1623 		if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1624 			status = -EPROTO;
1625 			ERR("Rx interrupt with no errors or packet!\n");
1626 
1627 			/* FIXME this is another "SHOULD NEVER HAPPEN" */
1628 
1629 /* SCRUB (RX) */
1630 			/* do the proper sequence to abort the transfer */
1631 			musb_ep_select(mbase, epnum);
1632 			val &= ~MUSB_RXCSR_H_REQPKT;
1633 			musb_writew(epio, MUSB_RXCSR, val);
1634 			goto finish;
1635 		}
1636 
1637 		/* we are expecting IN packets */
1638 #ifdef CONFIG_USB_INVENTRA_DMA
1639 		if (dma) {
1640 			struct dma_controller	*c;
1641 			u16			rx_count;
1642 			int			ret, length;
1643 			dma_addr_t		buf;
1644 
1645 			rx_count = musb_readw(epio, MUSB_RXCOUNT);
1646 
1647 			dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
1648 					epnum, rx_count,
1649 					urb->transfer_dma
1650 						+ urb->actual_length,
1651 					qh->offset,
1652 					urb->transfer_buffer_length);
1653 
1654 			c = musb->dma_controller;
1655 
1656 			if (usb_pipeisoc(pipe)) {
1657 				int d_status = 0;
1658 				struct usb_iso_packet_descriptor *d;
1659 
1660 				d = urb->iso_frame_desc + qh->iso_idx;
1661 
1662 				if (iso_err) {
1663 					d_status = -EILSEQ;
1664 					urb->error_count++;
1665 				}
1666 				if (rx_count > d->length) {
1667 					if (d_status == 0) {
1668 						d_status = -EOVERFLOW;
1669 						urb->error_count++;
1670 					}
1671 					dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1672 					    rx_count, d->length);
1673 
1674 					length = d->length;
1675 				} else
1676 					length = rx_count;
1677 				d->status = d_status;
1678 				buf = urb->transfer_dma + d->offset;
1679 			} else {
1680 				length = rx_count;
1681 				buf = urb->transfer_dma +
1682 						urb->actual_length;
1683 			}
1684 
1685 			dma->desired_mode = 0;
1686 #ifdef USE_MODE1
1687 			/* because of the issue below, mode 1 will
1688 			 * only rarely behave with correct semantics.
1689 			 */
1690 			if ((urb->transfer_flags &
1691 						URB_SHORT_NOT_OK)
1692 				&& (urb->transfer_buffer_length -
1693 						urb->actual_length)
1694 					> qh->maxpacket)
1695 				dma->desired_mode = 1;
1696 			if (rx_count < hw_ep->max_packet_sz_rx) {
1697 				length = rx_count;
1698 				dma->desired_mode = 0;
1699 			} else {
1700 				length = urb->transfer_buffer_length;
1701 			}
1702 #endif
1703 
1704 /* Disadvantage of using mode 1:
1705  *	It's basically usable only for mass storage class; essentially all
1706  *	other protocols also terminate transfers on short packets.
1707  *
1708  * Details:
1709  *	An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1710  *	If you try to use mode 1 for (transfer_buffer_length - 512), and try
1711  *	to use the extra IN token to grab the last packet using mode 0, then
1712  *	the problem is that you cannot be sure when the device will send the
1713  *	last packet and RxPktRdy set. Sometimes the packet is recd too soon
1714  *	such that it gets lost when RxCSR is re-set at the end of the mode 1
1715  *	transfer, while sometimes it is recd just a little late so that if you
1716  *	try to configure for mode 0 soon after the mode 1 transfer is
1717  *	completed, you will find rxcount 0. Okay, so you might think why not
1718  *	wait for an interrupt when the pkt is recd. Well, you won't get any!
1719  */
1720 
1721 			val = musb_readw(epio, MUSB_RXCSR);
1722 			val &= ~MUSB_RXCSR_H_REQPKT;
1723 
1724 			if (dma->desired_mode == 0)
1725 				val &= ~MUSB_RXCSR_H_AUTOREQ;
1726 			else
1727 				val |= MUSB_RXCSR_H_AUTOREQ;
1728 			val |= MUSB_RXCSR_DMAENAB;
1729 
1730 			/* autoclear shouldn't be set in high bandwidth */
1731 			if (qh->hb_mult == 1)
1732 				val |= MUSB_RXCSR_AUTOCLEAR;
1733 
1734 			musb_writew(epio, MUSB_RXCSR,
1735 				MUSB_RXCSR_H_WZC_BITS | val);
1736 
1737 			/* REVISIT if when actual_length != 0,
1738 			 * transfer_buffer_length needs to be
1739 			 * adjusted first...
1740 			 */
1741 			ret = c->channel_program(
1742 				dma, qh->maxpacket,
1743 				dma->desired_mode, buf, length);
1744 
1745 			if (!ret) {
1746 				c->channel_release(dma);
1747 				hw_ep->rx_channel = NULL;
1748 				dma = NULL;
1749 				val = musb_readw(epio, MUSB_RXCSR);
1750 				val &= ~(MUSB_RXCSR_DMAENAB
1751 					| MUSB_RXCSR_H_AUTOREQ
1752 					| MUSB_RXCSR_AUTOCLEAR);
1753 				musb_writew(epio, MUSB_RXCSR, val);
1754 			}
1755 		}
1756 #endif	/* Mentor DMA */
1757 
1758 		if (!dma) {
1759 			/* Unmap the buffer so that CPU can use it */
1760 			usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1761 			done = musb_host_packet_rx(musb, urb,
1762 					epnum, iso_err);
1763 			dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1764 		}
1765 	}
1766 
1767 finish:
1768 	urb->actual_length += xfer_len;
1769 	qh->offset += xfer_len;
1770 	if (done) {
1771 		if (urb->status == -EINPROGRESS)
1772 			urb->status = status;
1773 		musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1774 	}
1775 }
1776 
1777 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1778  * the software schedule associates multiple such nodes with a given
1779  * host side hardware endpoint + direction; scheduling may activate
1780  * that hardware endpoint.
1781  */
1782 static int musb_schedule(
1783 	struct musb		*musb,
1784 	struct musb_qh		*qh,
1785 	int			is_in)
1786 {
1787 	int			idle;
1788 	int			best_diff;
1789 	int			best_end, epnum;
1790 	struct musb_hw_ep	*hw_ep = NULL;
1791 	struct list_head	*head = NULL;
1792 	u8			toggle;
1793 	u8			txtype;
1794 	struct urb		*urb = next_urb(qh);
1795 
1796 	/* use fixed hardware for control and bulk */
1797 	if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1798 		head = &musb->control;
1799 		hw_ep = musb->control_ep;
1800 		goto success;
1801 	}
1802 
1803 	/* else, periodic transfers get muxed to other endpoints */
1804 
1805 	/*
1806 	 * We know this qh hasn't been scheduled, so all we need to do
1807 	 * is choose which hardware endpoint to put it on ...
1808 	 *
1809 	 * REVISIT what we really want here is a regular schedule tree
1810 	 * like e.g. OHCI uses.
1811 	 */
1812 	best_diff = 4096;
1813 	best_end = -1;
1814 
1815 	for (epnum = 1, hw_ep = musb->endpoints + 1;
1816 			epnum < musb->nr_endpoints;
1817 			epnum++, hw_ep++) {
1818 		int	diff;
1819 
1820 		if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1821 			continue;
1822 
1823 		if (hw_ep == musb->bulk_ep)
1824 			continue;
1825 
1826 		if (is_in)
1827 			diff = hw_ep->max_packet_sz_rx;
1828 		else
1829 			diff = hw_ep->max_packet_sz_tx;
1830 		diff -= (qh->maxpacket * qh->hb_mult);
1831 
1832 		if (diff >= 0 && best_diff > diff) {
1833 
1834 			/*
1835 			 * Mentor controller has a bug in that if we schedule
1836 			 * a BULK Tx transfer on an endpoint that had earlier
1837 			 * handled ISOC then the BULK transfer has to start on
1838 			 * a zero toggle.  If the BULK transfer starts on a 1
1839 			 * toggle then this transfer will fail as the mentor
1840 			 * controller starts the Bulk transfer on a 0 toggle
1841 			 * irrespective of the programming of the toggle bits
1842 			 * in the TXCSR register.  Check for this condition
1843 			 * while allocating the EP for a Tx Bulk transfer.  If
1844 			 * so skip this EP.
1845 			 */
1846 			hw_ep = musb->endpoints + epnum;
1847 			toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1848 			txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1849 					>> 4) & 0x3;
1850 			if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1851 				toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1852 				continue;
1853 
1854 			best_diff = diff;
1855 			best_end = epnum;
1856 		}
1857 	}
1858 	/* use bulk reserved ep1 if no other ep is free */
1859 	if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1860 		hw_ep = musb->bulk_ep;
1861 		if (is_in)
1862 			head = &musb->in_bulk;
1863 		else
1864 			head = &musb->out_bulk;
1865 
1866 		/* Enable bulk RX NAK timeout scheme when bulk requests are
1867 		 * multiplexed.  This scheme doen't work in high speed to full
1868 		 * speed scenario as NAK interrupts are not coming from a
1869 		 * full speed device connected to a high speed device.
1870 		 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1871 		 * 4 (8 frame or 8ms) for FS device.
1872 		 */
1873 		if (is_in && qh->dev)
1874 			qh->intv_reg =
1875 				(USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1876 		goto success;
1877 	} else if (best_end < 0) {
1878 		return -ENOSPC;
1879 	}
1880 
1881 	idle = 1;
1882 	qh->mux = 0;
1883 	hw_ep = musb->endpoints + best_end;
1884 	dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
1885 success:
1886 	if (head) {
1887 		idle = list_empty(head);
1888 		list_add_tail(&qh->ring, head);
1889 		qh->mux = 1;
1890 	}
1891 	qh->hw_ep = hw_ep;
1892 	qh->hep->hcpriv = qh;
1893 	if (idle)
1894 		musb_start_urb(musb, is_in, qh);
1895 	return 0;
1896 }
1897 
1898 #ifdef __UBOOT__
1899 /* check if transaction translator is needed for device */
1900 static int tt_needed(struct musb *musb, struct usb_device *dev)
1901 {
1902 	if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) &&
1903 			(dev->speed < USB_SPEED_HIGH))
1904 		return 1;
1905 	return 0;
1906 }
1907 #endif
1908 
1909 #ifndef __UBOOT__
1910 static int musb_urb_enqueue(
1911 #else
1912 int musb_urb_enqueue(
1913 #endif
1914 	struct usb_hcd			*hcd,
1915 	struct urb			*urb,
1916 	gfp_t				mem_flags)
1917 {
1918 	unsigned long			flags;
1919 	struct musb			*musb = hcd_to_musb(hcd);
1920 	struct usb_host_endpoint	*hep = urb->ep;
1921 	struct musb_qh			*qh;
1922 	struct usb_endpoint_descriptor	*epd = &hep->desc;
1923 	int				ret;
1924 	unsigned			type_reg;
1925 	unsigned			interval;
1926 
1927 	/* host role must be active */
1928 	if (!is_host_active(musb) || !musb->is_active)
1929 		return -ENODEV;
1930 
1931 	spin_lock_irqsave(&musb->lock, flags);
1932 	ret = usb_hcd_link_urb_to_ep(hcd, urb);
1933 	qh = ret ? NULL : hep->hcpriv;
1934 	if (qh)
1935 		urb->hcpriv = qh;
1936 	spin_unlock_irqrestore(&musb->lock, flags);
1937 
1938 	/* DMA mapping was already done, if needed, and this urb is on
1939 	 * hep->urb_list now ... so we're done, unless hep wasn't yet
1940 	 * scheduled onto a live qh.
1941 	 *
1942 	 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1943 	 * disabled, testing for empty qh->ring and avoiding qh setup costs
1944 	 * except for the first urb queued after a config change.
1945 	 */
1946 	if (qh || ret)
1947 		return ret;
1948 
1949 	/* Allocate and initialize qh, minimizing the work done each time
1950 	 * hw_ep gets reprogrammed, or with irqs blocked.  Then schedule it.
1951 	 *
1952 	 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1953 	 * for bugs in other kernel code to break this driver...
1954 	 */
1955 	qh = kzalloc(sizeof *qh, mem_flags);
1956 	if (!qh) {
1957 		spin_lock_irqsave(&musb->lock, flags);
1958 		usb_hcd_unlink_urb_from_ep(hcd, urb);
1959 		spin_unlock_irqrestore(&musb->lock, flags);
1960 		return -ENOMEM;
1961 	}
1962 
1963 	qh->hep = hep;
1964 	qh->dev = urb->dev;
1965 	INIT_LIST_HEAD(&qh->ring);
1966 	qh->is_ready = 1;
1967 
1968 	qh->maxpacket = usb_endpoint_maxp(epd);
1969 	qh->type = usb_endpoint_type(epd);
1970 
1971 	/* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1972 	 * Some musb cores don't support high bandwidth ISO transfers; and
1973 	 * we don't (yet!) support high bandwidth interrupt transfers.
1974 	 */
1975 	qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1976 	if (qh->hb_mult > 1) {
1977 		int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1978 
1979 		if (ok)
1980 			ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1981 				|| (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1982 		if (!ok) {
1983 			ret = -EMSGSIZE;
1984 			goto done;
1985 		}
1986 		qh->maxpacket &= 0x7ff;
1987 	}
1988 
1989 	qh->epnum = usb_endpoint_num(epd);
1990 
1991 	/* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1992 	qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1993 
1994 	/* precompute rxtype/txtype/type0 register */
1995 	type_reg = (qh->type << 4) | qh->epnum;
1996 	switch (urb->dev->speed) {
1997 	case USB_SPEED_LOW:
1998 		type_reg |= 0xc0;
1999 		break;
2000 	case USB_SPEED_FULL:
2001 		type_reg |= 0x80;
2002 		break;
2003 	default:
2004 		type_reg |= 0x40;
2005 	}
2006 	qh->type_reg = type_reg;
2007 
2008 	/* Precompute RXINTERVAL/TXINTERVAL register */
2009 	switch (qh->type) {
2010 	case USB_ENDPOINT_XFER_INT:
2011 		/*
2012 		 * Full/low speeds use the  linear encoding,
2013 		 * high speed uses the logarithmic encoding.
2014 		 */
2015 		if (urb->dev->speed <= USB_SPEED_FULL) {
2016 			interval = max_t(u8, epd->bInterval, 1);
2017 			break;
2018 		}
2019 		/* FALLTHROUGH */
2020 	case USB_ENDPOINT_XFER_ISOC:
2021 		/* ISO always uses logarithmic encoding */
2022 		interval = min_t(u8, epd->bInterval, 16);
2023 		break;
2024 	default:
2025 		/* REVISIT we actually want to use NAK limits, hinting to the
2026 		 * transfer scheduling logic to try some other qh, e.g. try
2027 		 * for 2 msec first:
2028 		 *
2029 		 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2030 		 *
2031 		 * The downside of disabling this is that transfer scheduling
2032 		 * gets VERY unfair for nonperiodic transfers; a misbehaving
2033 		 * peripheral could make that hurt.  That's perfectly normal
2034 		 * for reads from network or serial adapters ... so we have
2035 		 * partial NAKlimit support for bulk RX.
2036 		 *
2037 		 * The upside of disabling it is simpler transfer scheduling.
2038 		 */
2039 		interval = 0;
2040 	}
2041 	qh->intv_reg = interval;
2042 
2043 	/* precompute addressing for external hub/tt ports */
2044 	if (musb->is_multipoint) {
2045 #ifndef __UBOOT__
2046 		struct usb_device	*parent = urb->dev->parent;
2047 #else
2048 		struct usb_device	*parent = usb_dev_get_parent(urb->dev);
2049 #endif
2050 
2051 #ifndef __UBOOT__
2052 		if (parent != hcd->self.root_hub) {
2053 #else
2054 		if (parent) {
2055 #endif
2056 			qh->h_addr_reg = (u8) parent->devnum;
2057 
2058 #ifndef __UBOOT__
2059 			/* set up tt info if needed */
2060 			if (urb->dev->tt) {
2061 				qh->h_port_reg = (u8) urb->dev->ttport;
2062 				if (urb->dev->tt->hub)
2063 					qh->h_addr_reg =
2064 						(u8) urb->dev->tt->hub->devnum;
2065 				if (urb->dev->tt->multi)
2066 					qh->h_addr_reg |= 0x80;
2067 			}
2068 #else
2069 			if (tt_needed(musb, urb->dev)) {
2070 				uint8_t portnr = 0;
2071 				uint8_t hubaddr = 0;
2072 				usb_find_usb2_hub_address_port(urb->dev,
2073 							       &hubaddr,
2074 							       &portnr);
2075 				qh->h_addr_reg = hubaddr;
2076 				qh->h_port_reg = portnr;
2077 			}
2078 #endif
2079 		}
2080 	}
2081 
2082 	/* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2083 	 * until we get real dma queues (with an entry for each urb/buffer),
2084 	 * we only have work to do in the former case.
2085 	 */
2086 	spin_lock_irqsave(&musb->lock, flags);
2087 	if (hep->hcpriv) {
2088 		/* some concurrent activity submitted another urb to hep...
2089 		 * odd, rare, error prone, but legal.
2090 		 */
2091 		kfree(qh);
2092 		qh = NULL;
2093 		ret = 0;
2094 	} else
2095 		ret = musb_schedule(musb, qh,
2096 				epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2097 
2098 	if (ret == 0) {
2099 		urb->hcpriv = qh;
2100 		/* FIXME set urb->start_frame for iso/intr, it's tested in
2101 		 * musb_start_urb(), but otherwise only konicawc cares ...
2102 		 */
2103 	}
2104 	spin_unlock_irqrestore(&musb->lock, flags);
2105 
2106 done:
2107 	if (ret != 0) {
2108 		spin_lock_irqsave(&musb->lock, flags);
2109 		usb_hcd_unlink_urb_from_ep(hcd, urb);
2110 		spin_unlock_irqrestore(&musb->lock, flags);
2111 		kfree(qh);
2112 	}
2113 	return ret;
2114 }
2115 
2116 /*
2117  * abort a transfer that's at the head of a hardware queue.
2118  * called with controller locked, irqs blocked
2119  * that hardware queue advances to the next transfer, unless prevented
2120  */
2121 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2122 {
2123 	struct musb_hw_ep	*ep = qh->hw_ep;
2124 	struct musb		*musb = ep->musb;
2125 	void __iomem		*epio = ep->regs;
2126 	unsigned		hw_end = ep->epnum;
2127 	void __iomem		*regs = ep->musb->mregs;
2128 	int			is_in = usb_pipein(urb->pipe);
2129 	int			status = 0;
2130 	u16			csr;
2131 
2132 	musb_ep_select(regs, hw_end);
2133 
2134 	if (is_dma_capable()) {
2135 		struct dma_channel	*dma;
2136 
2137 		dma = is_in ? ep->rx_channel : ep->tx_channel;
2138 		if (dma) {
2139 			status = ep->musb->dma_controller->channel_abort(dma);
2140 			dev_dbg(musb->controller,
2141 				"abort %cX%d DMA for urb %p --> %d\n",
2142 				is_in ? 'R' : 'T', ep->epnum,
2143 				urb, status);
2144 			urb->actual_length += dma->actual_len;
2145 		}
2146 	}
2147 
2148 	/* turn off DMA requests, discard state, stop polling ... */
2149 	if (ep->epnum && is_in) {
2150 		/* giveback saves bulk toggle */
2151 		csr = musb_h_flush_rxfifo(ep, 0);
2152 
2153 		/* REVISIT we still get an irq; should likely clear the
2154 		 * endpoint's irq status here to avoid bogus irqs.
2155 		 * clearing that status is platform-specific...
2156 		 */
2157 	} else if (ep->epnum) {
2158 		musb_h_tx_flush_fifo(ep);
2159 		csr = musb_readw(epio, MUSB_TXCSR);
2160 		csr &= ~(MUSB_TXCSR_AUTOSET
2161 			| MUSB_TXCSR_DMAENAB
2162 			| MUSB_TXCSR_H_RXSTALL
2163 			| MUSB_TXCSR_H_NAKTIMEOUT
2164 			| MUSB_TXCSR_H_ERROR
2165 			| MUSB_TXCSR_TXPKTRDY);
2166 		musb_writew(epio, MUSB_TXCSR, csr);
2167 		/* REVISIT may need to clear FLUSHFIFO ... */
2168 		musb_writew(epio, MUSB_TXCSR, csr);
2169 		/* flush cpu writebuffer */
2170 		csr = musb_readw(epio, MUSB_TXCSR);
2171 	} else  {
2172 		musb_h_ep0_flush_fifo(ep);
2173 	}
2174 	if (status == 0)
2175 		musb_advance_schedule(ep->musb, urb, ep, is_in);
2176 	return status;
2177 }
2178 
2179 #ifndef __UBOOT__
2180 static int musb_urb_dequeue(
2181 #else
2182 int musb_urb_dequeue(
2183 #endif
2184 	struct usb_hcd *hcd,
2185 	struct urb *urb,
2186 	int status)
2187 {
2188 	struct musb		*musb = hcd_to_musb(hcd);
2189 	struct musb_qh		*qh;
2190 	unsigned long		flags;
2191 	int			is_in  = usb_pipein(urb->pipe);
2192 	int			ret;
2193 
2194 	dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2195 			usb_pipedevice(urb->pipe),
2196 			usb_pipeendpoint(urb->pipe),
2197 			is_in ? "in" : "out");
2198 
2199 	spin_lock_irqsave(&musb->lock, flags);
2200 	ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2201 	if (ret)
2202 		goto done;
2203 
2204 	qh = urb->hcpriv;
2205 	if (!qh)
2206 		goto done;
2207 
2208 	/*
2209 	 * Any URB not actively programmed into endpoint hardware can be
2210 	 * immediately given back; that's any URB not at the head of an
2211 	 * endpoint queue, unless someday we get real DMA queues.  And even
2212 	 * if it's at the head, it might not be known to the hardware...
2213 	 *
2214 	 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2215 	 * has already been updated.  This is a synchronous abort; it'd be
2216 	 * OK to hold off until after some IRQ, though.
2217 	 *
2218 	 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2219 	 */
2220 	if (!qh->is_ready
2221 			|| urb->urb_list.prev != &qh->hep->urb_list
2222 			|| musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2223 		int	ready = qh->is_ready;
2224 
2225 		qh->is_ready = 0;
2226 		musb_giveback(musb, urb, 0);
2227 		qh->is_ready = ready;
2228 
2229 		/* If nothing else (usually musb_giveback) is using it
2230 		 * and its URB list has emptied, recycle this qh.
2231 		 */
2232 		if (ready && list_empty(&qh->hep->urb_list)) {
2233 			qh->hep->hcpriv = NULL;
2234 			list_del(&qh->ring);
2235 			kfree(qh);
2236 		}
2237 	} else
2238 		ret = musb_cleanup_urb(urb, qh);
2239 done:
2240 	spin_unlock_irqrestore(&musb->lock, flags);
2241 	return ret;
2242 }
2243 
2244 #ifndef __UBOOT__
2245 /* disable an endpoint */
2246 static void
2247 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2248 {
2249 	u8			is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2250 	unsigned long		flags;
2251 	struct musb		*musb = hcd_to_musb(hcd);
2252 	struct musb_qh		*qh;
2253 	struct urb		*urb;
2254 
2255 	spin_lock_irqsave(&musb->lock, flags);
2256 
2257 	qh = hep->hcpriv;
2258 	if (qh == NULL)
2259 		goto exit;
2260 
2261 	/* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2262 
2263 	/* Kick the first URB off the hardware, if needed */
2264 	qh->is_ready = 0;
2265 	if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2266 		urb = next_urb(qh);
2267 
2268 		/* make software (then hardware) stop ASAP */
2269 		if (!urb->unlinked)
2270 			urb->status = -ESHUTDOWN;
2271 
2272 		/* cleanup */
2273 		musb_cleanup_urb(urb, qh);
2274 
2275 		/* Then nuke all the others ... and advance the
2276 		 * queue on hw_ep (e.g. bulk ring) when we're done.
2277 		 */
2278 		while (!list_empty(&hep->urb_list)) {
2279 			urb = next_urb(qh);
2280 			urb->status = -ESHUTDOWN;
2281 			musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2282 		}
2283 	} else {
2284 		/* Just empty the queue; the hardware is busy with
2285 		 * other transfers, and since !qh->is_ready nothing
2286 		 * will activate any of these as it advances.
2287 		 */
2288 		while (!list_empty(&hep->urb_list))
2289 			musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2290 
2291 		hep->hcpriv = NULL;
2292 		list_del(&qh->ring);
2293 		kfree(qh);
2294 	}
2295 exit:
2296 	spin_unlock_irqrestore(&musb->lock, flags);
2297 }
2298 
2299 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2300 {
2301 	struct musb	*musb = hcd_to_musb(hcd);
2302 
2303 	return musb_readw(musb->mregs, MUSB_FRAME);
2304 }
2305 
2306 static int musb_h_start(struct usb_hcd *hcd)
2307 {
2308 	struct musb	*musb = hcd_to_musb(hcd);
2309 
2310 	/* NOTE: musb_start() is called when the hub driver turns
2311 	 * on port power, or when (OTG) peripheral starts.
2312 	 */
2313 	hcd->state = HC_STATE_RUNNING;
2314 	musb->port1_status = 0;
2315 	return 0;
2316 }
2317 
2318 static void musb_h_stop(struct usb_hcd *hcd)
2319 {
2320 	musb_stop(hcd_to_musb(hcd));
2321 	hcd->state = HC_STATE_HALT;
2322 }
2323 
2324 static int musb_bus_suspend(struct usb_hcd *hcd)
2325 {
2326 	struct musb	*musb = hcd_to_musb(hcd);
2327 	u8		devctl;
2328 
2329 	if (!is_host_active(musb))
2330 		return 0;
2331 
2332 	switch (musb->xceiv->state) {
2333 	case OTG_STATE_A_SUSPEND:
2334 		return 0;
2335 	case OTG_STATE_A_WAIT_VRISE:
2336 		/* ID could be grounded even if there's no device
2337 		 * on the other end of the cable.  NOTE that the
2338 		 * A_WAIT_VRISE timers are messy with MUSB...
2339 		 */
2340 		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2341 		if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2342 			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2343 		break;
2344 	default:
2345 		break;
2346 	}
2347 
2348 	if (musb->is_active) {
2349 		WARNING("trying to suspend as %s while active\n",
2350 				otg_state_string(musb->xceiv->state));
2351 		return -EBUSY;
2352 	} else
2353 		return 0;
2354 }
2355 
2356 static int musb_bus_resume(struct usb_hcd *hcd)
2357 {
2358 	/* resuming child port does the work */
2359 	return 0;
2360 }
2361 
2362 const struct hc_driver musb_hc_driver = {
2363 	.description		= "musb-hcd",
2364 	.product_desc		= "MUSB HDRC host driver",
2365 	.hcd_priv_size		= sizeof(struct musb),
2366 	.flags			= HCD_USB2 | HCD_MEMORY,
2367 
2368 	/* not using irq handler or reset hooks from usbcore, since
2369 	 * those must be shared with peripheral code for OTG configs
2370 	 */
2371 
2372 	.start			= musb_h_start,
2373 	.stop			= musb_h_stop,
2374 
2375 	.get_frame_number	= musb_h_get_frame_number,
2376 
2377 	.urb_enqueue		= musb_urb_enqueue,
2378 	.urb_dequeue		= musb_urb_dequeue,
2379 	.endpoint_disable	= musb_h_disable,
2380 
2381 	.hub_status_data	= musb_hub_status_data,
2382 	.hub_control		= musb_hub_control,
2383 	.bus_suspend		= musb_bus_suspend,
2384 	.bus_resume		= musb_bus_resume,
2385 	/* .start_port_reset	= NULL, */
2386 	/* .hub_irq_enable	= NULL, */
2387 };
2388 #endif
2389