1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #ifndef __UBOOT__ 93 #include <linux/module.h> 94 #include <linux/kernel.h> 95 #include <linux/sched.h> 96 #include <linux/slab.h> 97 #include <linux/init.h> 98 #include <linux/list.h> 99 #include <linux/kobject.h> 100 #include <linux/prefetch.h> 101 #include <linux/platform_device.h> 102 #include <linux/io.h> 103 #else 104 #include <common.h> 105 #include <usb.h> 106 #include <asm/errno.h> 107 #include <linux/usb/ch9.h> 108 #include <linux/usb/gadget.h> 109 #include <linux/usb/musb.h> 110 #include <asm/io.h> 111 #include "linux-compat.h" 112 #include "usb-compat.h" 113 #endif 114 115 #include "musb_core.h" 116 117 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 118 119 120 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 121 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 122 123 #define MUSB_VERSION "6.0" 124 125 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 126 127 #define MUSB_DRIVER_NAME "musb-hdrc" 128 const char musb_driver_name[] = MUSB_DRIVER_NAME; 129 130 MODULE_DESCRIPTION(DRIVER_INFO); 131 MODULE_AUTHOR(DRIVER_AUTHOR); 132 MODULE_LICENSE("GPL"); 133 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 134 135 136 #ifndef __UBOOT__ 137 /*-------------------------------------------------------------------------*/ 138 139 static inline struct musb *dev_to_musb(struct device *dev) 140 { 141 return dev_get_drvdata(dev); 142 } 143 #endif 144 145 /*-------------------------------------------------------------------------*/ 146 147 #ifndef __UBOOT__ 148 #ifndef CONFIG_BLACKFIN 149 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 150 { 151 void __iomem *addr = phy->io_priv; 152 int i = 0; 153 u8 r; 154 u8 power; 155 int ret; 156 157 pm_runtime_get_sync(phy->io_dev); 158 159 /* Make sure the transceiver is not in low power mode */ 160 power = musb_readb(addr, MUSB_POWER); 161 power &= ~MUSB_POWER_SUSPENDM; 162 musb_writeb(addr, MUSB_POWER, power); 163 164 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 165 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 166 */ 167 168 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 170 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 171 172 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 173 & MUSB_ULPI_REG_CMPLT)) { 174 i++; 175 if (i == 10000) { 176 ret = -ETIMEDOUT; 177 goto out; 178 } 179 180 } 181 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 182 r &= ~MUSB_ULPI_REG_CMPLT; 183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 184 185 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 186 187 out: 188 pm_runtime_put(phy->io_dev); 189 190 return ret; 191 } 192 193 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 194 { 195 void __iomem *addr = phy->io_priv; 196 int i = 0; 197 u8 r = 0; 198 u8 power; 199 int ret = 0; 200 201 pm_runtime_get_sync(phy->io_dev); 202 203 /* Make sure the transceiver is not in low power mode */ 204 power = musb_readb(addr, MUSB_POWER); 205 power &= ~MUSB_POWER_SUSPENDM; 206 musb_writeb(addr, MUSB_POWER, power); 207 208 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 209 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 211 212 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 213 & MUSB_ULPI_REG_CMPLT)) { 214 i++; 215 if (i == 10000) { 216 ret = -ETIMEDOUT; 217 goto out; 218 } 219 } 220 221 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 222 r &= ~MUSB_ULPI_REG_CMPLT; 223 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 224 225 out: 226 pm_runtime_put(phy->io_dev); 227 228 return ret; 229 } 230 #else 231 #define musb_ulpi_read NULL 232 #define musb_ulpi_write NULL 233 #endif 234 235 static struct usb_phy_io_ops musb_ulpi_access = { 236 .read = musb_ulpi_read, 237 .write = musb_ulpi_write, 238 }; 239 #endif 240 241 /*-------------------------------------------------------------------------*/ 242 243 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 244 245 /* 246 * Load an endpoint's FIFO 247 */ 248 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 249 { 250 struct musb *musb = hw_ep->musb; 251 void __iomem *fifo = hw_ep->fifo; 252 253 prefetch((u8 *)src); 254 255 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 256 'T', hw_ep->epnum, fifo, len, src); 257 258 /* we can't assume unaligned reads work */ 259 if (likely((0x01 & (unsigned long) src) == 0)) { 260 u16 index = 0; 261 262 /* best case is 32bit-aligned source address */ 263 if ((0x02 & (unsigned long) src) == 0) { 264 if (len >= 4) { 265 writesl(fifo, src + index, len >> 2); 266 index += len & ~0x03; 267 } 268 if (len & 0x02) { 269 musb_writew(fifo, 0, *(u16 *)&src[index]); 270 index += 2; 271 } 272 } else { 273 if (len >= 2) { 274 writesw(fifo, src + index, len >> 1); 275 index += len & ~0x01; 276 } 277 } 278 if (len & 0x01) 279 musb_writeb(fifo, 0, src[index]); 280 } else { 281 /* byte aligned */ 282 writesb(fifo, src, len); 283 } 284 } 285 286 #if !defined(CONFIG_USB_MUSB_AM35X) 287 /* 288 * Unload an endpoint's FIFO 289 */ 290 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 291 { 292 struct musb *musb = hw_ep->musb; 293 void __iomem *fifo = hw_ep->fifo; 294 295 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 296 'R', hw_ep->epnum, fifo, len, dst); 297 298 /* we can't assume unaligned writes work */ 299 if (likely((0x01 & (unsigned long) dst) == 0)) { 300 u16 index = 0; 301 302 /* best case is 32bit-aligned destination address */ 303 if ((0x02 & (unsigned long) dst) == 0) { 304 if (len >= 4) { 305 readsl(fifo, dst, len >> 2); 306 index = len & ~0x03; 307 } 308 if (len & 0x02) { 309 *(u16 *)&dst[index] = musb_readw(fifo, 0); 310 index += 2; 311 } 312 } else { 313 if (len >= 2) { 314 readsw(fifo, dst, len >> 1); 315 index = len & ~0x01; 316 } 317 } 318 if (len & 0x01) 319 dst[index] = musb_readb(fifo, 0); 320 } else { 321 /* byte aligned */ 322 readsb(fifo, dst, len); 323 } 324 } 325 #endif 326 327 #endif /* normal PIO */ 328 329 330 /*-------------------------------------------------------------------------*/ 331 332 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 333 static const u8 musb_test_packet[53] = { 334 /* implicit SYNC then DATA0 to start */ 335 336 /* JKJKJKJK x9 */ 337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 338 /* JJKKJJKK x8 */ 339 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 340 /* JJJJKKKK x8 */ 341 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 342 /* JJJJJJJKKKKKKK x8 */ 343 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 344 /* JJJJJJJK x8 */ 345 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 346 /* JKKKKKKK x10, JK */ 347 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 348 349 /* implicit CRC16 then EOP to end */ 350 }; 351 352 void musb_load_testpacket(struct musb *musb) 353 { 354 void __iomem *regs = musb->endpoints[0].regs; 355 356 musb_ep_select(musb->mregs, 0); 357 musb_write_fifo(musb->control_ep, 358 sizeof(musb_test_packet), musb_test_packet); 359 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 360 } 361 362 #ifndef __UBOOT__ 363 /*-------------------------------------------------------------------------*/ 364 365 /* 366 * Handles OTG hnp timeouts, such as b_ase0_brst 367 */ 368 void musb_otg_timer_func(unsigned long data) 369 { 370 struct musb *musb = (struct musb *)data; 371 unsigned long flags; 372 373 spin_lock_irqsave(&musb->lock, flags); 374 switch (musb->xceiv->state) { 375 case OTG_STATE_B_WAIT_ACON: 376 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 377 musb_g_disconnect(musb); 378 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 379 musb->is_active = 0; 380 break; 381 case OTG_STATE_A_SUSPEND: 382 case OTG_STATE_A_WAIT_BCON: 383 dev_dbg(musb->controller, "HNP: %s timeout\n", 384 otg_state_string(musb->xceiv->state)); 385 musb_platform_set_vbus(musb, 0); 386 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 387 break; 388 default: 389 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 390 otg_state_string(musb->xceiv->state)); 391 } 392 musb->ignore_disconnect = 0; 393 spin_unlock_irqrestore(&musb->lock, flags); 394 } 395 396 /* 397 * Stops the HNP transition. Caller must take care of locking. 398 */ 399 void musb_hnp_stop(struct musb *musb) 400 { 401 struct usb_hcd *hcd = musb_to_hcd(musb); 402 void __iomem *mbase = musb->mregs; 403 u8 reg; 404 405 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 406 407 switch (musb->xceiv->state) { 408 case OTG_STATE_A_PERIPHERAL: 409 musb_g_disconnect(musb); 410 dev_dbg(musb->controller, "HNP: back to %s\n", 411 otg_state_string(musb->xceiv->state)); 412 break; 413 case OTG_STATE_B_HOST: 414 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 415 hcd->self.is_b_host = 0; 416 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 417 MUSB_DEV_MODE(musb); 418 reg = musb_readb(mbase, MUSB_POWER); 419 reg |= MUSB_POWER_SUSPENDM; 420 musb_writeb(mbase, MUSB_POWER, reg); 421 /* REVISIT: Start SESSION_REQUEST here? */ 422 break; 423 default: 424 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 425 otg_state_string(musb->xceiv->state)); 426 } 427 428 /* 429 * When returning to A state after HNP, avoid hub_port_rebounce(), 430 * which cause occasional OPT A "Did not receive reset after connect" 431 * errors. 432 */ 433 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 434 } 435 #endif 436 437 /* 438 * Interrupt Service Routine to record USB "global" interrupts. 439 * Since these do not happen often and signify things of 440 * paramount importance, it seems OK to check them individually; 441 * the order of the tests is specified in the manual 442 * 443 * @param musb instance pointer 444 * @param int_usb register contents 445 * @param devctl 446 * @param power 447 */ 448 449 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 450 u8 devctl, u8 power) 451 { 452 #ifndef __UBOOT__ 453 struct usb_otg *otg = musb->xceiv->otg; 454 #endif 455 irqreturn_t handled = IRQ_NONE; 456 457 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 458 int_usb); 459 460 #ifndef __UBOOT__ 461 /* in host mode, the peripheral may issue remote wakeup. 462 * in peripheral mode, the host may resume the link. 463 * spurious RESUME irqs happen too, paired with SUSPEND. 464 */ 465 if (int_usb & MUSB_INTR_RESUME) { 466 handled = IRQ_HANDLED; 467 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 468 469 if (devctl & MUSB_DEVCTL_HM) { 470 void __iomem *mbase = musb->mregs; 471 472 switch (musb->xceiv->state) { 473 case OTG_STATE_A_SUSPEND: 474 /* remote wakeup? later, GetPortStatus 475 * will stop RESUME signaling 476 */ 477 478 if (power & MUSB_POWER_SUSPENDM) { 479 /* spurious */ 480 musb->int_usb &= ~MUSB_INTR_SUSPEND; 481 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 482 break; 483 } 484 485 power &= ~MUSB_POWER_SUSPENDM; 486 musb_writeb(mbase, MUSB_POWER, 487 power | MUSB_POWER_RESUME); 488 489 musb->port1_status |= 490 (USB_PORT_STAT_C_SUSPEND << 16) 491 | MUSB_PORT_STAT_RESUME; 492 musb->rh_timer = jiffies 493 + msecs_to_jiffies(20); 494 495 musb->xceiv->state = OTG_STATE_A_HOST; 496 musb->is_active = 1; 497 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 498 break; 499 case OTG_STATE_B_WAIT_ACON: 500 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 501 musb->is_active = 1; 502 MUSB_DEV_MODE(musb); 503 break; 504 default: 505 WARNING("bogus %s RESUME (%s)\n", 506 "host", 507 otg_state_string(musb->xceiv->state)); 508 } 509 } else { 510 switch (musb->xceiv->state) { 511 case OTG_STATE_A_SUSPEND: 512 /* possibly DISCONNECT is upcoming */ 513 musb->xceiv->state = OTG_STATE_A_HOST; 514 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 515 break; 516 case OTG_STATE_B_WAIT_ACON: 517 case OTG_STATE_B_PERIPHERAL: 518 /* disconnect while suspended? we may 519 * not get a disconnect irq... 520 */ 521 if ((devctl & MUSB_DEVCTL_VBUS) 522 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 523 ) { 524 musb->int_usb |= MUSB_INTR_DISCONNECT; 525 musb->int_usb &= ~MUSB_INTR_SUSPEND; 526 break; 527 } 528 musb_g_resume(musb); 529 break; 530 case OTG_STATE_B_IDLE: 531 musb->int_usb &= ~MUSB_INTR_SUSPEND; 532 break; 533 default: 534 WARNING("bogus %s RESUME (%s)\n", 535 "peripheral", 536 otg_state_string(musb->xceiv->state)); 537 } 538 } 539 } 540 541 /* see manual for the order of the tests */ 542 if (int_usb & MUSB_INTR_SESSREQ) { 543 void __iomem *mbase = musb->mregs; 544 545 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 546 && (devctl & MUSB_DEVCTL_BDEVICE)) { 547 dev_dbg(musb->controller, "SessReq while on B state\n"); 548 return IRQ_HANDLED; 549 } 550 551 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 552 otg_state_string(musb->xceiv->state)); 553 554 /* IRQ arrives from ID pin sense or (later, if VBUS power 555 * is removed) SRP. responses are time critical: 556 * - turn on VBUS (with silicon-specific mechanism) 557 * - go through A_WAIT_VRISE 558 * - ... to A_WAIT_BCON. 559 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 560 */ 561 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 562 musb->ep0_stage = MUSB_EP0_START; 563 musb->xceiv->state = OTG_STATE_A_IDLE; 564 MUSB_HST_MODE(musb); 565 musb_platform_set_vbus(musb, 1); 566 567 handled = IRQ_HANDLED; 568 } 569 570 if (int_usb & MUSB_INTR_VBUSERROR) { 571 int ignore = 0; 572 573 /* During connection as an A-Device, we may see a short 574 * current spikes causing voltage drop, because of cable 575 * and peripheral capacitance combined with vbus draw. 576 * (So: less common with truly self-powered devices, where 577 * vbus doesn't act like a power supply.) 578 * 579 * Such spikes are short; usually less than ~500 usec, max 580 * of ~2 msec. That is, they're not sustained overcurrent 581 * errors, though they're reported using VBUSERROR irqs. 582 * 583 * Workarounds: (a) hardware: use self powered devices. 584 * (b) software: ignore non-repeated VBUS errors. 585 * 586 * REVISIT: do delays from lots of DEBUG_KERNEL checks 587 * make trouble here, keeping VBUS < 4.4V ? 588 */ 589 switch (musb->xceiv->state) { 590 case OTG_STATE_A_HOST: 591 /* recovery is dicey once we've gotten past the 592 * initial stages of enumeration, but if VBUS 593 * stayed ok at the other end of the link, and 594 * another reset is due (at least for high speed, 595 * to redo the chirp etc), it might work OK... 596 */ 597 case OTG_STATE_A_WAIT_BCON: 598 case OTG_STATE_A_WAIT_VRISE: 599 if (musb->vbuserr_retry) { 600 void __iomem *mbase = musb->mregs; 601 602 musb->vbuserr_retry--; 603 ignore = 1; 604 devctl |= MUSB_DEVCTL_SESSION; 605 musb_writeb(mbase, MUSB_DEVCTL, devctl); 606 } else { 607 musb->port1_status |= 608 USB_PORT_STAT_OVERCURRENT 609 | (USB_PORT_STAT_C_OVERCURRENT << 16); 610 } 611 break; 612 default: 613 break; 614 } 615 616 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 617 otg_state_string(musb->xceiv->state), 618 devctl, 619 ({ char *s; 620 switch (devctl & MUSB_DEVCTL_VBUS) { 621 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 622 s = "<SessEnd"; break; 623 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 624 s = "<AValid"; break; 625 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 626 s = "<VBusValid"; break; 627 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 628 default: 629 s = "VALID"; break; 630 }; s; }), 631 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 632 musb->port1_status); 633 634 /* go through A_WAIT_VFALL then start a new session */ 635 if (!ignore) 636 musb_platform_set_vbus(musb, 0); 637 handled = IRQ_HANDLED; 638 } 639 640 if (int_usb & MUSB_INTR_SUSPEND) { 641 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 642 otg_state_string(musb->xceiv->state), devctl, power); 643 handled = IRQ_HANDLED; 644 645 switch (musb->xceiv->state) { 646 case OTG_STATE_A_PERIPHERAL: 647 /* We also come here if the cable is removed, since 648 * this silicon doesn't report ID-no-longer-grounded. 649 * 650 * We depend on T(a_wait_bcon) to shut us down, and 651 * hope users don't do anything dicey during this 652 * undesired detour through A_WAIT_BCON. 653 */ 654 musb_hnp_stop(musb); 655 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 656 musb_root_disconnect(musb); 657 musb_platform_try_idle(musb, jiffies 658 + msecs_to_jiffies(musb->a_wait_bcon 659 ? : OTG_TIME_A_WAIT_BCON)); 660 661 break; 662 case OTG_STATE_B_IDLE: 663 if (!musb->is_active) 664 break; 665 case OTG_STATE_B_PERIPHERAL: 666 musb_g_suspend(musb); 667 musb->is_active = is_otg_enabled(musb) 668 && otg->gadget->b_hnp_enable; 669 if (musb->is_active) { 670 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 671 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 672 mod_timer(&musb->otg_timer, jiffies 673 + msecs_to_jiffies( 674 OTG_TIME_B_ASE0_BRST)); 675 } 676 break; 677 case OTG_STATE_A_WAIT_BCON: 678 if (musb->a_wait_bcon != 0) 679 musb_platform_try_idle(musb, jiffies 680 + msecs_to_jiffies(musb->a_wait_bcon)); 681 break; 682 case OTG_STATE_A_HOST: 683 musb->xceiv->state = OTG_STATE_A_SUSPEND; 684 musb->is_active = is_otg_enabled(musb) 685 && otg->host->b_hnp_enable; 686 break; 687 case OTG_STATE_B_HOST: 688 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 689 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 690 break; 691 default: 692 /* "should not happen" */ 693 musb->is_active = 0; 694 break; 695 } 696 } 697 #endif 698 699 if (int_usb & MUSB_INTR_CONNECT) { 700 struct usb_hcd *hcd = musb_to_hcd(musb); 701 702 handled = IRQ_HANDLED; 703 musb->is_active = 1; 704 705 musb->ep0_stage = MUSB_EP0_START; 706 707 /* flush endpoints when transitioning from Device Mode */ 708 if (is_peripheral_active(musb)) { 709 /* REVISIT HNP; just force disconnect */ 710 } 711 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 712 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 713 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 714 #ifndef __UBOOT__ 715 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 716 |USB_PORT_STAT_HIGH_SPEED 717 |USB_PORT_STAT_ENABLE 718 ); 719 musb->port1_status |= USB_PORT_STAT_CONNECTION 720 |(USB_PORT_STAT_C_CONNECTION << 16); 721 722 /* high vs full speed is just a guess until after reset */ 723 if (devctl & MUSB_DEVCTL_LSDEV) 724 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 725 726 /* indicate new connection to OTG machine */ 727 switch (musb->xceiv->state) { 728 case OTG_STATE_B_PERIPHERAL: 729 if (int_usb & MUSB_INTR_SUSPEND) { 730 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 731 int_usb &= ~MUSB_INTR_SUSPEND; 732 goto b_host; 733 } else 734 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 735 break; 736 case OTG_STATE_B_WAIT_ACON: 737 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 738 b_host: 739 musb->xceiv->state = OTG_STATE_B_HOST; 740 hcd->self.is_b_host = 1; 741 musb->ignore_disconnect = 0; 742 del_timer(&musb->otg_timer); 743 break; 744 default: 745 if ((devctl & MUSB_DEVCTL_VBUS) 746 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 747 musb->xceiv->state = OTG_STATE_A_HOST; 748 hcd->self.is_b_host = 0; 749 } 750 break; 751 } 752 753 /* poke the root hub */ 754 MUSB_HST_MODE(musb); 755 if (hcd->status_urb) 756 usb_hcd_poll_rh_status(hcd); 757 else 758 usb_hcd_resume_root_hub(hcd); 759 760 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 761 otg_state_string(musb->xceiv->state), devctl); 762 #endif 763 } 764 765 #ifndef __UBOOT__ 766 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 767 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 768 otg_state_string(musb->xceiv->state), 769 MUSB_MODE(musb), devctl); 770 handled = IRQ_HANDLED; 771 772 switch (musb->xceiv->state) { 773 case OTG_STATE_A_HOST: 774 case OTG_STATE_A_SUSPEND: 775 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 776 musb_root_disconnect(musb); 777 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 778 musb_platform_try_idle(musb, jiffies 779 + msecs_to_jiffies(musb->a_wait_bcon)); 780 break; 781 case OTG_STATE_B_HOST: 782 /* REVISIT this behaves for "real disconnect" 783 * cases; make sure the other transitions from 784 * from B_HOST act right too. The B_HOST code 785 * in hnp_stop() is currently not used... 786 */ 787 musb_root_disconnect(musb); 788 musb_to_hcd(musb)->self.is_b_host = 0; 789 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 790 MUSB_DEV_MODE(musb); 791 musb_g_disconnect(musb); 792 break; 793 case OTG_STATE_A_PERIPHERAL: 794 musb_hnp_stop(musb); 795 musb_root_disconnect(musb); 796 /* FALLTHROUGH */ 797 case OTG_STATE_B_WAIT_ACON: 798 /* FALLTHROUGH */ 799 case OTG_STATE_B_PERIPHERAL: 800 case OTG_STATE_B_IDLE: 801 musb_g_disconnect(musb); 802 break; 803 default: 804 WARNING("unhandled DISCONNECT transition (%s)\n", 805 otg_state_string(musb->xceiv->state)); 806 break; 807 } 808 } 809 810 /* mentor saves a bit: bus reset and babble share the same irq. 811 * only host sees babble; only peripheral sees bus reset. 812 */ 813 if (int_usb & MUSB_INTR_RESET) { 814 handled = IRQ_HANDLED; 815 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 816 /* 817 * Looks like non-HS BABBLE can be ignored, but 818 * HS BABBLE is an error condition. For HS the solution 819 * is to avoid babble in the first place and fix what 820 * caused BABBLE. When HS BABBLE happens we can only 821 * stop the session. 822 */ 823 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 824 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 825 else { 826 ERR("Stopping host session -- babble\n"); 827 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 828 } 829 } else if (is_peripheral_capable()) { 830 dev_dbg(musb->controller, "BUS RESET as %s\n", 831 otg_state_string(musb->xceiv->state)); 832 switch (musb->xceiv->state) { 833 case OTG_STATE_A_SUSPEND: 834 /* We need to ignore disconnect on suspend 835 * otherwise tusb 2.0 won't reconnect after a 836 * power cycle, which breaks otg compliance. 837 */ 838 musb->ignore_disconnect = 1; 839 musb_g_reset(musb); 840 /* FALLTHROUGH */ 841 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 842 /* never use invalid T(a_wait_bcon) */ 843 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 844 otg_state_string(musb->xceiv->state), 845 TA_WAIT_BCON(musb)); 846 mod_timer(&musb->otg_timer, jiffies 847 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 848 break; 849 case OTG_STATE_A_PERIPHERAL: 850 musb->ignore_disconnect = 0; 851 del_timer(&musb->otg_timer); 852 musb_g_reset(musb); 853 break; 854 case OTG_STATE_B_WAIT_ACON: 855 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 856 otg_state_string(musb->xceiv->state)); 857 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 858 musb_g_reset(musb); 859 break; 860 case OTG_STATE_B_IDLE: 861 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 862 /* FALLTHROUGH */ 863 case OTG_STATE_B_PERIPHERAL: 864 musb_g_reset(musb); 865 break; 866 default: 867 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 868 otg_state_string(musb->xceiv->state)); 869 } 870 } 871 } 872 #endif 873 874 #if 0 875 /* REVISIT ... this would be for multiplexing periodic endpoints, or 876 * supporting transfer phasing to prevent exceeding ISO bandwidth 877 * limits of a given frame or microframe. 878 * 879 * It's not needed for peripheral side, which dedicates endpoints; 880 * though it _might_ use SOF irqs for other purposes. 881 * 882 * And it's not currently needed for host side, which also dedicates 883 * endpoints, relies on TX/RX interval registers, and isn't claimed 884 * to support ISO transfers yet. 885 */ 886 if (int_usb & MUSB_INTR_SOF) { 887 void __iomem *mbase = musb->mregs; 888 struct musb_hw_ep *ep; 889 u8 epnum; 890 u16 frame; 891 892 dev_dbg(musb->controller, "START_OF_FRAME\n"); 893 handled = IRQ_HANDLED; 894 895 /* start any periodic Tx transfers waiting for current frame */ 896 frame = musb_readw(mbase, MUSB_FRAME); 897 ep = musb->endpoints; 898 for (epnum = 1; (epnum < musb->nr_endpoints) 899 && (musb->epmask >= (1 << epnum)); 900 epnum++, ep++) { 901 /* 902 * FIXME handle framecounter wraps (12 bits) 903 * eliminate duplicated StartUrb logic 904 */ 905 if (ep->dwWaitFrame >= frame) { 906 ep->dwWaitFrame = 0; 907 pr_debug("SOF --> periodic TX%s on %d\n", 908 ep->tx_channel ? " DMA" : "", 909 epnum); 910 if (!ep->tx_channel) 911 musb_h_tx_start(musb, epnum); 912 else 913 cppi_hostdma_start(musb, epnum); 914 } 915 } /* end of for loop */ 916 } 917 #endif 918 919 schedule_work(&musb->irq_work); 920 921 return handled; 922 } 923 924 /*-------------------------------------------------------------------------*/ 925 926 /* 927 * Program the HDRC to start (enable interrupts, dma, etc.). 928 */ 929 void musb_start(struct musb *musb) 930 { 931 void __iomem *regs = musb->mregs; 932 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 933 934 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 935 936 /* Set INT enable registers, enable interrupts */ 937 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 938 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 939 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 940 941 musb_writeb(regs, MUSB_TESTMODE, 0); 942 943 /* put into basic highspeed mode and start session */ 944 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 945 #ifdef CONFIG_USB_GADGET_DUALSPEED 946 | MUSB_POWER_HSENAB 947 #endif 948 /* ENSUSPEND wedges tusb */ 949 /* | MUSB_POWER_ENSUSPEND */ 950 ); 951 952 musb->is_active = 0; 953 devctl = musb_readb(regs, MUSB_DEVCTL); 954 devctl &= ~MUSB_DEVCTL_SESSION; 955 956 if (is_otg_enabled(musb)) { 957 #ifndef __UBOOT__ 958 /* session started after: 959 * (a) ID-grounded irq, host mode; 960 * (b) vbus present/connect IRQ, peripheral mode; 961 * (c) peripheral initiates, using SRP 962 */ 963 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 964 musb->is_active = 1; 965 else 966 devctl |= MUSB_DEVCTL_SESSION; 967 #endif 968 969 } else if (is_host_enabled(musb)) { 970 /* assume ID pin is hard-wired to ground */ 971 devctl |= MUSB_DEVCTL_SESSION; 972 973 } else /* peripheral is enabled */ { 974 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 975 musb->is_active = 1; 976 } 977 musb_platform_enable(musb); 978 musb_writeb(regs, MUSB_DEVCTL, devctl); 979 } 980 981 982 static void musb_generic_disable(struct musb *musb) 983 { 984 void __iomem *mbase = musb->mregs; 985 u16 temp; 986 987 /* disable interrupts */ 988 musb_writeb(mbase, MUSB_INTRUSBE, 0); 989 musb_writew(mbase, MUSB_INTRTXE, 0); 990 musb_writew(mbase, MUSB_INTRRXE, 0); 991 992 /* off */ 993 musb_writeb(mbase, MUSB_DEVCTL, 0); 994 995 /* flush pending interrupts */ 996 temp = musb_readb(mbase, MUSB_INTRUSB); 997 temp = musb_readw(mbase, MUSB_INTRTX); 998 temp = musb_readw(mbase, MUSB_INTRRX); 999 1000 } 1001 1002 /* 1003 * Make the HDRC stop (disable interrupts, etc.); 1004 * reversible by musb_start 1005 * called on gadget driver unregister 1006 * with controller locked, irqs blocked 1007 * acts as a NOP unless some role activated the hardware 1008 */ 1009 void musb_stop(struct musb *musb) 1010 { 1011 /* stop IRQs, timers, ... */ 1012 musb_platform_disable(musb); 1013 musb_generic_disable(musb); 1014 dev_dbg(musb->controller, "HDRC disabled\n"); 1015 1016 /* FIXME 1017 * - mark host and/or peripheral drivers unusable/inactive 1018 * - disable DMA (and enable it in HdrcStart) 1019 * - make sure we can musb_start() after musb_stop(); with 1020 * OTG mode, gadget driver module rmmod/modprobe cycles that 1021 * - ... 1022 */ 1023 musb_platform_try_idle(musb, 0); 1024 } 1025 1026 #ifndef __UBOOT__ 1027 static void musb_shutdown(struct platform_device *pdev) 1028 { 1029 struct musb *musb = dev_to_musb(&pdev->dev); 1030 unsigned long flags; 1031 1032 pm_runtime_get_sync(musb->controller); 1033 1034 musb_gadget_cleanup(musb); 1035 1036 spin_lock_irqsave(&musb->lock, flags); 1037 musb_platform_disable(musb); 1038 musb_generic_disable(musb); 1039 spin_unlock_irqrestore(&musb->lock, flags); 1040 1041 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1042 usb_remove_hcd(musb_to_hcd(musb)); 1043 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1044 musb_platform_exit(musb); 1045 1046 pm_runtime_put(musb->controller); 1047 /* FIXME power down */ 1048 } 1049 #endif 1050 1051 1052 /*-------------------------------------------------------------------------*/ 1053 1054 /* 1055 * The silicon either has hard-wired endpoint configurations, or else 1056 * "dynamic fifo" sizing. The driver has support for both, though at this 1057 * writing only the dynamic sizing is very well tested. Since we switched 1058 * away from compile-time hardware parameters, we can no longer rely on 1059 * dead code elimination to leave only the relevant one in the object file. 1060 * 1061 * We don't currently use dynamic fifo setup capability to do anything 1062 * more than selecting one of a bunch of predefined configurations. 1063 */ 1064 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1065 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1066 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1067 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1068 || defined(CONFIG_USB_MUSB_AM35X) \ 1069 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1070 || defined(CONFIG_USB_MUSB_DSPS) \ 1071 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1072 static ushort __devinitdata fifo_mode = 4; 1073 #elif defined(CONFIG_USB_MUSB_UX500) \ 1074 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1075 static ushort __devinitdata fifo_mode = 5; 1076 #else 1077 static ushort __devinitdata fifo_mode = 2; 1078 #endif 1079 1080 /* "modprobe ... fifo_mode=1" etc */ 1081 module_param(fifo_mode, ushort, 0); 1082 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1083 1084 /* 1085 * tables defining fifo_mode values. define more if you like. 1086 * for host side, make sure both halves of ep1 are set up. 1087 */ 1088 1089 /* mode 0 - fits in 2KB */ 1090 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1091 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1092 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1093 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1094 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1095 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1096 }; 1097 1098 /* mode 1 - fits in 4KB */ 1099 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1100 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1101 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1102 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1103 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1104 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1105 }; 1106 1107 /* mode 2 - fits in 4KB */ 1108 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1109 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1110 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1111 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1112 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1113 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1114 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1115 }; 1116 1117 /* mode 3 - fits in 4KB */ 1118 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1119 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1120 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1121 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1122 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1123 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1124 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1125 }; 1126 1127 /* mode 4 - fits in 16KB */ 1128 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1129 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1130 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1131 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1132 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1133 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1134 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1135 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1136 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1137 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1138 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1139 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1140 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1141 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1142 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1143 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1144 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1145 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1146 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1147 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1148 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1149 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1150 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1151 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1152 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1153 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1154 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1155 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1156 }; 1157 1158 /* mode 5 - fits in 8KB */ 1159 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1160 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1161 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1162 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1163 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1164 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1165 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1166 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1167 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1168 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1169 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1170 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1171 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1172 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1173 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1174 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1175 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1176 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1177 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1178 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1179 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1180 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1181 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1182 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1183 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1184 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1185 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1186 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1187 }; 1188 1189 /* 1190 * configure a fifo; for non-shared endpoints, this may be called 1191 * once for a tx fifo and once for an rx fifo. 1192 * 1193 * returns negative errno or offset for next fifo. 1194 */ 1195 static int __devinit 1196 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1197 const struct musb_fifo_cfg *cfg, u16 offset) 1198 { 1199 void __iomem *mbase = musb->mregs; 1200 int size = 0; 1201 u16 maxpacket = cfg->maxpacket; 1202 u16 c_off = offset >> 3; 1203 u8 c_size; 1204 1205 /* expect hw_ep has already been zero-initialized */ 1206 1207 size = ffs(max(maxpacket, (u16) 8)) - 1; 1208 maxpacket = 1 << size; 1209 1210 c_size = size - 3; 1211 if (cfg->mode == BUF_DOUBLE) { 1212 if ((offset + (maxpacket << 1)) > 1213 (1 << (musb->config->ram_bits + 2))) 1214 return -EMSGSIZE; 1215 c_size |= MUSB_FIFOSZ_DPB; 1216 } else { 1217 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1218 return -EMSGSIZE; 1219 } 1220 1221 /* configure the FIFO */ 1222 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1223 1224 /* EP0 reserved endpoint for control, bidirectional; 1225 * EP1 reserved for bulk, two unidirection halves. 1226 */ 1227 if (hw_ep->epnum == 1) 1228 musb->bulk_ep = hw_ep; 1229 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1230 switch (cfg->style) { 1231 case FIFO_TX: 1232 musb_write_txfifosz(mbase, c_size); 1233 musb_write_txfifoadd(mbase, c_off); 1234 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1235 hw_ep->max_packet_sz_tx = maxpacket; 1236 break; 1237 case FIFO_RX: 1238 musb_write_rxfifosz(mbase, c_size); 1239 musb_write_rxfifoadd(mbase, c_off); 1240 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1241 hw_ep->max_packet_sz_rx = maxpacket; 1242 break; 1243 case FIFO_RXTX: 1244 musb_write_txfifosz(mbase, c_size); 1245 musb_write_txfifoadd(mbase, c_off); 1246 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1247 hw_ep->max_packet_sz_rx = maxpacket; 1248 1249 musb_write_rxfifosz(mbase, c_size); 1250 musb_write_rxfifoadd(mbase, c_off); 1251 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1252 hw_ep->max_packet_sz_tx = maxpacket; 1253 1254 hw_ep->is_shared_fifo = true; 1255 break; 1256 } 1257 1258 /* NOTE rx and tx endpoint irqs aren't managed separately, 1259 * which happens to be ok 1260 */ 1261 musb->epmask |= (1 << hw_ep->epnum); 1262 1263 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1264 } 1265 1266 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1267 .style = FIFO_RXTX, .maxpacket = 64, 1268 }; 1269 1270 static int __devinit ep_config_from_table(struct musb *musb) 1271 { 1272 const struct musb_fifo_cfg *cfg; 1273 unsigned i, n; 1274 int offset; 1275 struct musb_hw_ep *hw_ep = musb->endpoints; 1276 1277 if (musb->config->fifo_cfg) { 1278 cfg = musb->config->fifo_cfg; 1279 n = musb->config->fifo_cfg_size; 1280 goto done; 1281 } 1282 1283 switch (fifo_mode) { 1284 default: 1285 fifo_mode = 0; 1286 /* FALLTHROUGH */ 1287 case 0: 1288 cfg = mode_0_cfg; 1289 n = ARRAY_SIZE(mode_0_cfg); 1290 break; 1291 case 1: 1292 cfg = mode_1_cfg; 1293 n = ARRAY_SIZE(mode_1_cfg); 1294 break; 1295 case 2: 1296 cfg = mode_2_cfg; 1297 n = ARRAY_SIZE(mode_2_cfg); 1298 break; 1299 case 3: 1300 cfg = mode_3_cfg; 1301 n = ARRAY_SIZE(mode_3_cfg); 1302 break; 1303 case 4: 1304 cfg = mode_4_cfg; 1305 n = ARRAY_SIZE(mode_4_cfg); 1306 break; 1307 case 5: 1308 cfg = mode_5_cfg; 1309 n = ARRAY_SIZE(mode_5_cfg); 1310 break; 1311 } 1312 1313 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1314 1315 done: 1316 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1317 /* assert(offset > 0) */ 1318 1319 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1320 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1321 */ 1322 1323 for (i = 0; i < n; i++) { 1324 u8 epn = cfg->hw_ep_num; 1325 1326 if (epn >= musb->config->num_eps) { 1327 pr_debug("%s: invalid ep %d\n", 1328 musb_driver_name, epn); 1329 return -EINVAL; 1330 } 1331 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1332 if (offset < 0) { 1333 pr_debug("%s: mem overrun, ep %d\n", 1334 musb_driver_name, epn); 1335 return -EINVAL; 1336 } 1337 epn++; 1338 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1339 } 1340 1341 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, 1342 musb->config->num_eps * 2 - 1, offset, 1343 (1 << (musb->config->ram_bits + 2))); 1344 1345 if (!musb->bulk_ep) { 1346 pr_debug("%s: missing bulk\n", musb_driver_name); 1347 return -EINVAL; 1348 } 1349 1350 return 0; 1351 } 1352 1353 1354 /* 1355 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1356 * @param musb the controller 1357 */ 1358 static int __devinit ep_config_from_hw(struct musb *musb) 1359 { 1360 u8 epnum = 0; 1361 struct musb_hw_ep *hw_ep; 1362 void *mbase = musb->mregs; 1363 int ret = 0; 1364 1365 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1366 1367 /* FIXME pick up ep0 maxpacket size */ 1368 1369 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1370 musb_ep_select(mbase, epnum); 1371 hw_ep = musb->endpoints + epnum; 1372 1373 ret = musb_read_fifosize(musb, hw_ep, epnum); 1374 if (ret < 0) 1375 break; 1376 1377 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1378 1379 /* pick an RX/TX endpoint for bulk */ 1380 if (hw_ep->max_packet_sz_tx < 512 1381 || hw_ep->max_packet_sz_rx < 512) 1382 continue; 1383 1384 /* REVISIT: this algorithm is lazy, we should at least 1385 * try to pick a double buffered endpoint. 1386 */ 1387 if (musb->bulk_ep) 1388 continue; 1389 musb->bulk_ep = hw_ep; 1390 } 1391 1392 if (!musb->bulk_ep) { 1393 pr_debug("%s: missing bulk\n", musb_driver_name); 1394 return -EINVAL; 1395 } 1396 1397 return 0; 1398 } 1399 1400 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1401 1402 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1403 * configure endpoints, or take their config from silicon 1404 */ 1405 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1406 { 1407 u8 reg; 1408 char *type; 1409 char aInfo[90], aRevision[32], aDate[12]; 1410 void __iomem *mbase = musb->mregs; 1411 int status = 0; 1412 int i; 1413 1414 /* log core options (read using indexed model) */ 1415 reg = musb_read_configdata(mbase); 1416 1417 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1418 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1419 strcat(aInfo, ", dyn FIFOs"); 1420 musb->dyn_fifo = true; 1421 } 1422 #ifndef CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT 1423 if (reg & MUSB_CONFIGDATA_MPRXE) { 1424 strcat(aInfo, ", bulk combine"); 1425 musb->bulk_combine = true; 1426 } 1427 if (reg & MUSB_CONFIGDATA_MPTXE) { 1428 strcat(aInfo, ", bulk split"); 1429 musb->bulk_split = true; 1430 } 1431 #else 1432 musb->bulk_combine = false; 1433 musb->bulk_split = false; 1434 #endif 1435 if (reg & MUSB_CONFIGDATA_HBRXE) { 1436 strcat(aInfo, ", HB-ISO Rx"); 1437 musb->hb_iso_rx = true; 1438 } 1439 if (reg & MUSB_CONFIGDATA_HBTXE) { 1440 strcat(aInfo, ", HB-ISO Tx"); 1441 musb->hb_iso_tx = true; 1442 } 1443 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1444 strcat(aInfo, ", SoftConn"); 1445 1446 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1447 1448 aDate[0] = 0; 1449 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1450 musb->is_multipoint = 1; 1451 type = "M"; 1452 } else { 1453 musb->is_multipoint = 0; 1454 type = ""; 1455 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1456 printk(KERN_ERR 1457 "%s: kernel must blacklist external hubs\n", 1458 musb_driver_name); 1459 #endif 1460 } 1461 1462 /* log release info */ 1463 musb->hwvers = musb_read_hwvers(mbase); 1464 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1465 MUSB_HWVERS_MINOR(musb->hwvers), 1466 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1467 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, 1468 aRevision, aDate); 1469 1470 /* configure ep0 */ 1471 musb_configure_ep0(musb); 1472 1473 /* discover endpoint configuration */ 1474 musb->nr_endpoints = 1; 1475 musb->epmask = 1; 1476 1477 if (musb->dyn_fifo) 1478 status = ep_config_from_table(musb); 1479 else 1480 status = ep_config_from_hw(musb); 1481 1482 if (status < 0) 1483 return status; 1484 1485 /* finish init, and print endpoint config */ 1486 for (i = 0; i < musb->nr_endpoints; i++) { 1487 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1488 1489 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1490 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1491 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1492 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1493 hw_ep->fifo_sync_va = 1494 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1495 1496 if (i == 0) 1497 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1498 else 1499 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1500 #endif 1501 1502 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1503 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1504 hw_ep->rx_reinit = 1; 1505 hw_ep->tx_reinit = 1; 1506 1507 if (hw_ep->max_packet_sz_tx) { 1508 dev_dbg(musb->controller, 1509 "%s: hw_ep %d%s, %smax %d\n", 1510 musb_driver_name, i, 1511 hw_ep->is_shared_fifo ? "shared" : "tx", 1512 hw_ep->tx_double_buffered 1513 ? "doublebuffer, " : "", 1514 hw_ep->max_packet_sz_tx); 1515 } 1516 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1517 dev_dbg(musb->controller, 1518 "%s: hw_ep %d%s, %smax %d\n", 1519 musb_driver_name, i, 1520 "rx", 1521 hw_ep->rx_double_buffered 1522 ? "doublebuffer, " : "", 1523 hw_ep->max_packet_sz_rx); 1524 } 1525 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1526 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1527 } 1528 1529 return 0; 1530 } 1531 1532 /*-------------------------------------------------------------------------*/ 1533 1534 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1535 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1536 1537 static irqreturn_t generic_interrupt(int irq, void *__hci) 1538 { 1539 unsigned long flags; 1540 irqreturn_t retval = IRQ_NONE; 1541 struct musb *musb = __hci; 1542 1543 spin_lock_irqsave(&musb->lock, flags); 1544 1545 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1546 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1547 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1548 1549 if (musb->int_usb || musb->int_tx || musb->int_rx) 1550 retval = musb_interrupt(musb); 1551 1552 spin_unlock_irqrestore(&musb->lock, flags); 1553 1554 return retval; 1555 } 1556 1557 #else 1558 #define generic_interrupt NULL 1559 #endif 1560 1561 /* 1562 * handle all the irqs defined by the HDRC core. for now we expect: other 1563 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1564 * will be assigned, and the irq will already have been acked. 1565 * 1566 * called in irq context with spinlock held, irqs blocked 1567 */ 1568 irqreturn_t musb_interrupt(struct musb *musb) 1569 { 1570 irqreturn_t retval = IRQ_NONE; 1571 u8 devctl, power; 1572 int ep_num; 1573 u32 reg; 1574 1575 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1576 power = musb_readb(musb->mregs, MUSB_POWER); 1577 1578 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1579 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1580 musb->int_usb, musb->int_tx, musb->int_rx); 1581 1582 /* the core can interrupt us for multiple reasons; docs have 1583 * a generic interrupt flowchart to follow 1584 */ 1585 if (musb->int_usb) 1586 retval |= musb_stage0_irq(musb, musb->int_usb, 1587 devctl, power); 1588 1589 /* "stage 1" is handling endpoint irqs */ 1590 1591 /* handle endpoint 0 first */ 1592 if (musb->int_tx & 1) { 1593 if (devctl & MUSB_DEVCTL_HM) { 1594 if (is_host_capable()) 1595 retval |= musb_h_ep0_irq(musb); 1596 } else { 1597 if (is_peripheral_capable()) 1598 retval |= musb_g_ep0_irq(musb); 1599 } 1600 } 1601 1602 /* RX on endpoints 1-15 */ 1603 reg = musb->int_rx >> 1; 1604 ep_num = 1; 1605 while (reg) { 1606 if (reg & 1) { 1607 /* musb_ep_select(musb->mregs, ep_num); */ 1608 /* REVISIT just retval = ep->rx_irq(...) */ 1609 retval = IRQ_HANDLED; 1610 if (devctl & MUSB_DEVCTL_HM) { 1611 if (is_host_capable()) 1612 musb_host_rx(musb, ep_num); 1613 } else { 1614 if (is_peripheral_capable()) 1615 musb_g_rx(musb, ep_num); 1616 } 1617 } 1618 1619 reg >>= 1; 1620 ep_num++; 1621 } 1622 1623 /* TX on endpoints 1-15 */ 1624 reg = musb->int_tx >> 1; 1625 ep_num = 1; 1626 while (reg) { 1627 if (reg & 1) { 1628 /* musb_ep_select(musb->mregs, ep_num); */ 1629 /* REVISIT just retval |= ep->tx_irq(...) */ 1630 retval = IRQ_HANDLED; 1631 if (devctl & MUSB_DEVCTL_HM) { 1632 if (is_host_capable()) 1633 musb_host_tx(musb, ep_num); 1634 } else { 1635 if (is_peripheral_capable()) 1636 musb_g_tx(musb, ep_num); 1637 } 1638 } 1639 reg >>= 1; 1640 ep_num++; 1641 } 1642 1643 return retval; 1644 } 1645 EXPORT_SYMBOL_GPL(musb_interrupt); 1646 1647 #ifndef CONFIG_MUSB_PIO_ONLY 1648 static bool __devinitdata use_dma = 1; 1649 1650 /* "modprobe ... use_dma=0" etc */ 1651 module_param(use_dma, bool, 0); 1652 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1653 1654 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1655 { 1656 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1657 1658 /* called with controller lock already held */ 1659 1660 if (!epnum) { 1661 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1662 if (!is_cppi_enabled()) { 1663 /* endpoint 0 */ 1664 if (devctl & MUSB_DEVCTL_HM) 1665 musb_h_ep0_irq(musb); 1666 else 1667 musb_g_ep0_irq(musb); 1668 } 1669 #endif 1670 } else { 1671 /* endpoints 1..15 */ 1672 if (transmit) { 1673 if (devctl & MUSB_DEVCTL_HM) { 1674 if (is_host_capable()) 1675 musb_host_tx(musb, epnum); 1676 } else { 1677 if (is_peripheral_capable()) 1678 musb_g_tx(musb, epnum); 1679 } 1680 } else { 1681 /* receive */ 1682 if (devctl & MUSB_DEVCTL_HM) { 1683 if (is_host_capable()) 1684 musb_host_rx(musb, epnum); 1685 } else { 1686 if (is_peripheral_capable()) 1687 musb_g_rx(musb, epnum); 1688 } 1689 } 1690 } 1691 } 1692 EXPORT_SYMBOL_GPL(musb_dma_completion); 1693 1694 #else 1695 #define use_dma 0 1696 #endif 1697 1698 /*-------------------------------------------------------------------------*/ 1699 1700 #ifdef CONFIG_SYSFS 1701 1702 static ssize_t 1703 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1704 { 1705 struct musb *musb = dev_to_musb(dev); 1706 unsigned long flags; 1707 int ret = -EINVAL; 1708 1709 spin_lock_irqsave(&musb->lock, flags); 1710 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1711 spin_unlock_irqrestore(&musb->lock, flags); 1712 1713 return ret; 1714 } 1715 1716 static ssize_t 1717 musb_mode_store(struct device *dev, struct device_attribute *attr, 1718 const char *buf, size_t n) 1719 { 1720 struct musb *musb = dev_to_musb(dev); 1721 unsigned long flags; 1722 int status; 1723 1724 spin_lock_irqsave(&musb->lock, flags); 1725 if (sysfs_streq(buf, "host")) 1726 status = musb_platform_set_mode(musb, MUSB_HOST); 1727 else if (sysfs_streq(buf, "peripheral")) 1728 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1729 else if (sysfs_streq(buf, "otg")) 1730 status = musb_platform_set_mode(musb, MUSB_OTG); 1731 else 1732 status = -EINVAL; 1733 spin_unlock_irqrestore(&musb->lock, flags); 1734 1735 return (status == 0) ? n : status; 1736 } 1737 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1738 1739 static ssize_t 1740 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1741 const char *buf, size_t n) 1742 { 1743 struct musb *musb = dev_to_musb(dev); 1744 unsigned long flags; 1745 unsigned long val; 1746 1747 if (sscanf(buf, "%lu", &val) < 1) { 1748 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1749 return -EINVAL; 1750 } 1751 1752 spin_lock_irqsave(&musb->lock, flags); 1753 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1754 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1755 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1756 musb->is_active = 0; 1757 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1758 spin_unlock_irqrestore(&musb->lock, flags); 1759 1760 return n; 1761 } 1762 1763 static ssize_t 1764 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1765 { 1766 struct musb *musb = dev_to_musb(dev); 1767 unsigned long flags; 1768 unsigned long val; 1769 int vbus; 1770 1771 spin_lock_irqsave(&musb->lock, flags); 1772 val = musb->a_wait_bcon; 1773 /* FIXME get_vbus_status() is normally #defined as false... 1774 * and is effectively TUSB-specific. 1775 */ 1776 vbus = musb_platform_get_vbus_status(musb); 1777 spin_unlock_irqrestore(&musb->lock, flags); 1778 1779 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1780 vbus ? "on" : "off", val); 1781 } 1782 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1783 1784 /* Gadget drivers can't know that a host is connected so they might want 1785 * to start SRP, but users can. This allows userspace to trigger SRP. 1786 */ 1787 static ssize_t 1788 musb_srp_store(struct device *dev, struct device_attribute *attr, 1789 const char *buf, size_t n) 1790 { 1791 struct musb *musb = dev_to_musb(dev); 1792 unsigned short srp; 1793 1794 if (sscanf(buf, "%hu", &srp) != 1 1795 || (srp != 1)) { 1796 dev_err(dev, "SRP: Value must be 1\n"); 1797 return -EINVAL; 1798 } 1799 1800 if (srp == 1) 1801 musb_g_wakeup(musb); 1802 1803 return n; 1804 } 1805 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1806 1807 static struct attribute *musb_attributes[] = { 1808 &dev_attr_mode.attr, 1809 &dev_attr_vbus.attr, 1810 &dev_attr_srp.attr, 1811 NULL 1812 }; 1813 1814 static const struct attribute_group musb_attr_group = { 1815 .attrs = musb_attributes, 1816 }; 1817 1818 #endif /* sysfs */ 1819 1820 #ifndef __UBOOT__ 1821 /* Only used to provide driver mode change events */ 1822 static void musb_irq_work(struct work_struct *data) 1823 { 1824 struct musb *musb = container_of(data, struct musb, irq_work); 1825 static int old_state; 1826 1827 if (musb->xceiv->state != old_state) { 1828 old_state = musb->xceiv->state; 1829 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1830 } 1831 } 1832 #endif 1833 1834 /* -------------------------------------------------------------------------- 1835 * Init support 1836 */ 1837 1838 static struct musb *__devinit 1839 allocate_instance(struct device *dev, 1840 struct musb_hdrc_config *config, void __iomem *mbase) 1841 { 1842 struct musb *musb; 1843 struct musb_hw_ep *ep; 1844 int epnum; 1845 #ifndef __UBOOT__ 1846 struct usb_hcd *hcd; 1847 1848 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1849 if (!hcd) 1850 return NULL; 1851 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1852 1853 musb = hcd_to_musb(hcd); 1854 #else 1855 musb = calloc(1, sizeof(*musb)); 1856 if (!musb) 1857 return NULL; 1858 #endif 1859 INIT_LIST_HEAD(&musb->control); 1860 INIT_LIST_HEAD(&musb->in_bulk); 1861 INIT_LIST_HEAD(&musb->out_bulk); 1862 1863 #ifndef __UBOOT__ 1864 hcd->uses_new_polling = 1; 1865 hcd->has_tt = 1; 1866 #endif 1867 1868 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1869 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1870 dev_set_drvdata(dev, musb); 1871 musb->mregs = mbase; 1872 musb->ctrl_base = mbase; 1873 musb->nIrq = -ENODEV; 1874 musb->config = config; 1875 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1876 for (epnum = 0, ep = musb->endpoints; 1877 epnum < musb->config->num_eps; 1878 epnum++, ep++) { 1879 ep->musb = musb; 1880 ep->epnum = epnum; 1881 } 1882 1883 musb->controller = dev; 1884 1885 return musb; 1886 } 1887 1888 static void musb_free(struct musb *musb) 1889 { 1890 /* this has multiple entry modes. it handles fault cleanup after 1891 * probe(), where things may be partially set up, as well as rmmod 1892 * cleanup after everything's been de-activated. 1893 */ 1894 1895 #ifdef CONFIG_SYSFS 1896 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1897 #endif 1898 1899 if (musb->nIrq >= 0) { 1900 if (musb->irq_wake) 1901 disable_irq_wake(musb->nIrq); 1902 free_irq(musb->nIrq, musb); 1903 } 1904 if (is_dma_capable() && musb->dma_controller) { 1905 struct dma_controller *c = musb->dma_controller; 1906 1907 (void) c->stop(c); 1908 dma_controller_destroy(c); 1909 } 1910 1911 kfree(musb); 1912 } 1913 1914 /* 1915 * Perform generic per-controller initialization. 1916 * 1917 * @pDevice: the controller (already clocked, etc) 1918 * @nIrq: irq 1919 * @mregs: virtual address of controller registers, 1920 * not yet corrected for platform-specific offsets 1921 */ 1922 #ifndef __UBOOT__ 1923 static int __devinit 1924 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1925 #else 1926 struct musb * 1927 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, 1928 void *ctrl) 1929 #endif 1930 { 1931 int status; 1932 struct musb *musb; 1933 #ifndef __UBOOT__ 1934 struct musb_hdrc_platform_data *plat = dev->platform_data; 1935 #else 1936 int nIrq = 0; 1937 #endif 1938 1939 /* The driver might handle more features than the board; OK. 1940 * Fail when the board needs a feature that's not enabled. 1941 */ 1942 if (!plat) { 1943 dev_dbg(dev, "no platform_data?\n"); 1944 status = -ENODEV; 1945 goto fail0; 1946 } 1947 1948 /* allocate */ 1949 musb = allocate_instance(dev, plat->config, ctrl); 1950 if (!musb) { 1951 status = -ENOMEM; 1952 goto fail0; 1953 } 1954 1955 pm_runtime_use_autosuspend(musb->controller); 1956 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1957 pm_runtime_enable(musb->controller); 1958 1959 spin_lock_init(&musb->lock); 1960 musb->board_mode = plat->mode; 1961 musb->board_set_power = plat->set_power; 1962 musb->min_power = plat->min_power; 1963 musb->ops = plat->platform_ops; 1964 1965 /* The musb_platform_init() call: 1966 * - adjusts musb->mregs and musb->isr if needed, 1967 * - may initialize an integrated tranceiver 1968 * - initializes musb->xceiv, usually by otg_get_phy() 1969 * - stops powering VBUS 1970 * 1971 * There are various transceiver configurations. Blackfin, 1972 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1973 * external/discrete ones in various flavors (twl4030 family, 1974 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1975 */ 1976 musb->isr = generic_interrupt; 1977 status = musb_platform_init(musb); 1978 if (status < 0) 1979 goto fail1; 1980 1981 if (!musb->isr) { 1982 status = -ENODEV; 1983 goto fail2; 1984 } 1985 1986 #ifndef __UBOOT__ 1987 if (!musb->xceiv->io_ops) { 1988 musb->xceiv->io_dev = musb->controller; 1989 musb->xceiv->io_priv = musb->mregs; 1990 musb->xceiv->io_ops = &musb_ulpi_access; 1991 } 1992 #endif 1993 1994 pm_runtime_get_sync(musb->controller); 1995 1996 #ifndef CONFIG_MUSB_PIO_ONLY 1997 if (use_dma && dev->dma_mask) { 1998 struct dma_controller *c; 1999 2000 c = dma_controller_create(musb, musb->mregs); 2001 musb->dma_controller = c; 2002 if (c) 2003 (void) c->start(c); 2004 } 2005 #endif 2006 #ifndef __UBOOT__ 2007 /* ideally this would be abstracted in platform setup */ 2008 if (!is_dma_capable() || !musb->dma_controller) 2009 dev->dma_mask = NULL; 2010 #endif 2011 2012 /* be sure interrupts are disabled before connecting ISR */ 2013 musb_platform_disable(musb); 2014 musb_generic_disable(musb); 2015 2016 /* setup musb parts of the core (especially endpoints) */ 2017 status = musb_core_init(plat->config->multipoint 2018 ? MUSB_CONTROLLER_MHDRC 2019 : MUSB_CONTROLLER_HDRC, musb); 2020 if (status < 0) 2021 goto fail3; 2022 2023 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2024 2025 /* Init IRQ workqueue before request_irq */ 2026 INIT_WORK(&musb->irq_work, musb_irq_work); 2027 2028 /* attach to the IRQ */ 2029 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2030 dev_err(dev, "request_irq %d failed!\n", nIrq); 2031 status = -ENODEV; 2032 goto fail3; 2033 } 2034 musb->nIrq = nIrq; 2035 /* FIXME this handles wakeup irqs wrong */ 2036 if (enable_irq_wake(nIrq) == 0) { 2037 musb->irq_wake = 1; 2038 device_init_wakeup(dev, 1); 2039 } else { 2040 musb->irq_wake = 0; 2041 } 2042 2043 #ifndef __UBOOT__ 2044 /* host side needs more setup */ 2045 if (is_host_enabled(musb)) { 2046 struct usb_hcd *hcd = musb_to_hcd(musb); 2047 2048 otg_set_host(musb->xceiv->otg, &hcd->self); 2049 2050 if (is_otg_enabled(musb)) 2051 hcd->self.otg_port = 1; 2052 musb->xceiv->otg->host = &hcd->self; 2053 hcd->power_budget = 2 * (plat->power ? : 250); 2054 2055 /* program PHY to use external vBus if required */ 2056 if (plat->extvbus) { 2057 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2058 busctl |= MUSB_ULPI_USE_EXTVBUS; 2059 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2060 } 2061 } 2062 #endif 2063 2064 /* For the host-only role, we can activate right away. 2065 * (We expect the ID pin to be forcibly grounded!!) 2066 * Otherwise, wait till the gadget driver hooks up. 2067 */ 2068 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2069 struct usb_hcd *hcd = musb_to_hcd(musb); 2070 2071 MUSB_HST_MODE(musb); 2072 #ifndef __UBOOT__ 2073 musb->xceiv->otg->default_a = 1; 2074 musb->xceiv->state = OTG_STATE_A_IDLE; 2075 2076 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2077 2078 hcd->self.uses_pio_for_control = 1; 2079 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2080 "HOST", status, 2081 musb_readb(musb->mregs, MUSB_DEVCTL), 2082 (musb_readb(musb->mregs, MUSB_DEVCTL) 2083 & MUSB_DEVCTL_BDEVICE 2084 ? 'B' : 'A')); 2085 #endif 2086 2087 } else /* peripheral is enabled */ { 2088 MUSB_DEV_MODE(musb); 2089 #ifndef __UBOOT__ 2090 musb->xceiv->otg->default_a = 0; 2091 musb->xceiv->state = OTG_STATE_B_IDLE; 2092 #endif 2093 2094 if (is_peripheral_capable()) 2095 status = musb_gadget_setup(musb); 2096 2097 #ifndef __UBOOT__ 2098 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2099 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2100 status, 2101 musb_readb(musb->mregs, MUSB_DEVCTL)); 2102 #endif 2103 2104 } 2105 if (status < 0) 2106 goto fail3; 2107 2108 status = musb_init_debugfs(musb); 2109 if (status < 0) 2110 goto fail4; 2111 2112 #ifdef CONFIG_SYSFS 2113 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2114 if (status) 2115 goto fail5; 2116 #endif 2117 2118 pm_runtime_put(musb->controller); 2119 2120 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", 2121 ({char *s; 2122 switch (musb->board_mode) { 2123 case MUSB_HOST: s = "Host"; break; 2124 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2125 default: s = "OTG"; break; 2126 }; s; }), 2127 ctrl, 2128 (is_dma_capable() && musb->dma_controller) 2129 ? "DMA" : "PIO", 2130 musb->nIrq); 2131 2132 #ifndef __UBOOT__ 2133 return 0; 2134 #else 2135 return status == 0 ? musb : NULL; 2136 #endif 2137 2138 fail5: 2139 musb_exit_debugfs(musb); 2140 2141 fail4: 2142 #ifndef __UBOOT__ 2143 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2144 usb_remove_hcd(musb_to_hcd(musb)); 2145 else 2146 #endif 2147 musb_gadget_cleanup(musb); 2148 2149 fail3: 2150 pm_runtime_put_sync(musb->controller); 2151 2152 fail2: 2153 if (musb->irq_wake) 2154 device_init_wakeup(dev, 0); 2155 musb_platform_exit(musb); 2156 2157 fail1: 2158 dev_err(musb->controller, 2159 "musb_init_controller failed with status %d\n", status); 2160 2161 musb_free(musb); 2162 2163 fail0: 2164 2165 #ifndef __UBOOT__ 2166 return status; 2167 #else 2168 return status == 0 ? musb : NULL; 2169 #endif 2170 2171 } 2172 2173 /*-------------------------------------------------------------------------*/ 2174 2175 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2176 * bridge to a platform device; this driver then suffices. 2177 */ 2178 2179 #ifndef CONFIG_MUSB_PIO_ONLY 2180 static u64 *orig_dma_mask; 2181 #endif 2182 2183 #ifndef __UBOOT__ 2184 static int __devinit musb_probe(struct platform_device *pdev) 2185 { 2186 struct device *dev = &pdev->dev; 2187 int irq = platform_get_irq_byname(pdev, "mc"); 2188 int status; 2189 struct resource *iomem; 2190 void __iomem *base; 2191 2192 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2193 if (!iomem || irq <= 0) 2194 return -ENODEV; 2195 2196 base = ioremap(iomem->start, resource_size(iomem)); 2197 if (!base) { 2198 dev_err(dev, "ioremap failed\n"); 2199 return -ENOMEM; 2200 } 2201 2202 #ifndef CONFIG_MUSB_PIO_ONLY 2203 /* clobbered by use_dma=n */ 2204 orig_dma_mask = dev->dma_mask; 2205 #endif 2206 status = musb_init_controller(dev, irq, base); 2207 if (status < 0) 2208 iounmap(base); 2209 2210 return status; 2211 } 2212 2213 static int __devexit musb_remove(struct platform_device *pdev) 2214 { 2215 struct musb *musb = dev_to_musb(&pdev->dev); 2216 void __iomem *ctrl_base = musb->ctrl_base; 2217 2218 /* this gets called on rmmod. 2219 * - Host mode: host may still be active 2220 * - Peripheral mode: peripheral is deactivated (or never-activated) 2221 * - OTG mode: both roles are deactivated (or never-activated) 2222 */ 2223 musb_exit_debugfs(musb); 2224 musb_shutdown(pdev); 2225 2226 musb_free(musb); 2227 iounmap(ctrl_base); 2228 device_init_wakeup(&pdev->dev, 0); 2229 #ifndef CONFIG_MUSB_PIO_ONLY 2230 pdev->dev.dma_mask = orig_dma_mask; 2231 #endif 2232 return 0; 2233 } 2234 2235 #ifdef CONFIG_PM 2236 2237 static void musb_save_context(struct musb *musb) 2238 { 2239 int i; 2240 void __iomem *musb_base = musb->mregs; 2241 void __iomem *epio; 2242 2243 if (is_host_enabled(musb)) { 2244 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2245 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2246 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2247 } 2248 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2249 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2250 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2251 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2252 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2253 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2254 2255 for (i = 0; i < musb->config->num_eps; ++i) { 2256 struct musb_hw_ep *hw_ep; 2257 2258 hw_ep = &musb->endpoints[i]; 2259 if (!hw_ep) 2260 continue; 2261 2262 epio = hw_ep->regs; 2263 if (!epio) 2264 continue; 2265 2266 musb_writeb(musb_base, MUSB_INDEX, i); 2267 musb->context.index_regs[i].txmaxp = 2268 musb_readw(epio, MUSB_TXMAXP); 2269 musb->context.index_regs[i].txcsr = 2270 musb_readw(epio, MUSB_TXCSR); 2271 musb->context.index_regs[i].rxmaxp = 2272 musb_readw(epio, MUSB_RXMAXP); 2273 musb->context.index_regs[i].rxcsr = 2274 musb_readw(epio, MUSB_RXCSR); 2275 2276 if (musb->dyn_fifo) { 2277 musb->context.index_regs[i].txfifoadd = 2278 musb_read_txfifoadd(musb_base); 2279 musb->context.index_regs[i].rxfifoadd = 2280 musb_read_rxfifoadd(musb_base); 2281 musb->context.index_regs[i].txfifosz = 2282 musb_read_txfifosz(musb_base); 2283 musb->context.index_regs[i].rxfifosz = 2284 musb_read_rxfifosz(musb_base); 2285 } 2286 if (is_host_enabled(musb)) { 2287 musb->context.index_regs[i].txtype = 2288 musb_readb(epio, MUSB_TXTYPE); 2289 musb->context.index_regs[i].txinterval = 2290 musb_readb(epio, MUSB_TXINTERVAL); 2291 musb->context.index_regs[i].rxtype = 2292 musb_readb(epio, MUSB_RXTYPE); 2293 musb->context.index_regs[i].rxinterval = 2294 musb_readb(epio, MUSB_RXINTERVAL); 2295 2296 musb->context.index_regs[i].txfunaddr = 2297 musb_read_txfunaddr(musb_base, i); 2298 musb->context.index_regs[i].txhubaddr = 2299 musb_read_txhubaddr(musb_base, i); 2300 musb->context.index_regs[i].txhubport = 2301 musb_read_txhubport(musb_base, i); 2302 2303 musb->context.index_regs[i].rxfunaddr = 2304 musb_read_rxfunaddr(musb_base, i); 2305 musb->context.index_regs[i].rxhubaddr = 2306 musb_read_rxhubaddr(musb_base, i); 2307 musb->context.index_regs[i].rxhubport = 2308 musb_read_rxhubport(musb_base, i); 2309 } 2310 } 2311 } 2312 2313 static void musb_restore_context(struct musb *musb) 2314 { 2315 int i; 2316 void __iomem *musb_base = musb->mregs; 2317 void __iomem *ep_target_regs; 2318 void __iomem *epio; 2319 2320 if (is_host_enabled(musb)) { 2321 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2322 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2323 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2324 } 2325 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2326 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2327 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2328 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2329 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2330 2331 for (i = 0; i < musb->config->num_eps; ++i) { 2332 struct musb_hw_ep *hw_ep; 2333 2334 hw_ep = &musb->endpoints[i]; 2335 if (!hw_ep) 2336 continue; 2337 2338 epio = hw_ep->regs; 2339 if (!epio) 2340 continue; 2341 2342 musb_writeb(musb_base, MUSB_INDEX, i); 2343 musb_writew(epio, MUSB_TXMAXP, 2344 musb->context.index_regs[i].txmaxp); 2345 musb_writew(epio, MUSB_TXCSR, 2346 musb->context.index_regs[i].txcsr); 2347 musb_writew(epio, MUSB_RXMAXP, 2348 musb->context.index_regs[i].rxmaxp); 2349 musb_writew(epio, MUSB_RXCSR, 2350 musb->context.index_regs[i].rxcsr); 2351 2352 if (musb->dyn_fifo) { 2353 musb_write_txfifosz(musb_base, 2354 musb->context.index_regs[i].txfifosz); 2355 musb_write_rxfifosz(musb_base, 2356 musb->context.index_regs[i].rxfifosz); 2357 musb_write_txfifoadd(musb_base, 2358 musb->context.index_regs[i].txfifoadd); 2359 musb_write_rxfifoadd(musb_base, 2360 musb->context.index_regs[i].rxfifoadd); 2361 } 2362 2363 if (is_host_enabled(musb)) { 2364 musb_writeb(epio, MUSB_TXTYPE, 2365 musb->context.index_regs[i].txtype); 2366 musb_writeb(epio, MUSB_TXINTERVAL, 2367 musb->context.index_regs[i].txinterval); 2368 musb_writeb(epio, MUSB_RXTYPE, 2369 musb->context.index_regs[i].rxtype); 2370 musb_writeb(epio, MUSB_RXINTERVAL, 2371 2372 musb->context.index_regs[i].rxinterval); 2373 musb_write_txfunaddr(musb_base, i, 2374 musb->context.index_regs[i].txfunaddr); 2375 musb_write_txhubaddr(musb_base, i, 2376 musb->context.index_regs[i].txhubaddr); 2377 musb_write_txhubport(musb_base, i, 2378 musb->context.index_regs[i].txhubport); 2379 2380 ep_target_regs = 2381 musb_read_target_reg_base(i, musb_base); 2382 2383 musb_write_rxfunaddr(ep_target_regs, 2384 musb->context.index_regs[i].rxfunaddr); 2385 musb_write_rxhubaddr(ep_target_regs, 2386 musb->context.index_regs[i].rxhubaddr); 2387 musb_write_rxhubport(ep_target_regs, 2388 musb->context.index_regs[i].rxhubport); 2389 } 2390 } 2391 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2392 } 2393 2394 static int musb_suspend(struct device *dev) 2395 { 2396 struct musb *musb = dev_to_musb(dev); 2397 unsigned long flags; 2398 2399 spin_lock_irqsave(&musb->lock, flags); 2400 2401 if (is_peripheral_active(musb)) { 2402 /* FIXME force disconnect unless we know USB will wake 2403 * the system up quickly enough to respond ... 2404 */ 2405 } else if (is_host_active(musb)) { 2406 /* we know all the children are suspended; sometimes 2407 * they will even be wakeup-enabled. 2408 */ 2409 } 2410 2411 spin_unlock_irqrestore(&musb->lock, flags); 2412 return 0; 2413 } 2414 2415 static int musb_resume_noirq(struct device *dev) 2416 { 2417 /* for static cmos like DaVinci, register values were preserved 2418 * unless for some reason the whole soc powered down or the USB 2419 * module got reset through the PSC (vs just being disabled). 2420 */ 2421 return 0; 2422 } 2423 2424 static int musb_runtime_suspend(struct device *dev) 2425 { 2426 struct musb *musb = dev_to_musb(dev); 2427 2428 musb_save_context(musb); 2429 2430 return 0; 2431 } 2432 2433 static int musb_runtime_resume(struct device *dev) 2434 { 2435 struct musb *musb = dev_to_musb(dev); 2436 static int first = 1; 2437 2438 /* 2439 * When pm_runtime_get_sync called for the first time in driver 2440 * init, some of the structure is still not initialized which is 2441 * used in restore function. But clock needs to be 2442 * enabled before any register access, so 2443 * pm_runtime_get_sync has to be called. 2444 * Also context restore without save does not make 2445 * any sense 2446 */ 2447 if (!first) 2448 musb_restore_context(musb); 2449 first = 0; 2450 2451 return 0; 2452 } 2453 2454 static const struct dev_pm_ops musb_dev_pm_ops = { 2455 .suspend = musb_suspend, 2456 .resume_noirq = musb_resume_noirq, 2457 .runtime_suspend = musb_runtime_suspend, 2458 .runtime_resume = musb_runtime_resume, 2459 }; 2460 2461 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2462 #else 2463 #define MUSB_DEV_PM_OPS NULL 2464 #endif 2465 2466 static struct platform_driver musb_driver = { 2467 .driver = { 2468 .name = (char *)musb_driver_name, 2469 .bus = &platform_bus_type, 2470 .owner = THIS_MODULE, 2471 .pm = MUSB_DEV_PM_OPS, 2472 }, 2473 .probe = musb_probe, 2474 .remove = __devexit_p(musb_remove), 2475 .shutdown = musb_shutdown, 2476 }; 2477 2478 /*-------------------------------------------------------------------------*/ 2479 2480 static int __init musb_init(void) 2481 { 2482 if (usb_disabled()) 2483 return 0; 2484 2485 pr_info("%s: version " MUSB_VERSION ", " 2486 "?dma?" 2487 ", " 2488 "otg (peripheral+host)", 2489 musb_driver_name); 2490 return platform_driver_register(&musb_driver); 2491 } 2492 module_init(musb_init); 2493 2494 static void __exit musb_cleanup(void) 2495 { 2496 platform_driver_unregister(&musb_driver); 2497 } 2498 module_exit(musb_cleanup); 2499 #endif 2500