1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #define __UBOOT__ 93 #ifndef __UBOOT__ 94 #include <linux/module.h> 95 #include <linux/kernel.h> 96 #include <linux/sched.h> 97 #include <linux/slab.h> 98 #include <linux/init.h> 99 #include <linux/list.h> 100 #include <linux/kobject.h> 101 #include <linux/prefetch.h> 102 #include <linux/platform_device.h> 103 #include <linux/io.h> 104 #else 105 #include <common.h> 106 #include <usb.h> 107 #include <asm/errno.h> 108 #include <linux/usb/ch9.h> 109 #include <linux/usb/gadget.h> 110 #include <linux/usb/musb.h> 111 #include <asm/io.h> 112 #include "linux-compat.h" 113 #include "usb-compat.h" 114 #endif 115 116 #include "musb_core.h" 117 118 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 119 120 121 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 122 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 123 124 #define MUSB_VERSION "6.0" 125 126 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 127 128 #define MUSB_DRIVER_NAME "musb-hdrc" 129 const char musb_driver_name[] = MUSB_DRIVER_NAME; 130 131 MODULE_DESCRIPTION(DRIVER_INFO); 132 MODULE_AUTHOR(DRIVER_AUTHOR); 133 MODULE_LICENSE("GPL"); 134 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 135 136 137 #ifndef __UBOOT__ 138 /*-------------------------------------------------------------------------*/ 139 140 static inline struct musb *dev_to_musb(struct device *dev) 141 { 142 return dev_get_drvdata(dev); 143 } 144 #endif 145 146 /*-------------------------------------------------------------------------*/ 147 148 #ifndef __UBOOT__ 149 #ifndef CONFIG_BLACKFIN 150 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 151 { 152 void __iomem *addr = phy->io_priv; 153 int i = 0; 154 u8 r; 155 u8 power; 156 int ret; 157 158 pm_runtime_get_sync(phy->io_dev); 159 160 /* Make sure the transceiver is not in low power mode */ 161 power = musb_readb(addr, MUSB_POWER); 162 power &= ~MUSB_POWER_SUSPENDM; 163 musb_writeb(addr, MUSB_POWER, power); 164 165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 167 */ 168 169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 172 173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 174 & MUSB_ULPI_REG_CMPLT)) { 175 i++; 176 if (i == 10000) { 177 ret = -ETIMEDOUT; 178 goto out; 179 } 180 181 } 182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 183 r &= ~MUSB_ULPI_REG_CMPLT; 184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 185 186 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 187 188 out: 189 pm_runtime_put(phy->io_dev); 190 191 return ret; 192 } 193 194 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 195 { 196 void __iomem *addr = phy->io_priv; 197 int i = 0; 198 u8 r = 0; 199 u8 power; 200 int ret = 0; 201 202 pm_runtime_get_sync(phy->io_dev); 203 204 /* Make sure the transceiver is not in low power mode */ 205 power = musb_readb(addr, MUSB_POWER); 206 power &= ~MUSB_POWER_SUSPENDM; 207 musb_writeb(addr, MUSB_POWER, power); 208 209 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 210 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 211 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 212 213 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 214 & MUSB_ULPI_REG_CMPLT)) { 215 i++; 216 if (i == 10000) { 217 ret = -ETIMEDOUT; 218 goto out; 219 } 220 } 221 222 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 223 r &= ~MUSB_ULPI_REG_CMPLT; 224 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 225 226 out: 227 pm_runtime_put(phy->io_dev); 228 229 return ret; 230 } 231 #else 232 #define musb_ulpi_read NULL 233 #define musb_ulpi_write NULL 234 #endif 235 236 static struct usb_phy_io_ops musb_ulpi_access = { 237 .read = musb_ulpi_read, 238 .write = musb_ulpi_write, 239 }; 240 #endif 241 242 /*-------------------------------------------------------------------------*/ 243 244 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 245 246 /* 247 * Load an endpoint's FIFO 248 */ 249 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 250 { 251 struct musb *musb = hw_ep->musb; 252 void __iomem *fifo = hw_ep->fifo; 253 254 prefetch((u8 *)src); 255 256 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 257 'T', hw_ep->epnum, fifo, len, src); 258 259 /* we can't assume unaligned reads work */ 260 if (likely((0x01 & (unsigned long) src) == 0)) { 261 u16 index = 0; 262 263 /* best case is 32bit-aligned source address */ 264 if ((0x02 & (unsigned long) src) == 0) { 265 if (len >= 4) { 266 writesl(fifo, src + index, len >> 2); 267 index += len & ~0x03; 268 } 269 if (len & 0x02) { 270 musb_writew(fifo, 0, *(u16 *)&src[index]); 271 index += 2; 272 } 273 } else { 274 if (len >= 2) { 275 writesw(fifo, src + index, len >> 1); 276 index += len & ~0x01; 277 } 278 } 279 if (len & 0x01) 280 musb_writeb(fifo, 0, src[index]); 281 } else { 282 /* byte aligned */ 283 writesb(fifo, src, len); 284 } 285 } 286 287 #if !defined(CONFIG_USB_MUSB_AM35X) 288 /* 289 * Unload an endpoint's FIFO 290 */ 291 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 292 { 293 struct musb *musb = hw_ep->musb; 294 void __iomem *fifo = hw_ep->fifo; 295 296 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 297 'R', hw_ep->epnum, fifo, len, dst); 298 299 /* we can't assume unaligned writes work */ 300 if (likely((0x01 & (unsigned long) dst) == 0)) { 301 u16 index = 0; 302 303 /* best case is 32bit-aligned destination address */ 304 if ((0x02 & (unsigned long) dst) == 0) { 305 if (len >= 4) { 306 readsl(fifo, dst, len >> 2); 307 index = len & ~0x03; 308 } 309 if (len & 0x02) { 310 *(u16 *)&dst[index] = musb_readw(fifo, 0); 311 index += 2; 312 } 313 } else { 314 if (len >= 2) { 315 readsw(fifo, dst, len >> 1); 316 index = len & ~0x01; 317 } 318 } 319 if (len & 0x01) 320 dst[index] = musb_readb(fifo, 0); 321 } else { 322 /* byte aligned */ 323 readsb(fifo, dst, len); 324 } 325 } 326 #endif 327 328 #endif /* normal PIO */ 329 330 331 /*-------------------------------------------------------------------------*/ 332 333 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 334 static const u8 musb_test_packet[53] = { 335 /* implicit SYNC then DATA0 to start */ 336 337 /* JKJKJKJK x9 */ 338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 339 /* JJKKJJKK x8 */ 340 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 341 /* JJJJKKKK x8 */ 342 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 343 /* JJJJJJJKKKKKKK x8 */ 344 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 345 /* JJJJJJJK x8 */ 346 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 347 /* JKKKKKKK x10, JK */ 348 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 349 350 /* implicit CRC16 then EOP to end */ 351 }; 352 353 void musb_load_testpacket(struct musb *musb) 354 { 355 void __iomem *regs = musb->endpoints[0].regs; 356 357 musb_ep_select(musb->mregs, 0); 358 musb_write_fifo(musb->control_ep, 359 sizeof(musb_test_packet), musb_test_packet); 360 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 361 } 362 363 #ifndef __UBOOT__ 364 /*-------------------------------------------------------------------------*/ 365 366 /* 367 * Handles OTG hnp timeouts, such as b_ase0_brst 368 */ 369 void musb_otg_timer_func(unsigned long data) 370 { 371 struct musb *musb = (struct musb *)data; 372 unsigned long flags; 373 374 spin_lock_irqsave(&musb->lock, flags); 375 switch (musb->xceiv->state) { 376 case OTG_STATE_B_WAIT_ACON: 377 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 378 musb_g_disconnect(musb); 379 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 380 musb->is_active = 0; 381 break; 382 case OTG_STATE_A_SUSPEND: 383 case OTG_STATE_A_WAIT_BCON: 384 dev_dbg(musb->controller, "HNP: %s timeout\n", 385 otg_state_string(musb->xceiv->state)); 386 musb_platform_set_vbus(musb, 0); 387 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 388 break; 389 default: 390 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 391 otg_state_string(musb->xceiv->state)); 392 } 393 musb->ignore_disconnect = 0; 394 spin_unlock_irqrestore(&musb->lock, flags); 395 } 396 397 /* 398 * Stops the HNP transition. Caller must take care of locking. 399 */ 400 void musb_hnp_stop(struct musb *musb) 401 { 402 struct usb_hcd *hcd = musb_to_hcd(musb); 403 void __iomem *mbase = musb->mregs; 404 u8 reg; 405 406 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 407 408 switch (musb->xceiv->state) { 409 case OTG_STATE_A_PERIPHERAL: 410 musb_g_disconnect(musb); 411 dev_dbg(musb->controller, "HNP: back to %s\n", 412 otg_state_string(musb->xceiv->state)); 413 break; 414 case OTG_STATE_B_HOST: 415 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 416 hcd->self.is_b_host = 0; 417 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 418 MUSB_DEV_MODE(musb); 419 reg = musb_readb(mbase, MUSB_POWER); 420 reg |= MUSB_POWER_SUSPENDM; 421 musb_writeb(mbase, MUSB_POWER, reg); 422 /* REVISIT: Start SESSION_REQUEST here? */ 423 break; 424 default: 425 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 426 otg_state_string(musb->xceiv->state)); 427 } 428 429 /* 430 * When returning to A state after HNP, avoid hub_port_rebounce(), 431 * which cause occasional OPT A "Did not receive reset after connect" 432 * errors. 433 */ 434 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 435 } 436 #endif 437 438 /* 439 * Interrupt Service Routine to record USB "global" interrupts. 440 * Since these do not happen often and signify things of 441 * paramount importance, it seems OK to check them individually; 442 * the order of the tests is specified in the manual 443 * 444 * @param musb instance pointer 445 * @param int_usb register contents 446 * @param devctl 447 * @param power 448 */ 449 450 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 451 u8 devctl, u8 power) 452 { 453 #ifndef __UBOOT__ 454 struct usb_otg *otg = musb->xceiv->otg; 455 #endif 456 irqreturn_t handled = IRQ_NONE; 457 458 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 459 int_usb); 460 461 #ifndef __UBOOT__ 462 /* in host mode, the peripheral may issue remote wakeup. 463 * in peripheral mode, the host may resume the link. 464 * spurious RESUME irqs happen too, paired with SUSPEND. 465 */ 466 if (int_usb & MUSB_INTR_RESUME) { 467 handled = IRQ_HANDLED; 468 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 469 470 if (devctl & MUSB_DEVCTL_HM) { 471 void __iomem *mbase = musb->mregs; 472 473 switch (musb->xceiv->state) { 474 case OTG_STATE_A_SUSPEND: 475 /* remote wakeup? later, GetPortStatus 476 * will stop RESUME signaling 477 */ 478 479 if (power & MUSB_POWER_SUSPENDM) { 480 /* spurious */ 481 musb->int_usb &= ~MUSB_INTR_SUSPEND; 482 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 483 break; 484 } 485 486 power &= ~MUSB_POWER_SUSPENDM; 487 musb_writeb(mbase, MUSB_POWER, 488 power | MUSB_POWER_RESUME); 489 490 musb->port1_status |= 491 (USB_PORT_STAT_C_SUSPEND << 16) 492 | MUSB_PORT_STAT_RESUME; 493 musb->rh_timer = jiffies 494 + msecs_to_jiffies(20); 495 496 musb->xceiv->state = OTG_STATE_A_HOST; 497 musb->is_active = 1; 498 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 499 break; 500 case OTG_STATE_B_WAIT_ACON: 501 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 502 musb->is_active = 1; 503 MUSB_DEV_MODE(musb); 504 break; 505 default: 506 WARNING("bogus %s RESUME (%s)\n", 507 "host", 508 otg_state_string(musb->xceiv->state)); 509 } 510 } else { 511 switch (musb->xceiv->state) { 512 case OTG_STATE_A_SUSPEND: 513 /* possibly DISCONNECT is upcoming */ 514 musb->xceiv->state = OTG_STATE_A_HOST; 515 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 516 break; 517 case OTG_STATE_B_WAIT_ACON: 518 case OTG_STATE_B_PERIPHERAL: 519 /* disconnect while suspended? we may 520 * not get a disconnect irq... 521 */ 522 if ((devctl & MUSB_DEVCTL_VBUS) 523 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 524 ) { 525 musb->int_usb |= MUSB_INTR_DISCONNECT; 526 musb->int_usb &= ~MUSB_INTR_SUSPEND; 527 break; 528 } 529 musb_g_resume(musb); 530 break; 531 case OTG_STATE_B_IDLE: 532 musb->int_usb &= ~MUSB_INTR_SUSPEND; 533 break; 534 default: 535 WARNING("bogus %s RESUME (%s)\n", 536 "peripheral", 537 otg_state_string(musb->xceiv->state)); 538 } 539 } 540 } 541 542 /* see manual for the order of the tests */ 543 if (int_usb & MUSB_INTR_SESSREQ) { 544 void __iomem *mbase = musb->mregs; 545 546 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 547 && (devctl & MUSB_DEVCTL_BDEVICE)) { 548 dev_dbg(musb->controller, "SessReq while on B state\n"); 549 return IRQ_HANDLED; 550 } 551 552 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 553 otg_state_string(musb->xceiv->state)); 554 555 /* IRQ arrives from ID pin sense or (later, if VBUS power 556 * is removed) SRP. responses are time critical: 557 * - turn on VBUS (with silicon-specific mechanism) 558 * - go through A_WAIT_VRISE 559 * - ... to A_WAIT_BCON. 560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 561 */ 562 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 563 musb->ep0_stage = MUSB_EP0_START; 564 musb->xceiv->state = OTG_STATE_A_IDLE; 565 MUSB_HST_MODE(musb); 566 musb_platform_set_vbus(musb, 1); 567 568 handled = IRQ_HANDLED; 569 } 570 571 if (int_usb & MUSB_INTR_VBUSERROR) { 572 int ignore = 0; 573 574 /* During connection as an A-Device, we may see a short 575 * current spikes causing voltage drop, because of cable 576 * and peripheral capacitance combined with vbus draw. 577 * (So: less common with truly self-powered devices, where 578 * vbus doesn't act like a power supply.) 579 * 580 * Such spikes are short; usually less than ~500 usec, max 581 * of ~2 msec. That is, they're not sustained overcurrent 582 * errors, though they're reported using VBUSERROR irqs. 583 * 584 * Workarounds: (a) hardware: use self powered devices. 585 * (b) software: ignore non-repeated VBUS errors. 586 * 587 * REVISIT: do delays from lots of DEBUG_KERNEL checks 588 * make trouble here, keeping VBUS < 4.4V ? 589 */ 590 switch (musb->xceiv->state) { 591 case OTG_STATE_A_HOST: 592 /* recovery is dicey once we've gotten past the 593 * initial stages of enumeration, but if VBUS 594 * stayed ok at the other end of the link, and 595 * another reset is due (at least for high speed, 596 * to redo the chirp etc), it might work OK... 597 */ 598 case OTG_STATE_A_WAIT_BCON: 599 case OTG_STATE_A_WAIT_VRISE: 600 if (musb->vbuserr_retry) { 601 void __iomem *mbase = musb->mregs; 602 603 musb->vbuserr_retry--; 604 ignore = 1; 605 devctl |= MUSB_DEVCTL_SESSION; 606 musb_writeb(mbase, MUSB_DEVCTL, devctl); 607 } else { 608 musb->port1_status |= 609 USB_PORT_STAT_OVERCURRENT 610 | (USB_PORT_STAT_C_OVERCURRENT << 16); 611 } 612 break; 613 default: 614 break; 615 } 616 617 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 618 otg_state_string(musb->xceiv->state), 619 devctl, 620 ({ char *s; 621 switch (devctl & MUSB_DEVCTL_VBUS) { 622 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 623 s = "<SessEnd"; break; 624 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 625 s = "<AValid"; break; 626 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 627 s = "<VBusValid"; break; 628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 629 default: 630 s = "VALID"; break; 631 }; s; }), 632 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 633 musb->port1_status); 634 635 /* go through A_WAIT_VFALL then start a new session */ 636 if (!ignore) 637 musb_platform_set_vbus(musb, 0); 638 handled = IRQ_HANDLED; 639 } 640 641 if (int_usb & MUSB_INTR_SUSPEND) { 642 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 643 otg_state_string(musb->xceiv->state), devctl, power); 644 handled = IRQ_HANDLED; 645 646 switch (musb->xceiv->state) { 647 case OTG_STATE_A_PERIPHERAL: 648 /* We also come here if the cable is removed, since 649 * this silicon doesn't report ID-no-longer-grounded. 650 * 651 * We depend on T(a_wait_bcon) to shut us down, and 652 * hope users don't do anything dicey during this 653 * undesired detour through A_WAIT_BCON. 654 */ 655 musb_hnp_stop(musb); 656 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 657 musb_root_disconnect(musb); 658 musb_platform_try_idle(musb, jiffies 659 + msecs_to_jiffies(musb->a_wait_bcon 660 ? : OTG_TIME_A_WAIT_BCON)); 661 662 break; 663 case OTG_STATE_B_IDLE: 664 if (!musb->is_active) 665 break; 666 case OTG_STATE_B_PERIPHERAL: 667 musb_g_suspend(musb); 668 musb->is_active = is_otg_enabled(musb) 669 && otg->gadget->b_hnp_enable; 670 if (musb->is_active) { 671 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 672 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 673 mod_timer(&musb->otg_timer, jiffies 674 + msecs_to_jiffies( 675 OTG_TIME_B_ASE0_BRST)); 676 } 677 break; 678 case OTG_STATE_A_WAIT_BCON: 679 if (musb->a_wait_bcon != 0) 680 musb_platform_try_idle(musb, jiffies 681 + msecs_to_jiffies(musb->a_wait_bcon)); 682 break; 683 case OTG_STATE_A_HOST: 684 musb->xceiv->state = OTG_STATE_A_SUSPEND; 685 musb->is_active = is_otg_enabled(musb) 686 && otg->host->b_hnp_enable; 687 break; 688 case OTG_STATE_B_HOST: 689 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 690 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 691 break; 692 default: 693 /* "should not happen" */ 694 musb->is_active = 0; 695 break; 696 } 697 } 698 #endif 699 700 if (int_usb & MUSB_INTR_CONNECT) { 701 struct usb_hcd *hcd = musb_to_hcd(musb); 702 703 handled = IRQ_HANDLED; 704 musb->is_active = 1; 705 706 musb->ep0_stage = MUSB_EP0_START; 707 708 /* flush endpoints when transitioning from Device Mode */ 709 if (is_peripheral_active(musb)) { 710 /* REVISIT HNP; just force disconnect */ 711 } 712 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 713 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 714 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 715 #ifndef __UBOOT__ 716 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 717 |USB_PORT_STAT_HIGH_SPEED 718 |USB_PORT_STAT_ENABLE 719 ); 720 musb->port1_status |= USB_PORT_STAT_CONNECTION 721 |(USB_PORT_STAT_C_CONNECTION << 16); 722 723 /* high vs full speed is just a guess until after reset */ 724 if (devctl & MUSB_DEVCTL_LSDEV) 725 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 726 727 /* indicate new connection to OTG machine */ 728 switch (musb->xceiv->state) { 729 case OTG_STATE_B_PERIPHERAL: 730 if (int_usb & MUSB_INTR_SUSPEND) { 731 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 732 int_usb &= ~MUSB_INTR_SUSPEND; 733 goto b_host; 734 } else 735 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 736 break; 737 case OTG_STATE_B_WAIT_ACON: 738 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 739 b_host: 740 musb->xceiv->state = OTG_STATE_B_HOST; 741 hcd->self.is_b_host = 1; 742 musb->ignore_disconnect = 0; 743 del_timer(&musb->otg_timer); 744 break; 745 default: 746 if ((devctl & MUSB_DEVCTL_VBUS) 747 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 748 musb->xceiv->state = OTG_STATE_A_HOST; 749 hcd->self.is_b_host = 0; 750 } 751 break; 752 } 753 754 /* poke the root hub */ 755 MUSB_HST_MODE(musb); 756 if (hcd->status_urb) 757 usb_hcd_poll_rh_status(hcd); 758 else 759 usb_hcd_resume_root_hub(hcd); 760 761 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 762 otg_state_string(musb->xceiv->state), devctl); 763 #endif 764 } 765 766 #ifndef __UBOOT__ 767 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 768 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 769 otg_state_string(musb->xceiv->state), 770 MUSB_MODE(musb), devctl); 771 handled = IRQ_HANDLED; 772 773 switch (musb->xceiv->state) { 774 case OTG_STATE_A_HOST: 775 case OTG_STATE_A_SUSPEND: 776 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 777 musb_root_disconnect(musb); 778 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 779 musb_platform_try_idle(musb, jiffies 780 + msecs_to_jiffies(musb->a_wait_bcon)); 781 break; 782 case OTG_STATE_B_HOST: 783 /* REVISIT this behaves for "real disconnect" 784 * cases; make sure the other transitions from 785 * from B_HOST act right too. The B_HOST code 786 * in hnp_stop() is currently not used... 787 */ 788 musb_root_disconnect(musb); 789 musb_to_hcd(musb)->self.is_b_host = 0; 790 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 791 MUSB_DEV_MODE(musb); 792 musb_g_disconnect(musb); 793 break; 794 case OTG_STATE_A_PERIPHERAL: 795 musb_hnp_stop(musb); 796 musb_root_disconnect(musb); 797 /* FALLTHROUGH */ 798 case OTG_STATE_B_WAIT_ACON: 799 /* FALLTHROUGH */ 800 case OTG_STATE_B_PERIPHERAL: 801 case OTG_STATE_B_IDLE: 802 musb_g_disconnect(musb); 803 break; 804 default: 805 WARNING("unhandled DISCONNECT transition (%s)\n", 806 otg_state_string(musb->xceiv->state)); 807 break; 808 } 809 } 810 811 /* mentor saves a bit: bus reset and babble share the same irq. 812 * only host sees babble; only peripheral sees bus reset. 813 */ 814 if (int_usb & MUSB_INTR_RESET) { 815 handled = IRQ_HANDLED; 816 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 817 /* 818 * Looks like non-HS BABBLE can be ignored, but 819 * HS BABBLE is an error condition. For HS the solution 820 * is to avoid babble in the first place and fix what 821 * caused BABBLE. When HS BABBLE happens we can only 822 * stop the session. 823 */ 824 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 825 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 826 else { 827 ERR("Stopping host session -- babble\n"); 828 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 829 } 830 } else if (is_peripheral_capable()) { 831 dev_dbg(musb->controller, "BUS RESET as %s\n", 832 otg_state_string(musb->xceiv->state)); 833 switch (musb->xceiv->state) { 834 case OTG_STATE_A_SUSPEND: 835 /* We need to ignore disconnect on suspend 836 * otherwise tusb 2.0 won't reconnect after a 837 * power cycle, which breaks otg compliance. 838 */ 839 musb->ignore_disconnect = 1; 840 musb_g_reset(musb); 841 /* FALLTHROUGH */ 842 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 843 /* never use invalid T(a_wait_bcon) */ 844 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 845 otg_state_string(musb->xceiv->state), 846 TA_WAIT_BCON(musb)); 847 mod_timer(&musb->otg_timer, jiffies 848 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 849 break; 850 case OTG_STATE_A_PERIPHERAL: 851 musb->ignore_disconnect = 0; 852 del_timer(&musb->otg_timer); 853 musb_g_reset(musb); 854 break; 855 case OTG_STATE_B_WAIT_ACON: 856 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 857 otg_state_string(musb->xceiv->state)); 858 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 859 musb_g_reset(musb); 860 break; 861 case OTG_STATE_B_IDLE: 862 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 863 /* FALLTHROUGH */ 864 case OTG_STATE_B_PERIPHERAL: 865 musb_g_reset(musb); 866 break; 867 default: 868 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 869 otg_state_string(musb->xceiv->state)); 870 } 871 } 872 } 873 #endif 874 875 #if 0 876 /* REVISIT ... this would be for multiplexing periodic endpoints, or 877 * supporting transfer phasing to prevent exceeding ISO bandwidth 878 * limits of a given frame or microframe. 879 * 880 * It's not needed for peripheral side, which dedicates endpoints; 881 * though it _might_ use SOF irqs for other purposes. 882 * 883 * And it's not currently needed for host side, which also dedicates 884 * endpoints, relies on TX/RX interval registers, and isn't claimed 885 * to support ISO transfers yet. 886 */ 887 if (int_usb & MUSB_INTR_SOF) { 888 void __iomem *mbase = musb->mregs; 889 struct musb_hw_ep *ep; 890 u8 epnum; 891 u16 frame; 892 893 dev_dbg(musb->controller, "START_OF_FRAME\n"); 894 handled = IRQ_HANDLED; 895 896 /* start any periodic Tx transfers waiting for current frame */ 897 frame = musb_readw(mbase, MUSB_FRAME); 898 ep = musb->endpoints; 899 for (epnum = 1; (epnum < musb->nr_endpoints) 900 && (musb->epmask >= (1 << epnum)); 901 epnum++, ep++) { 902 /* 903 * FIXME handle framecounter wraps (12 bits) 904 * eliminate duplicated StartUrb logic 905 */ 906 if (ep->dwWaitFrame >= frame) { 907 ep->dwWaitFrame = 0; 908 pr_debug("SOF --> periodic TX%s on %d\n", 909 ep->tx_channel ? " DMA" : "", 910 epnum); 911 if (!ep->tx_channel) 912 musb_h_tx_start(musb, epnum); 913 else 914 cppi_hostdma_start(musb, epnum); 915 } 916 } /* end of for loop */ 917 } 918 #endif 919 920 schedule_work(&musb->irq_work); 921 922 return handled; 923 } 924 925 /*-------------------------------------------------------------------------*/ 926 927 /* 928 * Program the HDRC to start (enable interrupts, dma, etc.). 929 */ 930 void musb_start(struct musb *musb) 931 { 932 void __iomem *regs = musb->mregs; 933 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 934 935 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 936 937 /* Set INT enable registers, enable interrupts */ 938 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 939 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 940 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 941 942 musb_writeb(regs, MUSB_TESTMODE, 0); 943 944 /* put into basic highspeed mode and start session */ 945 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 946 #ifdef CONFIG_USB_GADGET_DUALSPEED 947 | MUSB_POWER_HSENAB 948 #endif 949 /* ENSUSPEND wedges tusb */ 950 /* | MUSB_POWER_ENSUSPEND */ 951 ); 952 953 musb->is_active = 0; 954 devctl = musb_readb(regs, MUSB_DEVCTL); 955 devctl &= ~MUSB_DEVCTL_SESSION; 956 957 if (is_otg_enabled(musb)) { 958 #ifndef __UBOOT__ 959 /* session started after: 960 * (a) ID-grounded irq, host mode; 961 * (b) vbus present/connect IRQ, peripheral mode; 962 * (c) peripheral initiates, using SRP 963 */ 964 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 965 musb->is_active = 1; 966 else 967 devctl |= MUSB_DEVCTL_SESSION; 968 #endif 969 970 } else if (is_host_enabled(musb)) { 971 /* assume ID pin is hard-wired to ground */ 972 devctl |= MUSB_DEVCTL_SESSION; 973 974 } else /* peripheral is enabled */ { 975 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 976 musb->is_active = 1; 977 } 978 musb_platform_enable(musb); 979 musb_writeb(regs, MUSB_DEVCTL, devctl); 980 } 981 982 983 static void musb_generic_disable(struct musb *musb) 984 { 985 void __iomem *mbase = musb->mregs; 986 u16 temp; 987 988 /* disable interrupts */ 989 musb_writeb(mbase, MUSB_INTRUSBE, 0); 990 musb_writew(mbase, MUSB_INTRTXE, 0); 991 musb_writew(mbase, MUSB_INTRRXE, 0); 992 993 /* off */ 994 musb_writeb(mbase, MUSB_DEVCTL, 0); 995 996 /* flush pending interrupts */ 997 temp = musb_readb(mbase, MUSB_INTRUSB); 998 temp = musb_readw(mbase, MUSB_INTRTX); 999 temp = musb_readw(mbase, MUSB_INTRRX); 1000 1001 } 1002 1003 /* 1004 * Make the HDRC stop (disable interrupts, etc.); 1005 * reversible by musb_start 1006 * called on gadget driver unregister 1007 * with controller locked, irqs blocked 1008 * acts as a NOP unless some role activated the hardware 1009 */ 1010 void musb_stop(struct musb *musb) 1011 { 1012 /* stop IRQs, timers, ... */ 1013 musb_platform_disable(musb); 1014 musb_generic_disable(musb); 1015 dev_dbg(musb->controller, "HDRC disabled\n"); 1016 1017 /* FIXME 1018 * - mark host and/or peripheral drivers unusable/inactive 1019 * - disable DMA (and enable it in HdrcStart) 1020 * - make sure we can musb_start() after musb_stop(); with 1021 * OTG mode, gadget driver module rmmod/modprobe cycles that 1022 * - ... 1023 */ 1024 musb_platform_try_idle(musb, 0); 1025 } 1026 1027 #ifndef __UBOOT__ 1028 static void musb_shutdown(struct platform_device *pdev) 1029 { 1030 struct musb *musb = dev_to_musb(&pdev->dev); 1031 unsigned long flags; 1032 1033 pm_runtime_get_sync(musb->controller); 1034 1035 musb_gadget_cleanup(musb); 1036 1037 spin_lock_irqsave(&musb->lock, flags); 1038 musb_platform_disable(musb); 1039 musb_generic_disable(musb); 1040 spin_unlock_irqrestore(&musb->lock, flags); 1041 1042 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1043 usb_remove_hcd(musb_to_hcd(musb)); 1044 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1045 musb_platform_exit(musb); 1046 1047 pm_runtime_put(musb->controller); 1048 /* FIXME power down */ 1049 } 1050 #endif 1051 1052 1053 /*-------------------------------------------------------------------------*/ 1054 1055 /* 1056 * The silicon either has hard-wired endpoint configurations, or else 1057 * "dynamic fifo" sizing. The driver has support for both, though at this 1058 * writing only the dynamic sizing is very well tested. Since we switched 1059 * away from compile-time hardware parameters, we can no longer rely on 1060 * dead code elimination to leave only the relevant one in the object file. 1061 * 1062 * We don't currently use dynamic fifo setup capability to do anything 1063 * more than selecting one of a bunch of predefined configurations. 1064 */ 1065 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1066 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1067 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1068 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1069 || defined(CONFIG_USB_MUSB_AM35X) \ 1070 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1071 || defined(CONFIG_USB_MUSB_DSPS) \ 1072 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1073 static ushort __devinitdata fifo_mode = 4; 1074 #elif defined(CONFIG_USB_MUSB_UX500) \ 1075 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1076 static ushort __devinitdata fifo_mode = 5; 1077 #else 1078 static ushort __devinitdata fifo_mode = 2; 1079 #endif 1080 1081 /* "modprobe ... fifo_mode=1" etc */ 1082 module_param(fifo_mode, ushort, 0); 1083 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1084 1085 /* 1086 * tables defining fifo_mode values. define more if you like. 1087 * for host side, make sure both halves of ep1 are set up. 1088 */ 1089 1090 /* mode 0 - fits in 2KB */ 1091 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1092 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1093 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1094 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1095 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1096 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1097 }; 1098 1099 /* mode 1 - fits in 4KB */ 1100 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1101 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1102 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1103 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1104 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1105 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1106 }; 1107 1108 /* mode 2 - fits in 4KB */ 1109 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1110 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1111 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1112 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1113 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1114 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1115 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1116 }; 1117 1118 /* mode 3 - fits in 4KB */ 1119 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1120 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1121 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1122 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1123 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1124 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1125 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1126 }; 1127 1128 /* mode 4 - fits in 16KB */ 1129 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1130 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1131 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1132 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1133 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1134 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1135 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1136 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1137 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1138 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1139 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1140 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1141 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1142 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1143 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1144 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1145 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1146 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1147 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1148 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1149 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1150 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1151 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1152 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1153 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1154 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1155 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1156 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1157 }; 1158 1159 /* mode 5 - fits in 8KB */ 1160 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1161 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1162 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1163 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1164 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1165 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1166 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1167 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1168 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1169 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1170 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1171 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1172 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1173 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1174 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1175 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1176 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1177 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1178 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1179 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1180 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1181 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1182 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1183 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1184 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1185 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1186 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1187 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1188 }; 1189 1190 /* 1191 * configure a fifo; for non-shared endpoints, this may be called 1192 * once for a tx fifo and once for an rx fifo. 1193 * 1194 * returns negative errno or offset for next fifo. 1195 */ 1196 static int __devinit 1197 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1198 const struct musb_fifo_cfg *cfg, u16 offset) 1199 { 1200 void __iomem *mbase = musb->mregs; 1201 int size = 0; 1202 u16 maxpacket = cfg->maxpacket; 1203 u16 c_off = offset >> 3; 1204 u8 c_size; 1205 1206 /* expect hw_ep has already been zero-initialized */ 1207 1208 size = ffs(max(maxpacket, (u16) 8)) - 1; 1209 maxpacket = 1 << size; 1210 1211 c_size = size - 3; 1212 if (cfg->mode == BUF_DOUBLE) { 1213 if ((offset + (maxpacket << 1)) > 1214 (1 << (musb->config->ram_bits + 2))) 1215 return -EMSGSIZE; 1216 c_size |= MUSB_FIFOSZ_DPB; 1217 } else { 1218 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1219 return -EMSGSIZE; 1220 } 1221 1222 /* configure the FIFO */ 1223 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1224 1225 /* EP0 reserved endpoint for control, bidirectional; 1226 * EP1 reserved for bulk, two unidirection halves. 1227 */ 1228 if (hw_ep->epnum == 1) 1229 musb->bulk_ep = hw_ep; 1230 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1231 switch (cfg->style) { 1232 case FIFO_TX: 1233 musb_write_txfifosz(mbase, c_size); 1234 musb_write_txfifoadd(mbase, c_off); 1235 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1236 hw_ep->max_packet_sz_tx = maxpacket; 1237 break; 1238 case FIFO_RX: 1239 musb_write_rxfifosz(mbase, c_size); 1240 musb_write_rxfifoadd(mbase, c_off); 1241 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1242 hw_ep->max_packet_sz_rx = maxpacket; 1243 break; 1244 case FIFO_RXTX: 1245 musb_write_txfifosz(mbase, c_size); 1246 musb_write_txfifoadd(mbase, c_off); 1247 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1248 hw_ep->max_packet_sz_rx = maxpacket; 1249 1250 musb_write_rxfifosz(mbase, c_size); 1251 musb_write_rxfifoadd(mbase, c_off); 1252 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1253 hw_ep->max_packet_sz_tx = maxpacket; 1254 1255 hw_ep->is_shared_fifo = true; 1256 break; 1257 } 1258 1259 /* NOTE rx and tx endpoint irqs aren't managed separately, 1260 * which happens to be ok 1261 */ 1262 musb->epmask |= (1 << hw_ep->epnum); 1263 1264 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1265 } 1266 1267 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1268 .style = FIFO_RXTX, .maxpacket = 64, 1269 }; 1270 1271 static int __devinit ep_config_from_table(struct musb *musb) 1272 { 1273 const struct musb_fifo_cfg *cfg; 1274 unsigned i, n; 1275 int offset; 1276 struct musb_hw_ep *hw_ep = musb->endpoints; 1277 1278 if (musb->config->fifo_cfg) { 1279 cfg = musb->config->fifo_cfg; 1280 n = musb->config->fifo_cfg_size; 1281 goto done; 1282 } 1283 1284 switch (fifo_mode) { 1285 default: 1286 fifo_mode = 0; 1287 /* FALLTHROUGH */ 1288 case 0: 1289 cfg = mode_0_cfg; 1290 n = ARRAY_SIZE(mode_0_cfg); 1291 break; 1292 case 1: 1293 cfg = mode_1_cfg; 1294 n = ARRAY_SIZE(mode_1_cfg); 1295 break; 1296 case 2: 1297 cfg = mode_2_cfg; 1298 n = ARRAY_SIZE(mode_2_cfg); 1299 break; 1300 case 3: 1301 cfg = mode_3_cfg; 1302 n = ARRAY_SIZE(mode_3_cfg); 1303 break; 1304 case 4: 1305 cfg = mode_4_cfg; 1306 n = ARRAY_SIZE(mode_4_cfg); 1307 break; 1308 case 5: 1309 cfg = mode_5_cfg; 1310 n = ARRAY_SIZE(mode_5_cfg); 1311 break; 1312 } 1313 1314 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1315 1316 done: 1317 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1318 /* assert(offset > 0) */ 1319 1320 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1321 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1322 */ 1323 1324 for (i = 0; i < n; i++) { 1325 u8 epn = cfg->hw_ep_num; 1326 1327 if (epn >= musb->config->num_eps) { 1328 pr_debug("%s: invalid ep %d\n", 1329 musb_driver_name, epn); 1330 return -EINVAL; 1331 } 1332 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1333 if (offset < 0) { 1334 pr_debug("%s: mem overrun, ep %d\n", 1335 musb_driver_name, epn); 1336 return -EINVAL; 1337 } 1338 epn++; 1339 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1340 } 1341 1342 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, 1343 musb->config->num_eps * 2 - 1, offset, 1344 (1 << (musb->config->ram_bits + 2))); 1345 1346 if (!musb->bulk_ep) { 1347 pr_debug("%s: missing bulk\n", musb_driver_name); 1348 return -EINVAL; 1349 } 1350 1351 return 0; 1352 } 1353 1354 1355 /* 1356 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1357 * @param musb the controller 1358 */ 1359 static int __devinit ep_config_from_hw(struct musb *musb) 1360 { 1361 u8 epnum = 0; 1362 struct musb_hw_ep *hw_ep; 1363 void *mbase = musb->mregs; 1364 int ret = 0; 1365 1366 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1367 1368 /* FIXME pick up ep0 maxpacket size */ 1369 1370 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1371 musb_ep_select(mbase, epnum); 1372 hw_ep = musb->endpoints + epnum; 1373 1374 ret = musb_read_fifosize(musb, hw_ep, epnum); 1375 if (ret < 0) 1376 break; 1377 1378 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1379 1380 /* pick an RX/TX endpoint for bulk */ 1381 if (hw_ep->max_packet_sz_tx < 512 1382 || hw_ep->max_packet_sz_rx < 512) 1383 continue; 1384 1385 /* REVISIT: this algorithm is lazy, we should at least 1386 * try to pick a double buffered endpoint. 1387 */ 1388 if (musb->bulk_ep) 1389 continue; 1390 musb->bulk_ep = hw_ep; 1391 } 1392 1393 if (!musb->bulk_ep) { 1394 pr_debug("%s: missing bulk\n", musb_driver_name); 1395 return -EINVAL; 1396 } 1397 1398 return 0; 1399 } 1400 1401 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1402 1403 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1404 * configure endpoints, or take their config from silicon 1405 */ 1406 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1407 { 1408 u8 reg; 1409 char *type; 1410 char aInfo[90], aRevision[32], aDate[12]; 1411 void __iomem *mbase = musb->mregs; 1412 int status = 0; 1413 int i; 1414 1415 /* log core options (read using indexed model) */ 1416 reg = musb_read_configdata(mbase); 1417 1418 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1419 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1420 strcat(aInfo, ", dyn FIFOs"); 1421 musb->dyn_fifo = true; 1422 } 1423 #ifndef CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT 1424 if (reg & MUSB_CONFIGDATA_MPRXE) { 1425 strcat(aInfo, ", bulk combine"); 1426 musb->bulk_combine = true; 1427 } 1428 if (reg & MUSB_CONFIGDATA_MPTXE) { 1429 strcat(aInfo, ", bulk split"); 1430 musb->bulk_split = true; 1431 } 1432 #else 1433 musb->bulk_combine = false; 1434 musb->bulk_split = false; 1435 #endif 1436 if (reg & MUSB_CONFIGDATA_HBRXE) { 1437 strcat(aInfo, ", HB-ISO Rx"); 1438 musb->hb_iso_rx = true; 1439 } 1440 if (reg & MUSB_CONFIGDATA_HBTXE) { 1441 strcat(aInfo, ", HB-ISO Tx"); 1442 musb->hb_iso_tx = true; 1443 } 1444 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1445 strcat(aInfo, ", SoftConn"); 1446 1447 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1448 1449 aDate[0] = 0; 1450 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1451 musb->is_multipoint = 1; 1452 type = "M"; 1453 } else { 1454 musb->is_multipoint = 0; 1455 type = ""; 1456 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1457 printk(KERN_ERR 1458 "%s: kernel must blacklist external hubs\n", 1459 musb_driver_name); 1460 #endif 1461 } 1462 1463 /* log release info */ 1464 musb->hwvers = musb_read_hwvers(mbase); 1465 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1466 MUSB_HWVERS_MINOR(musb->hwvers), 1467 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1468 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, 1469 aRevision, aDate); 1470 1471 /* configure ep0 */ 1472 musb_configure_ep0(musb); 1473 1474 /* discover endpoint configuration */ 1475 musb->nr_endpoints = 1; 1476 musb->epmask = 1; 1477 1478 if (musb->dyn_fifo) 1479 status = ep_config_from_table(musb); 1480 else 1481 status = ep_config_from_hw(musb); 1482 1483 if (status < 0) 1484 return status; 1485 1486 /* finish init, and print endpoint config */ 1487 for (i = 0; i < musb->nr_endpoints; i++) { 1488 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1489 1490 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1491 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1492 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1493 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1494 hw_ep->fifo_sync_va = 1495 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1496 1497 if (i == 0) 1498 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1499 else 1500 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1501 #endif 1502 1503 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1504 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1505 hw_ep->rx_reinit = 1; 1506 hw_ep->tx_reinit = 1; 1507 1508 if (hw_ep->max_packet_sz_tx) { 1509 dev_dbg(musb->controller, 1510 "%s: hw_ep %d%s, %smax %d\n", 1511 musb_driver_name, i, 1512 hw_ep->is_shared_fifo ? "shared" : "tx", 1513 hw_ep->tx_double_buffered 1514 ? "doublebuffer, " : "", 1515 hw_ep->max_packet_sz_tx); 1516 } 1517 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1518 dev_dbg(musb->controller, 1519 "%s: hw_ep %d%s, %smax %d\n", 1520 musb_driver_name, i, 1521 "rx", 1522 hw_ep->rx_double_buffered 1523 ? "doublebuffer, " : "", 1524 hw_ep->max_packet_sz_rx); 1525 } 1526 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1527 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1528 } 1529 1530 return 0; 1531 } 1532 1533 /*-------------------------------------------------------------------------*/ 1534 1535 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1536 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1537 1538 static irqreturn_t generic_interrupt(int irq, void *__hci) 1539 { 1540 unsigned long flags; 1541 irqreturn_t retval = IRQ_NONE; 1542 struct musb *musb = __hci; 1543 1544 spin_lock_irqsave(&musb->lock, flags); 1545 1546 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1547 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1548 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1549 1550 if (musb->int_usb || musb->int_tx || musb->int_rx) 1551 retval = musb_interrupt(musb); 1552 1553 spin_unlock_irqrestore(&musb->lock, flags); 1554 1555 return retval; 1556 } 1557 1558 #else 1559 #define generic_interrupt NULL 1560 #endif 1561 1562 /* 1563 * handle all the irqs defined by the HDRC core. for now we expect: other 1564 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1565 * will be assigned, and the irq will already have been acked. 1566 * 1567 * called in irq context with spinlock held, irqs blocked 1568 */ 1569 irqreturn_t musb_interrupt(struct musb *musb) 1570 { 1571 irqreturn_t retval = IRQ_NONE; 1572 u8 devctl, power; 1573 int ep_num; 1574 u32 reg; 1575 1576 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1577 power = musb_readb(musb->mregs, MUSB_POWER); 1578 1579 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1580 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1581 musb->int_usb, musb->int_tx, musb->int_rx); 1582 1583 /* the core can interrupt us for multiple reasons; docs have 1584 * a generic interrupt flowchart to follow 1585 */ 1586 if (musb->int_usb) 1587 retval |= musb_stage0_irq(musb, musb->int_usb, 1588 devctl, power); 1589 1590 /* "stage 1" is handling endpoint irqs */ 1591 1592 /* handle endpoint 0 first */ 1593 if (musb->int_tx & 1) { 1594 if (devctl & MUSB_DEVCTL_HM) { 1595 if (is_host_capable()) 1596 retval |= musb_h_ep0_irq(musb); 1597 } else { 1598 if (is_peripheral_capable()) 1599 retval |= musb_g_ep0_irq(musb); 1600 } 1601 } 1602 1603 /* RX on endpoints 1-15 */ 1604 reg = musb->int_rx >> 1; 1605 ep_num = 1; 1606 while (reg) { 1607 if (reg & 1) { 1608 /* musb_ep_select(musb->mregs, ep_num); */ 1609 /* REVISIT just retval = ep->rx_irq(...) */ 1610 retval = IRQ_HANDLED; 1611 if (devctl & MUSB_DEVCTL_HM) { 1612 if (is_host_capable()) 1613 musb_host_rx(musb, ep_num); 1614 } else { 1615 if (is_peripheral_capable()) 1616 musb_g_rx(musb, ep_num); 1617 } 1618 } 1619 1620 reg >>= 1; 1621 ep_num++; 1622 } 1623 1624 /* TX on endpoints 1-15 */ 1625 reg = musb->int_tx >> 1; 1626 ep_num = 1; 1627 while (reg) { 1628 if (reg & 1) { 1629 /* musb_ep_select(musb->mregs, ep_num); */ 1630 /* REVISIT just retval |= ep->tx_irq(...) */ 1631 retval = IRQ_HANDLED; 1632 if (devctl & MUSB_DEVCTL_HM) { 1633 if (is_host_capable()) 1634 musb_host_tx(musb, ep_num); 1635 } else { 1636 if (is_peripheral_capable()) 1637 musb_g_tx(musb, ep_num); 1638 } 1639 } 1640 reg >>= 1; 1641 ep_num++; 1642 } 1643 1644 return retval; 1645 } 1646 EXPORT_SYMBOL_GPL(musb_interrupt); 1647 1648 #ifndef CONFIG_MUSB_PIO_ONLY 1649 static bool __devinitdata use_dma = 1; 1650 1651 /* "modprobe ... use_dma=0" etc */ 1652 module_param(use_dma, bool, 0); 1653 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1654 1655 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1656 { 1657 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1658 1659 /* called with controller lock already held */ 1660 1661 if (!epnum) { 1662 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1663 if (!is_cppi_enabled()) { 1664 /* endpoint 0 */ 1665 if (devctl & MUSB_DEVCTL_HM) 1666 musb_h_ep0_irq(musb); 1667 else 1668 musb_g_ep0_irq(musb); 1669 } 1670 #endif 1671 } else { 1672 /* endpoints 1..15 */ 1673 if (transmit) { 1674 if (devctl & MUSB_DEVCTL_HM) { 1675 if (is_host_capable()) 1676 musb_host_tx(musb, epnum); 1677 } else { 1678 if (is_peripheral_capable()) 1679 musb_g_tx(musb, epnum); 1680 } 1681 } else { 1682 /* receive */ 1683 if (devctl & MUSB_DEVCTL_HM) { 1684 if (is_host_capable()) 1685 musb_host_rx(musb, epnum); 1686 } else { 1687 if (is_peripheral_capable()) 1688 musb_g_rx(musb, epnum); 1689 } 1690 } 1691 } 1692 } 1693 EXPORT_SYMBOL_GPL(musb_dma_completion); 1694 1695 #else 1696 #define use_dma 0 1697 #endif 1698 1699 /*-------------------------------------------------------------------------*/ 1700 1701 #ifdef CONFIG_SYSFS 1702 1703 static ssize_t 1704 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1705 { 1706 struct musb *musb = dev_to_musb(dev); 1707 unsigned long flags; 1708 int ret = -EINVAL; 1709 1710 spin_lock_irqsave(&musb->lock, flags); 1711 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1712 spin_unlock_irqrestore(&musb->lock, flags); 1713 1714 return ret; 1715 } 1716 1717 static ssize_t 1718 musb_mode_store(struct device *dev, struct device_attribute *attr, 1719 const char *buf, size_t n) 1720 { 1721 struct musb *musb = dev_to_musb(dev); 1722 unsigned long flags; 1723 int status; 1724 1725 spin_lock_irqsave(&musb->lock, flags); 1726 if (sysfs_streq(buf, "host")) 1727 status = musb_platform_set_mode(musb, MUSB_HOST); 1728 else if (sysfs_streq(buf, "peripheral")) 1729 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1730 else if (sysfs_streq(buf, "otg")) 1731 status = musb_platform_set_mode(musb, MUSB_OTG); 1732 else 1733 status = -EINVAL; 1734 spin_unlock_irqrestore(&musb->lock, flags); 1735 1736 return (status == 0) ? n : status; 1737 } 1738 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1739 1740 static ssize_t 1741 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1742 const char *buf, size_t n) 1743 { 1744 struct musb *musb = dev_to_musb(dev); 1745 unsigned long flags; 1746 unsigned long val; 1747 1748 if (sscanf(buf, "%lu", &val) < 1) { 1749 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1750 return -EINVAL; 1751 } 1752 1753 spin_lock_irqsave(&musb->lock, flags); 1754 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1755 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1756 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1757 musb->is_active = 0; 1758 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1759 spin_unlock_irqrestore(&musb->lock, flags); 1760 1761 return n; 1762 } 1763 1764 static ssize_t 1765 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1766 { 1767 struct musb *musb = dev_to_musb(dev); 1768 unsigned long flags; 1769 unsigned long val; 1770 int vbus; 1771 1772 spin_lock_irqsave(&musb->lock, flags); 1773 val = musb->a_wait_bcon; 1774 /* FIXME get_vbus_status() is normally #defined as false... 1775 * and is effectively TUSB-specific. 1776 */ 1777 vbus = musb_platform_get_vbus_status(musb); 1778 spin_unlock_irqrestore(&musb->lock, flags); 1779 1780 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1781 vbus ? "on" : "off", val); 1782 } 1783 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1784 1785 /* Gadget drivers can't know that a host is connected so they might want 1786 * to start SRP, but users can. This allows userspace to trigger SRP. 1787 */ 1788 static ssize_t 1789 musb_srp_store(struct device *dev, struct device_attribute *attr, 1790 const char *buf, size_t n) 1791 { 1792 struct musb *musb = dev_to_musb(dev); 1793 unsigned short srp; 1794 1795 if (sscanf(buf, "%hu", &srp) != 1 1796 || (srp != 1)) { 1797 dev_err(dev, "SRP: Value must be 1\n"); 1798 return -EINVAL; 1799 } 1800 1801 if (srp == 1) 1802 musb_g_wakeup(musb); 1803 1804 return n; 1805 } 1806 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1807 1808 static struct attribute *musb_attributes[] = { 1809 &dev_attr_mode.attr, 1810 &dev_attr_vbus.attr, 1811 &dev_attr_srp.attr, 1812 NULL 1813 }; 1814 1815 static const struct attribute_group musb_attr_group = { 1816 .attrs = musb_attributes, 1817 }; 1818 1819 #endif /* sysfs */ 1820 1821 #ifndef __UBOOT__ 1822 /* Only used to provide driver mode change events */ 1823 static void musb_irq_work(struct work_struct *data) 1824 { 1825 struct musb *musb = container_of(data, struct musb, irq_work); 1826 static int old_state; 1827 1828 if (musb->xceiv->state != old_state) { 1829 old_state = musb->xceiv->state; 1830 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1831 } 1832 } 1833 #endif 1834 1835 /* -------------------------------------------------------------------------- 1836 * Init support 1837 */ 1838 1839 static struct musb *__devinit 1840 allocate_instance(struct device *dev, 1841 struct musb_hdrc_config *config, void __iomem *mbase) 1842 { 1843 struct musb *musb; 1844 struct musb_hw_ep *ep; 1845 int epnum; 1846 #ifndef __UBOOT__ 1847 struct usb_hcd *hcd; 1848 1849 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1850 if (!hcd) 1851 return NULL; 1852 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1853 1854 musb = hcd_to_musb(hcd); 1855 #else 1856 musb = calloc(1, sizeof(*musb)); 1857 if (!musb) 1858 return NULL; 1859 #endif 1860 INIT_LIST_HEAD(&musb->control); 1861 INIT_LIST_HEAD(&musb->in_bulk); 1862 INIT_LIST_HEAD(&musb->out_bulk); 1863 1864 #ifndef __UBOOT__ 1865 hcd->uses_new_polling = 1; 1866 hcd->has_tt = 1; 1867 #endif 1868 1869 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1870 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1871 dev_set_drvdata(dev, musb); 1872 musb->mregs = mbase; 1873 musb->ctrl_base = mbase; 1874 musb->nIrq = -ENODEV; 1875 musb->config = config; 1876 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1877 for (epnum = 0, ep = musb->endpoints; 1878 epnum < musb->config->num_eps; 1879 epnum++, ep++) { 1880 ep->musb = musb; 1881 ep->epnum = epnum; 1882 } 1883 1884 musb->controller = dev; 1885 1886 return musb; 1887 } 1888 1889 static void musb_free(struct musb *musb) 1890 { 1891 /* this has multiple entry modes. it handles fault cleanup after 1892 * probe(), where things may be partially set up, as well as rmmod 1893 * cleanup after everything's been de-activated. 1894 */ 1895 1896 #ifdef CONFIG_SYSFS 1897 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1898 #endif 1899 1900 if (musb->nIrq >= 0) { 1901 if (musb->irq_wake) 1902 disable_irq_wake(musb->nIrq); 1903 free_irq(musb->nIrq, musb); 1904 } 1905 if (is_dma_capable() && musb->dma_controller) { 1906 struct dma_controller *c = musb->dma_controller; 1907 1908 (void) c->stop(c); 1909 dma_controller_destroy(c); 1910 } 1911 1912 kfree(musb); 1913 } 1914 1915 /* 1916 * Perform generic per-controller initialization. 1917 * 1918 * @pDevice: the controller (already clocked, etc) 1919 * @nIrq: irq 1920 * @mregs: virtual address of controller registers, 1921 * not yet corrected for platform-specific offsets 1922 */ 1923 #ifndef __UBOOT__ 1924 static int __devinit 1925 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1926 #else 1927 struct musb * 1928 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, 1929 void *ctrl) 1930 #endif 1931 { 1932 int status; 1933 struct musb *musb; 1934 #ifndef __UBOOT__ 1935 struct musb_hdrc_platform_data *plat = dev->platform_data; 1936 #else 1937 int nIrq = 0; 1938 #endif 1939 1940 /* The driver might handle more features than the board; OK. 1941 * Fail when the board needs a feature that's not enabled. 1942 */ 1943 if (!plat) { 1944 dev_dbg(dev, "no platform_data?\n"); 1945 status = -ENODEV; 1946 goto fail0; 1947 } 1948 1949 /* allocate */ 1950 musb = allocate_instance(dev, plat->config, ctrl); 1951 if (!musb) { 1952 status = -ENOMEM; 1953 goto fail0; 1954 } 1955 1956 pm_runtime_use_autosuspend(musb->controller); 1957 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1958 pm_runtime_enable(musb->controller); 1959 1960 spin_lock_init(&musb->lock); 1961 musb->board_mode = plat->mode; 1962 musb->board_set_power = plat->set_power; 1963 musb->min_power = plat->min_power; 1964 musb->ops = plat->platform_ops; 1965 1966 /* The musb_platform_init() call: 1967 * - adjusts musb->mregs and musb->isr if needed, 1968 * - may initialize an integrated tranceiver 1969 * - initializes musb->xceiv, usually by otg_get_phy() 1970 * - stops powering VBUS 1971 * 1972 * There are various transceiver configurations. Blackfin, 1973 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1974 * external/discrete ones in various flavors (twl4030 family, 1975 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1976 */ 1977 musb->isr = generic_interrupt; 1978 status = musb_platform_init(musb); 1979 if (status < 0) 1980 goto fail1; 1981 1982 if (!musb->isr) { 1983 status = -ENODEV; 1984 goto fail2; 1985 } 1986 1987 #ifndef __UBOOT__ 1988 if (!musb->xceiv->io_ops) { 1989 musb->xceiv->io_dev = musb->controller; 1990 musb->xceiv->io_priv = musb->mregs; 1991 musb->xceiv->io_ops = &musb_ulpi_access; 1992 } 1993 #endif 1994 1995 pm_runtime_get_sync(musb->controller); 1996 1997 #ifndef CONFIG_MUSB_PIO_ONLY 1998 if (use_dma && dev->dma_mask) { 1999 struct dma_controller *c; 2000 2001 c = dma_controller_create(musb, musb->mregs); 2002 musb->dma_controller = c; 2003 if (c) 2004 (void) c->start(c); 2005 } 2006 #endif 2007 #ifndef __UBOOT__ 2008 /* ideally this would be abstracted in platform setup */ 2009 if (!is_dma_capable() || !musb->dma_controller) 2010 dev->dma_mask = NULL; 2011 #endif 2012 2013 /* be sure interrupts are disabled before connecting ISR */ 2014 musb_platform_disable(musb); 2015 musb_generic_disable(musb); 2016 2017 /* setup musb parts of the core (especially endpoints) */ 2018 status = musb_core_init(plat->config->multipoint 2019 ? MUSB_CONTROLLER_MHDRC 2020 : MUSB_CONTROLLER_HDRC, musb); 2021 if (status < 0) 2022 goto fail3; 2023 2024 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2025 2026 /* Init IRQ workqueue before request_irq */ 2027 INIT_WORK(&musb->irq_work, musb_irq_work); 2028 2029 /* attach to the IRQ */ 2030 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2031 dev_err(dev, "request_irq %d failed!\n", nIrq); 2032 status = -ENODEV; 2033 goto fail3; 2034 } 2035 musb->nIrq = nIrq; 2036 /* FIXME this handles wakeup irqs wrong */ 2037 if (enable_irq_wake(nIrq) == 0) { 2038 musb->irq_wake = 1; 2039 device_init_wakeup(dev, 1); 2040 } else { 2041 musb->irq_wake = 0; 2042 } 2043 2044 #ifndef __UBOOT__ 2045 /* host side needs more setup */ 2046 if (is_host_enabled(musb)) { 2047 struct usb_hcd *hcd = musb_to_hcd(musb); 2048 2049 otg_set_host(musb->xceiv->otg, &hcd->self); 2050 2051 if (is_otg_enabled(musb)) 2052 hcd->self.otg_port = 1; 2053 musb->xceiv->otg->host = &hcd->self; 2054 hcd->power_budget = 2 * (plat->power ? : 250); 2055 2056 /* program PHY to use external vBus if required */ 2057 if (plat->extvbus) { 2058 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2059 busctl |= MUSB_ULPI_USE_EXTVBUS; 2060 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2061 } 2062 } 2063 #endif 2064 2065 /* For the host-only role, we can activate right away. 2066 * (We expect the ID pin to be forcibly grounded!!) 2067 * Otherwise, wait till the gadget driver hooks up. 2068 */ 2069 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2070 struct usb_hcd *hcd = musb_to_hcd(musb); 2071 2072 MUSB_HST_MODE(musb); 2073 #ifndef __UBOOT__ 2074 musb->xceiv->otg->default_a = 1; 2075 musb->xceiv->state = OTG_STATE_A_IDLE; 2076 2077 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2078 2079 hcd->self.uses_pio_for_control = 1; 2080 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2081 "HOST", status, 2082 musb_readb(musb->mregs, MUSB_DEVCTL), 2083 (musb_readb(musb->mregs, MUSB_DEVCTL) 2084 & MUSB_DEVCTL_BDEVICE 2085 ? 'B' : 'A')); 2086 #endif 2087 2088 } else /* peripheral is enabled */ { 2089 MUSB_DEV_MODE(musb); 2090 #ifndef __UBOOT__ 2091 musb->xceiv->otg->default_a = 0; 2092 musb->xceiv->state = OTG_STATE_B_IDLE; 2093 #endif 2094 2095 if (is_peripheral_capable()) 2096 status = musb_gadget_setup(musb); 2097 2098 #ifndef __UBOOT__ 2099 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2100 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2101 status, 2102 musb_readb(musb->mregs, MUSB_DEVCTL)); 2103 #endif 2104 2105 } 2106 if (status < 0) 2107 goto fail3; 2108 2109 status = musb_init_debugfs(musb); 2110 if (status < 0) 2111 goto fail4; 2112 2113 #ifdef CONFIG_SYSFS 2114 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2115 if (status) 2116 goto fail5; 2117 #endif 2118 2119 pm_runtime_put(musb->controller); 2120 2121 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", 2122 ({char *s; 2123 switch (musb->board_mode) { 2124 case MUSB_HOST: s = "Host"; break; 2125 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2126 default: s = "OTG"; break; 2127 }; s; }), 2128 ctrl, 2129 (is_dma_capable() && musb->dma_controller) 2130 ? "DMA" : "PIO", 2131 musb->nIrq); 2132 2133 #ifndef __UBOOT__ 2134 return 0; 2135 #else 2136 return status == 0 ? musb : NULL; 2137 #endif 2138 2139 fail5: 2140 musb_exit_debugfs(musb); 2141 2142 fail4: 2143 #ifndef __UBOOT__ 2144 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2145 usb_remove_hcd(musb_to_hcd(musb)); 2146 else 2147 #endif 2148 musb_gadget_cleanup(musb); 2149 2150 fail3: 2151 pm_runtime_put_sync(musb->controller); 2152 2153 fail2: 2154 if (musb->irq_wake) 2155 device_init_wakeup(dev, 0); 2156 musb_platform_exit(musb); 2157 2158 fail1: 2159 dev_err(musb->controller, 2160 "musb_init_controller failed with status %d\n", status); 2161 2162 musb_free(musb); 2163 2164 fail0: 2165 2166 #ifndef __UBOOT__ 2167 return status; 2168 #else 2169 return status == 0 ? musb : NULL; 2170 #endif 2171 2172 } 2173 2174 /*-------------------------------------------------------------------------*/ 2175 2176 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2177 * bridge to a platform device; this driver then suffices. 2178 */ 2179 2180 #ifndef CONFIG_MUSB_PIO_ONLY 2181 static u64 *orig_dma_mask; 2182 #endif 2183 2184 #ifndef __UBOOT__ 2185 static int __devinit musb_probe(struct platform_device *pdev) 2186 { 2187 struct device *dev = &pdev->dev; 2188 int irq = platform_get_irq_byname(pdev, "mc"); 2189 int status; 2190 struct resource *iomem; 2191 void __iomem *base; 2192 2193 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2194 if (!iomem || irq <= 0) 2195 return -ENODEV; 2196 2197 base = ioremap(iomem->start, resource_size(iomem)); 2198 if (!base) { 2199 dev_err(dev, "ioremap failed\n"); 2200 return -ENOMEM; 2201 } 2202 2203 #ifndef CONFIG_MUSB_PIO_ONLY 2204 /* clobbered by use_dma=n */ 2205 orig_dma_mask = dev->dma_mask; 2206 #endif 2207 status = musb_init_controller(dev, irq, base); 2208 if (status < 0) 2209 iounmap(base); 2210 2211 return status; 2212 } 2213 2214 static int __devexit musb_remove(struct platform_device *pdev) 2215 { 2216 struct musb *musb = dev_to_musb(&pdev->dev); 2217 void __iomem *ctrl_base = musb->ctrl_base; 2218 2219 /* this gets called on rmmod. 2220 * - Host mode: host may still be active 2221 * - Peripheral mode: peripheral is deactivated (or never-activated) 2222 * - OTG mode: both roles are deactivated (or never-activated) 2223 */ 2224 musb_exit_debugfs(musb); 2225 musb_shutdown(pdev); 2226 2227 musb_free(musb); 2228 iounmap(ctrl_base); 2229 device_init_wakeup(&pdev->dev, 0); 2230 #ifndef CONFIG_MUSB_PIO_ONLY 2231 pdev->dev.dma_mask = orig_dma_mask; 2232 #endif 2233 return 0; 2234 } 2235 2236 #ifdef CONFIG_PM 2237 2238 static void musb_save_context(struct musb *musb) 2239 { 2240 int i; 2241 void __iomem *musb_base = musb->mregs; 2242 void __iomem *epio; 2243 2244 if (is_host_enabled(musb)) { 2245 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2246 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2247 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2248 } 2249 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2250 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2251 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2252 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2253 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2254 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2255 2256 for (i = 0; i < musb->config->num_eps; ++i) { 2257 struct musb_hw_ep *hw_ep; 2258 2259 hw_ep = &musb->endpoints[i]; 2260 if (!hw_ep) 2261 continue; 2262 2263 epio = hw_ep->regs; 2264 if (!epio) 2265 continue; 2266 2267 musb_writeb(musb_base, MUSB_INDEX, i); 2268 musb->context.index_regs[i].txmaxp = 2269 musb_readw(epio, MUSB_TXMAXP); 2270 musb->context.index_regs[i].txcsr = 2271 musb_readw(epio, MUSB_TXCSR); 2272 musb->context.index_regs[i].rxmaxp = 2273 musb_readw(epio, MUSB_RXMAXP); 2274 musb->context.index_regs[i].rxcsr = 2275 musb_readw(epio, MUSB_RXCSR); 2276 2277 if (musb->dyn_fifo) { 2278 musb->context.index_regs[i].txfifoadd = 2279 musb_read_txfifoadd(musb_base); 2280 musb->context.index_regs[i].rxfifoadd = 2281 musb_read_rxfifoadd(musb_base); 2282 musb->context.index_regs[i].txfifosz = 2283 musb_read_txfifosz(musb_base); 2284 musb->context.index_regs[i].rxfifosz = 2285 musb_read_rxfifosz(musb_base); 2286 } 2287 if (is_host_enabled(musb)) { 2288 musb->context.index_regs[i].txtype = 2289 musb_readb(epio, MUSB_TXTYPE); 2290 musb->context.index_regs[i].txinterval = 2291 musb_readb(epio, MUSB_TXINTERVAL); 2292 musb->context.index_regs[i].rxtype = 2293 musb_readb(epio, MUSB_RXTYPE); 2294 musb->context.index_regs[i].rxinterval = 2295 musb_readb(epio, MUSB_RXINTERVAL); 2296 2297 musb->context.index_regs[i].txfunaddr = 2298 musb_read_txfunaddr(musb_base, i); 2299 musb->context.index_regs[i].txhubaddr = 2300 musb_read_txhubaddr(musb_base, i); 2301 musb->context.index_regs[i].txhubport = 2302 musb_read_txhubport(musb_base, i); 2303 2304 musb->context.index_regs[i].rxfunaddr = 2305 musb_read_rxfunaddr(musb_base, i); 2306 musb->context.index_regs[i].rxhubaddr = 2307 musb_read_rxhubaddr(musb_base, i); 2308 musb->context.index_regs[i].rxhubport = 2309 musb_read_rxhubport(musb_base, i); 2310 } 2311 } 2312 } 2313 2314 static void musb_restore_context(struct musb *musb) 2315 { 2316 int i; 2317 void __iomem *musb_base = musb->mregs; 2318 void __iomem *ep_target_regs; 2319 void __iomem *epio; 2320 2321 if (is_host_enabled(musb)) { 2322 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2323 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2324 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2325 } 2326 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2327 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2328 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2329 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2330 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2331 2332 for (i = 0; i < musb->config->num_eps; ++i) { 2333 struct musb_hw_ep *hw_ep; 2334 2335 hw_ep = &musb->endpoints[i]; 2336 if (!hw_ep) 2337 continue; 2338 2339 epio = hw_ep->regs; 2340 if (!epio) 2341 continue; 2342 2343 musb_writeb(musb_base, MUSB_INDEX, i); 2344 musb_writew(epio, MUSB_TXMAXP, 2345 musb->context.index_regs[i].txmaxp); 2346 musb_writew(epio, MUSB_TXCSR, 2347 musb->context.index_regs[i].txcsr); 2348 musb_writew(epio, MUSB_RXMAXP, 2349 musb->context.index_regs[i].rxmaxp); 2350 musb_writew(epio, MUSB_RXCSR, 2351 musb->context.index_regs[i].rxcsr); 2352 2353 if (musb->dyn_fifo) { 2354 musb_write_txfifosz(musb_base, 2355 musb->context.index_regs[i].txfifosz); 2356 musb_write_rxfifosz(musb_base, 2357 musb->context.index_regs[i].rxfifosz); 2358 musb_write_txfifoadd(musb_base, 2359 musb->context.index_regs[i].txfifoadd); 2360 musb_write_rxfifoadd(musb_base, 2361 musb->context.index_regs[i].rxfifoadd); 2362 } 2363 2364 if (is_host_enabled(musb)) { 2365 musb_writeb(epio, MUSB_TXTYPE, 2366 musb->context.index_regs[i].txtype); 2367 musb_writeb(epio, MUSB_TXINTERVAL, 2368 musb->context.index_regs[i].txinterval); 2369 musb_writeb(epio, MUSB_RXTYPE, 2370 musb->context.index_regs[i].rxtype); 2371 musb_writeb(epio, MUSB_RXINTERVAL, 2372 2373 musb->context.index_regs[i].rxinterval); 2374 musb_write_txfunaddr(musb_base, i, 2375 musb->context.index_regs[i].txfunaddr); 2376 musb_write_txhubaddr(musb_base, i, 2377 musb->context.index_regs[i].txhubaddr); 2378 musb_write_txhubport(musb_base, i, 2379 musb->context.index_regs[i].txhubport); 2380 2381 ep_target_regs = 2382 musb_read_target_reg_base(i, musb_base); 2383 2384 musb_write_rxfunaddr(ep_target_regs, 2385 musb->context.index_regs[i].rxfunaddr); 2386 musb_write_rxhubaddr(ep_target_regs, 2387 musb->context.index_regs[i].rxhubaddr); 2388 musb_write_rxhubport(ep_target_regs, 2389 musb->context.index_regs[i].rxhubport); 2390 } 2391 } 2392 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2393 } 2394 2395 static int musb_suspend(struct device *dev) 2396 { 2397 struct musb *musb = dev_to_musb(dev); 2398 unsigned long flags; 2399 2400 spin_lock_irqsave(&musb->lock, flags); 2401 2402 if (is_peripheral_active(musb)) { 2403 /* FIXME force disconnect unless we know USB will wake 2404 * the system up quickly enough to respond ... 2405 */ 2406 } else if (is_host_active(musb)) { 2407 /* we know all the children are suspended; sometimes 2408 * they will even be wakeup-enabled. 2409 */ 2410 } 2411 2412 spin_unlock_irqrestore(&musb->lock, flags); 2413 return 0; 2414 } 2415 2416 static int musb_resume_noirq(struct device *dev) 2417 { 2418 /* for static cmos like DaVinci, register values were preserved 2419 * unless for some reason the whole soc powered down or the USB 2420 * module got reset through the PSC (vs just being disabled). 2421 */ 2422 return 0; 2423 } 2424 2425 static int musb_runtime_suspend(struct device *dev) 2426 { 2427 struct musb *musb = dev_to_musb(dev); 2428 2429 musb_save_context(musb); 2430 2431 return 0; 2432 } 2433 2434 static int musb_runtime_resume(struct device *dev) 2435 { 2436 struct musb *musb = dev_to_musb(dev); 2437 static int first = 1; 2438 2439 /* 2440 * When pm_runtime_get_sync called for the first time in driver 2441 * init, some of the structure is still not initialized which is 2442 * used in restore function. But clock needs to be 2443 * enabled before any register access, so 2444 * pm_runtime_get_sync has to be called. 2445 * Also context restore without save does not make 2446 * any sense 2447 */ 2448 if (!first) 2449 musb_restore_context(musb); 2450 first = 0; 2451 2452 return 0; 2453 } 2454 2455 static const struct dev_pm_ops musb_dev_pm_ops = { 2456 .suspend = musb_suspend, 2457 .resume_noirq = musb_resume_noirq, 2458 .runtime_suspend = musb_runtime_suspend, 2459 .runtime_resume = musb_runtime_resume, 2460 }; 2461 2462 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2463 #else 2464 #define MUSB_DEV_PM_OPS NULL 2465 #endif 2466 2467 static struct platform_driver musb_driver = { 2468 .driver = { 2469 .name = (char *)musb_driver_name, 2470 .bus = &platform_bus_type, 2471 .owner = THIS_MODULE, 2472 .pm = MUSB_DEV_PM_OPS, 2473 }, 2474 .probe = musb_probe, 2475 .remove = __devexit_p(musb_remove), 2476 .shutdown = musb_shutdown, 2477 }; 2478 2479 /*-------------------------------------------------------------------------*/ 2480 2481 static int __init musb_init(void) 2482 { 2483 if (usb_disabled()) 2484 return 0; 2485 2486 pr_info("%s: version " MUSB_VERSION ", " 2487 "?dma?" 2488 ", " 2489 "otg (peripheral+host)", 2490 musb_driver_name); 2491 return platform_driver_register(&musb_driver); 2492 } 2493 module_init(musb_init); 2494 2495 static void __exit musb_cleanup(void) 2496 { 2497 platform_driver_unregister(&musb_driver); 2498 } 2499 module_exit(musb_cleanup); 2500 #endif 2501