1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #ifndef __UBOOT__ 93 #include <linux/module.h> 94 #include <linux/kernel.h> 95 #include <linux/sched.h> 96 #include <linux/slab.h> 97 #include <linux/init.h> 98 #include <linux/list.h> 99 #include <linux/kobject.h> 100 #include <linux/prefetch.h> 101 #include <linux/platform_device.h> 102 #include <linux/io.h> 103 #else 104 #include <common.h> 105 #include <usb.h> 106 #include <asm/errno.h> 107 #include <linux/usb/ch9.h> 108 #include <linux/usb/gadget.h> 109 #include <linux/usb/musb.h> 110 #include <asm/io.h> 111 #include "linux-compat.h" 112 #include "usb-compat.h" 113 #endif 114 115 #include "musb_core.h" 116 117 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 118 119 120 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 121 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 122 123 #define MUSB_VERSION "6.0" 124 125 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 126 127 #define MUSB_DRIVER_NAME "musb-hdrc" 128 const char musb_driver_name[] = MUSB_DRIVER_NAME; 129 130 MODULE_DESCRIPTION(DRIVER_INFO); 131 MODULE_AUTHOR(DRIVER_AUTHOR); 132 MODULE_LICENSE("GPL"); 133 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 134 135 136 #ifndef __UBOOT__ 137 /*-------------------------------------------------------------------------*/ 138 139 static inline struct musb *dev_to_musb(struct device *dev) 140 { 141 return dev_get_drvdata(dev); 142 } 143 #endif 144 145 /*-------------------------------------------------------------------------*/ 146 147 #ifndef __UBOOT__ 148 #ifndef CONFIG_BLACKFIN 149 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 150 { 151 void __iomem *addr = phy->io_priv; 152 int i = 0; 153 u8 r; 154 u8 power; 155 int ret; 156 157 pm_runtime_get_sync(phy->io_dev); 158 159 /* Make sure the transceiver is not in low power mode */ 160 power = musb_readb(addr, MUSB_POWER); 161 power &= ~MUSB_POWER_SUSPENDM; 162 musb_writeb(addr, MUSB_POWER, power); 163 164 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 165 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 166 */ 167 168 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 170 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 171 172 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 173 & MUSB_ULPI_REG_CMPLT)) { 174 i++; 175 if (i == 10000) { 176 ret = -ETIMEDOUT; 177 goto out; 178 } 179 180 } 181 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 182 r &= ~MUSB_ULPI_REG_CMPLT; 183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 184 185 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 186 187 out: 188 pm_runtime_put(phy->io_dev); 189 190 return ret; 191 } 192 193 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 194 { 195 void __iomem *addr = phy->io_priv; 196 int i = 0; 197 u8 r = 0; 198 u8 power; 199 int ret = 0; 200 201 pm_runtime_get_sync(phy->io_dev); 202 203 /* Make sure the transceiver is not in low power mode */ 204 power = musb_readb(addr, MUSB_POWER); 205 power &= ~MUSB_POWER_SUSPENDM; 206 musb_writeb(addr, MUSB_POWER, power); 207 208 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 209 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 211 212 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 213 & MUSB_ULPI_REG_CMPLT)) { 214 i++; 215 if (i == 10000) { 216 ret = -ETIMEDOUT; 217 goto out; 218 } 219 } 220 221 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 222 r &= ~MUSB_ULPI_REG_CMPLT; 223 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 224 225 out: 226 pm_runtime_put(phy->io_dev); 227 228 return ret; 229 } 230 #else 231 #define musb_ulpi_read NULL 232 #define musb_ulpi_write NULL 233 #endif 234 235 static struct usb_phy_io_ops musb_ulpi_access = { 236 .read = musb_ulpi_read, 237 .write = musb_ulpi_write, 238 }; 239 #endif 240 241 /*-------------------------------------------------------------------------*/ 242 243 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 244 245 /* 246 * Load an endpoint's FIFO 247 */ 248 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 249 { 250 struct musb *musb = hw_ep->musb; 251 void __iomem *fifo = hw_ep->fifo; 252 253 prefetch((u8 *)src); 254 255 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 256 'T', hw_ep->epnum, fifo, len, src); 257 258 /* we can't assume unaligned reads work */ 259 if (likely((0x01 & (unsigned long) src) == 0)) { 260 u16 index = 0; 261 262 /* best case is 32bit-aligned source address */ 263 if ((0x02 & (unsigned long) src) == 0) { 264 if (len >= 4) { 265 writesl(fifo, src + index, len >> 2); 266 index += len & ~0x03; 267 } 268 if (len & 0x02) { 269 musb_writew(fifo, 0, *(u16 *)&src[index]); 270 index += 2; 271 } 272 } else { 273 if (len >= 2) { 274 writesw(fifo, src + index, len >> 1); 275 index += len & ~0x01; 276 } 277 } 278 if (len & 0x01) 279 musb_writeb(fifo, 0, src[index]); 280 } else { 281 /* byte aligned */ 282 writesb(fifo, src, len); 283 } 284 } 285 286 #if !defined(CONFIG_USB_MUSB_AM35X) 287 /* 288 * Unload an endpoint's FIFO 289 */ 290 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 291 { 292 struct musb *musb = hw_ep->musb; 293 void __iomem *fifo = hw_ep->fifo; 294 295 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 296 'R', hw_ep->epnum, fifo, len, dst); 297 298 /* we can't assume unaligned writes work */ 299 if (likely((0x01 & (unsigned long) dst) == 0)) { 300 u16 index = 0; 301 302 /* best case is 32bit-aligned destination address */ 303 if ((0x02 & (unsigned long) dst) == 0) { 304 if (len >= 4) { 305 readsl(fifo, dst, len >> 2); 306 index = len & ~0x03; 307 } 308 if (len & 0x02) { 309 *(u16 *)&dst[index] = musb_readw(fifo, 0); 310 index += 2; 311 } 312 } else { 313 if (len >= 2) { 314 readsw(fifo, dst, len >> 1); 315 index = len & ~0x01; 316 } 317 } 318 if (len & 0x01) 319 dst[index] = musb_readb(fifo, 0); 320 } else { 321 /* byte aligned */ 322 readsb(fifo, dst, len); 323 } 324 } 325 #endif 326 327 #endif /* normal PIO */ 328 329 330 /*-------------------------------------------------------------------------*/ 331 332 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 333 static const u8 musb_test_packet[53] = { 334 /* implicit SYNC then DATA0 to start */ 335 336 /* JKJKJKJK x9 */ 337 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 338 /* JJKKJJKK x8 */ 339 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 340 /* JJJJKKKK x8 */ 341 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 342 /* JJJJJJJKKKKKKK x8 */ 343 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 344 /* JJJJJJJK x8 */ 345 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 346 /* JKKKKKKK x10, JK */ 347 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 348 349 /* implicit CRC16 then EOP to end */ 350 }; 351 352 void musb_load_testpacket(struct musb *musb) 353 { 354 void __iomem *regs = musb->endpoints[0].regs; 355 356 musb_ep_select(musb->mregs, 0); 357 musb_write_fifo(musb->control_ep, 358 sizeof(musb_test_packet), musb_test_packet); 359 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 360 } 361 362 #ifndef __UBOOT__ 363 /*-------------------------------------------------------------------------*/ 364 365 /* 366 * Handles OTG hnp timeouts, such as b_ase0_brst 367 */ 368 void musb_otg_timer_func(unsigned long data) 369 { 370 struct musb *musb = (struct musb *)data; 371 unsigned long flags; 372 373 spin_lock_irqsave(&musb->lock, flags); 374 switch (musb->xceiv->state) { 375 case OTG_STATE_B_WAIT_ACON: 376 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 377 musb_g_disconnect(musb); 378 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 379 musb->is_active = 0; 380 break; 381 case OTG_STATE_A_SUSPEND: 382 case OTG_STATE_A_WAIT_BCON: 383 dev_dbg(musb->controller, "HNP: %s timeout\n", 384 otg_state_string(musb->xceiv->state)); 385 musb_platform_set_vbus(musb, 0); 386 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 387 break; 388 default: 389 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 390 otg_state_string(musb->xceiv->state)); 391 } 392 musb->ignore_disconnect = 0; 393 spin_unlock_irqrestore(&musb->lock, flags); 394 } 395 396 /* 397 * Stops the HNP transition. Caller must take care of locking. 398 */ 399 void musb_hnp_stop(struct musb *musb) 400 { 401 struct usb_hcd *hcd = musb_to_hcd(musb); 402 void __iomem *mbase = musb->mregs; 403 u8 reg; 404 405 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 406 407 switch (musb->xceiv->state) { 408 case OTG_STATE_A_PERIPHERAL: 409 musb_g_disconnect(musb); 410 dev_dbg(musb->controller, "HNP: back to %s\n", 411 otg_state_string(musb->xceiv->state)); 412 break; 413 case OTG_STATE_B_HOST: 414 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 415 hcd->self.is_b_host = 0; 416 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 417 MUSB_DEV_MODE(musb); 418 reg = musb_readb(mbase, MUSB_POWER); 419 reg |= MUSB_POWER_SUSPENDM; 420 musb_writeb(mbase, MUSB_POWER, reg); 421 /* REVISIT: Start SESSION_REQUEST here? */ 422 break; 423 default: 424 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 425 otg_state_string(musb->xceiv->state)); 426 } 427 428 /* 429 * When returning to A state after HNP, avoid hub_port_rebounce(), 430 * which cause occasional OPT A "Did not receive reset after connect" 431 * errors. 432 */ 433 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 434 } 435 #endif 436 437 /* 438 * Interrupt Service Routine to record USB "global" interrupts. 439 * Since these do not happen often and signify things of 440 * paramount importance, it seems OK to check them individually; 441 * the order of the tests is specified in the manual 442 * 443 * @param musb instance pointer 444 * @param int_usb register contents 445 * @param devctl 446 * @param power 447 */ 448 449 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 450 u8 devctl, u8 power) 451 { 452 #ifndef __UBOOT__ 453 struct usb_otg *otg = musb->xceiv->otg; 454 #endif 455 irqreturn_t handled = IRQ_NONE; 456 457 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 458 int_usb); 459 460 #ifndef __UBOOT__ 461 /* in host mode, the peripheral may issue remote wakeup. 462 * in peripheral mode, the host may resume the link. 463 * spurious RESUME irqs happen too, paired with SUSPEND. 464 */ 465 if (int_usb & MUSB_INTR_RESUME) { 466 handled = IRQ_HANDLED; 467 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 468 469 if (devctl & MUSB_DEVCTL_HM) { 470 void __iomem *mbase = musb->mregs; 471 472 switch (musb->xceiv->state) { 473 case OTG_STATE_A_SUSPEND: 474 /* remote wakeup? later, GetPortStatus 475 * will stop RESUME signaling 476 */ 477 478 if (power & MUSB_POWER_SUSPENDM) { 479 /* spurious */ 480 musb->int_usb &= ~MUSB_INTR_SUSPEND; 481 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 482 break; 483 } 484 485 power &= ~MUSB_POWER_SUSPENDM; 486 musb_writeb(mbase, MUSB_POWER, 487 power | MUSB_POWER_RESUME); 488 489 musb->port1_status |= 490 (USB_PORT_STAT_C_SUSPEND << 16) 491 | MUSB_PORT_STAT_RESUME; 492 musb->rh_timer = jiffies 493 + msecs_to_jiffies(20); 494 495 musb->xceiv->state = OTG_STATE_A_HOST; 496 musb->is_active = 1; 497 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 498 break; 499 case OTG_STATE_B_WAIT_ACON: 500 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 501 musb->is_active = 1; 502 MUSB_DEV_MODE(musb); 503 break; 504 default: 505 WARNING("bogus %s RESUME (%s)\n", 506 "host", 507 otg_state_string(musb->xceiv->state)); 508 } 509 } else { 510 switch (musb->xceiv->state) { 511 case OTG_STATE_A_SUSPEND: 512 /* possibly DISCONNECT is upcoming */ 513 musb->xceiv->state = OTG_STATE_A_HOST; 514 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 515 break; 516 case OTG_STATE_B_WAIT_ACON: 517 case OTG_STATE_B_PERIPHERAL: 518 /* disconnect while suspended? we may 519 * not get a disconnect irq... 520 */ 521 if ((devctl & MUSB_DEVCTL_VBUS) 522 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 523 ) { 524 musb->int_usb |= MUSB_INTR_DISCONNECT; 525 musb->int_usb &= ~MUSB_INTR_SUSPEND; 526 break; 527 } 528 musb_g_resume(musb); 529 break; 530 case OTG_STATE_B_IDLE: 531 musb->int_usb &= ~MUSB_INTR_SUSPEND; 532 break; 533 default: 534 WARNING("bogus %s RESUME (%s)\n", 535 "peripheral", 536 otg_state_string(musb->xceiv->state)); 537 } 538 } 539 } 540 541 /* see manual for the order of the tests */ 542 if (int_usb & MUSB_INTR_SESSREQ) { 543 void __iomem *mbase = musb->mregs; 544 545 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 546 && (devctl & MUSB_DEVCTL_BDEVICE)) { 547 dev_dbg(musb->controller, "SessReq while on B state\n"); 548 return IRQ_HANDLED; 549 } 550 551 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 552 otg_state_string(musb->xceiv->state)); 553 554 /* IRQ arrives from ID pin sense or (later, if VBUS power 555 * is removed) SRP. responses are time critical: 556 * - turn on VBUS (with silicon-specific mechanism) 557 * - go through A_WAIT_VRISE 558 * - ... to A_WAIT_BCON. 559 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 560 */ 561 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 562 musb->ep0_stage = MUSB_EP0_START; 563 musb->xceiv->state = OTG_STATE_A_IDLE; 564 MUSB_HST_MODE(musb); 565 musb_platform_set_vbus(musb, 1); 566 567 handled = IRQ_HANDLED; 568 } 569 570 if (int_usb & MUSB_INTR_VBUSERROR) { 571 int ignore = 0; 572 573 /* During connection as an A-Device, we may see a short 574 * current spikes causing voltage drop, because of cable 575 * and peripheral capacitance combined with vbus draw. 576 * (So: less common with truly self-powered devices, where 577 * vbus doesn't act like a power supply.) 578 * 579 * Such spikes are short; usually less than ~500 usec, max 580 * of ~2 msec. That is, they're not sustained overcurrent 581 * errors, though they're reported using VBUSERROR irqs. 582 * 583 * Workarounds: (a) hardware: use self powered devices. 584 * (b) software: ignore non-repeated VBUS errors. 585 * 586 * REVISIT: do delays from lots of DEBUG_KERNEL checks 587 * make trouble here, keeping VBUS < 4.4V ? 588 */ 589 switch (musb->xceiv->state) { 590 case OTG_STATE_A_HOST: 591 /* recovery is dicey once we've gotten past the 592 * initial stages of enumeration, but if VBUS 593 * stayed ok at the other end of the link, and 594 * another reset is due (at least for high speed, 595 * to redo the chirp etc), it might work OK... 596 */ 597 case OTG_STATE_A_WAIT_BCON: 598 case OTG_STATE_A_WAIT_VRISE: 599 if (musb->vbuserr_retry) { 600 void __iomem *mbase = musb->mregs; 601 602 musb->vbuserr_retry--; 603 ignore = 1; 604 devctl |= MUSB_DEVCTL_SESSION; 605 musb_writeb(mbase, MUSB_DEVCTL, devctl); 606 } else { 607 musb->port1_status |= 608 USB_PORT_STAT_OVERCURRENT 609 | (USB_PORT_STAT_C_OVERCURRENT << 16); 610 } 611 break; 612 default: 613 break; 614 } 615 616 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 617 otg_state_string(musb->xceiv->state), 618 devctl, 619 ({ char *s; 620 switch (devctl & MUSB_DEVCTL_VBUS) { 621 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 622 s = "<SessEnd"; break; 623 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 624 s = "<AValid"; break; 625 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 626 s = "<VBusValid"; break; 627 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 628 default: 629 s = "VALID"; break; 630 }; s; }), 631 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 632 musb->port1_status); 633 634 /* go through A_WAIT_VFALL then start a new session */ 635 if (!ignore) 636 musb_platform_set_vbus(musb, 0); 637 handled = IRQ_HANDLED; 638 } 639 640 if (int_usb & MUSB_INTR_SUSPEND) { 641 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 642 otg_state_string(musb->xceiv->state), devctl, power); 643 handled = IRQ_HANDLED; 644 645 switch (musb->xceiv->state) { 646 case OTG_STATE_A_PERIPHERAL: 647 /* We also come here if the cable is removed, since 648 * this silicon doesn't report ID-no-longer-grounded. 649 * 650 * We depend on T(a_wait_bcon) to shut us down, and 651 * hope users don't do anything dicey during this 652 * undesired detour through A_WAIT_BCON. 653 */ 654 musb_hnp_stop(musb); 655 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 656 musb_root_disconnect(musb); 657 musb_platform_try_idle(musb, jiffies 658 + msecs_to_jiffies(musb->a_wait_bcon 659 ? : OTG_TIME_A_WAIT_BCON)); 660 661 break; 662 case OTG_STATE_B_IDLE: 663 if (!musb->is_active) 664 break; 665 case OTG_STATE_B_PERIPHERAL: 666 musb_g_suspend(musb); 667 musb->is_active = is_otg_enabled(musb) 668 && otg->gadget->b_hnp_enable; 669 if (musb->is_active) { 670 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 671 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 672 mod_timer(&musb->otg_timer, jiffies 673 + msecs_to_jiffies( 674 OTG_TIME_B_ASE0_BRST)); 675 } 676 break; 677 case OTG_STATE_A_WAIT_BCON: 678 if (musb->a_wait_bcon != 0) 679 musb_platform_try_idle(musb, jiffies 680 + msecs_to_jiffies(musb->a_wait_bcon)); 681 break; 682 case OTG_STATE_A_HOST: 683 musb->xceiv->state = OTG_STATE_A_SUSPEND; 684 musb->is_active = is_otg_enabled(musb) 685 && otg->host->b_hnp_enable; 686 break; 687 case OTG_STATE_B_HOST: 688 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 689 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 690 break; 691 default: 692 /* "should not happen" */ 693 musb->is_active = 0; 694 break; 695 } 696 } 697 #endif 698 699 if (int_usb & MUSB_INTR_CONNECT) { 700 struct usb_hcd *hcd = musb_to_hcd(musb); 701 702 handled = IRQ_HANDLED; 703 musb->is_active = 1; 704 705 musb->ep0_stage = MUSB_EP0_START; 706 707 /* flush endpoints when transitioning from Device Mode */ 708 if (is_peripheral_active(musb)) { 709 /* REVISIT HNP; just force disconnect */ 710 } 711 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 712 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 713 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 714 #ifndef __UBOOT__ 715 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 716 |USB_PORT_STAT_HIGH_SPEED 717 |USB_PORT_STAT_ENABLE 718 ); 719 musb->port1_status |= USB_PORT_STAT_CONNECTION 720 |(USB_PORT_STAT_C_CONNECTION << 16); 721 722 /* high vs full speed is just a guess until after reset */ 723 if (devctl & MUSB_DEVCTL_LSDEV) 724 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 725 726 /* indicate new connection to OTG machine */ 727 switch (musb->xceiv->state) { 728 case OTG_STATE_B_PERIPHERAL: 729 if (int_usb & MUSB_INTR_SUSPEND) { 730 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 731 int_usb &= ~MUSB_INTR_SUSPEND; 732 goto b_host; 733 } else 734 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 735 break; 736 case OTG_STATE_B_WAIT_ACON: 737 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 738 b_host: 739 musb->xceiv->state = OTG_STATE_B_HOST; 740 hcd->self.is_b_host = 1; 741 musb->ignore_disconnect = 0; 742 del_timer(&musb->otg_timer); 743 break; 744 default: 745 if ((devctl & MUSB_DEVCTL_VBUS) 746 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 747 musb->xceiv->state = OTG_STATE_A_HOST; 748 hcd->self.is_b_host = 0; 749 } 750 break; 751 } 752 753 /* poke the root hub */ 754 MUSB_HST_MODE(musb); 755 if (hcd->status_urb) 756 usb_hcd_poll_rh_status(hcd); 757 else 758 usb_hcd_resume_root_hub(hcd); 759 760 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 761 otg_state_string(musb->xceiv->state), devctl); 762 #endif 763 } 764 765 #ifndef __UBOOT__ 766 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 767 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 768 otg_state_string(musb->xceiv->state), 769 MUSB_MODE(musb), devctl); 770 handled = IRQ_HANDLED; 771 772 switch (musb->xceiv->state) { 773 case OTG_STATE_A_HOST: 774 case OTG_STATE_A_SUSPEND: 775 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 776 musb_root_disconnect(musb); 777 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 778 musb_platform_try_idle(musb, jiffies 779 + msecs_to_jiffies(musb->a_wait_bcon)); 780 break; 781 case OTG_STATE_B_HOST: 782 /* REVISIT this behaves for "real disconnect" 783 * cases; make sure the other transitions from 784 * from B_HOST act right too. The B_HOST code 785 * in hnp_stop() is currently not used... 786 */ 787 musb_root_disconnect(musb); 788 musb_to_hcd(musb)->self.is_b_host = 0; 789 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 790 MUSB_DEV_MODE(musb); 791 musb_g_disconnect(musb); 792 break; 793 case OTG_STATE_A_PERIPHERAL: 794 musb_hnp_stop(musb); 795 musb_root_disconnect(musb); 796 /* FALLTHROUGH */ 797 case OTG_STATE_B_WAIT_ACON: 798 /* FALLTHROUGH */ 799 case OTG_STATE_B_PERIPHERAL: 800 case OTG_STATE_B_IDLE: 801 musb_g_disconnect(musb); 802 break; 803 default: 804 WARNING("unhandled DISCONNECT transition (%s)\n", 805 otg_state_string(musb->xceiv->state)); 806 break; 807 } 808 } 809 810 /* mentor saves a bit: bus reset and babble share the same irq. 811 * only host sees babble; only peripheral sees bus reset. 812 */ 813 if (int_usb & MUSB_INTR_RESET) { 814 handled = IRQ_HANDLED; 815 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 816 /* 817 * Looks like non-HS BABBLE can be ignored, but 818 * HS BABBLE is an error condition. For HS the solution 819 * is to avoid babble in the first place and fix what 820 * caused BABBLE. When HS BABBLE happens we can only 821 * stop the session. 822 */ 823 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 824 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 825 else { 826 ERR("Stopping host session -- babble\n"); 827 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 828 } 829 } else if (is_peripheral_capable()) { 830 dev_dbg(musb->controller, "BUS RESET as %s\n", 831 otg_state_string(musb->xceiv->state)); 832 switch (musb->xceiv->state) { 833 case OTG_STATE_A_SUSPEND: 834 /* We need to ignore disconnect on suspend 835 * otherwise tusb 2.0 won't reconnect after a 836 * power cycle, which breaks otg compliance. 837 */ 838 musb->ignore_disconnect = 1; 839 musb_g_reset(musb); 840 /* FALLTHROUGH */ 841 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 842 /* never use invalid T(a_wait_bcon) */ 843 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 844 otg_state_string(musb->xceiv->state), 845 TA_WAIT_BCON(musb)); 846 mod_timer(&musb->otg_timer, jiffies 847 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 848 break; 849 case OTG_STATE_A_PERIPHERAL: 850 musb->ignore_disconnect = 0; 851 del_timer(&musb->otg_timer); 852 musb_g_reset(musb); 853 break; 854 case OTG_STATE_B_WAIT_ACON: 855 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 856 otg_state_string(musb->xceiv->state)); 857 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 858 musb_g_reset(musb); 859 break; 860 case OTG_STATE_B_IDLE: 861 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 862 /* FALLTHROUGH */ 863 case OTG_STATE_B_PERIPHERAL: 864 musb_g_reset(musb); 865 break; 866 default: 867 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 868 otg_state_string(musb->xceiv->state)); 869 } 870 } 871 } 872 #endif 873 874 #if 0 875 /* REVISIT ... this would be for multiplexing periodic endpoints, or 876 * supporting transfer phasing to prevent exceeding ISO bandwidth 877 * limits of a given frame or microframe. 878 * 879 * It's not needed for peripheral side, which dedicates endpoints; 880 * though it _might_ use SOF irqs for other purposes. 881 * 882 * And it's not currently needed for host side, which also dedicates 883 * endpoints, relies on TX/RX interval registers, and isn't claimed 884 * to support ISO transfers yet. 885 */ 886 if (int_usb & MUSB_INTR_SOF) { 887 void __iomem *mbase = musb->mregs; 888 struct musb_hw_ep *ep; 889 u8 epnum; 890 u16 frame; 891 892 dev_dbg(musb->controller, "START_OF_FRAME\n"); 893 handled = IRQ_HANDLED; 894 895 /* start any periodic Tx transfers waiting for current frame */ 896 frame = musb_readw(mbase, MUSB_FRAME); 897 ep = musb->endpoints; 898 for (epnum = 1; (epnum < musb->nr_endpoints) 899 && (musb->epmask >= (1 << epnum)); 900 epnum++, ep++) { 901 /* 902 * FIXME handle framecounter wraps (12 bits) 903 * eliminate duplicated StartUrb logic 904 */ 905 if (ep->dwWaitFrame >= frame) { 906 ep->dwWaitFrame = 0; 907 pr_debug("SOF --> periodic TX%s on %d\n", 908 ep->tx_channel ? " DMA" : "", 909 epnum); 910 if (!ep->tx_channel) 911 musb_h_tx_start(musb, epnum); 912 else 913 cppi_hostdma_start(musb, epnum); 914 } 915 } /* end of for loop */ 916 } 917 #endif 918 919 schedule_work(&musb->irq_work); 920 921 return handled; 922 } 923 924 /*-------------------------------------------------------------------------*/ 925 926 /* 927 * Program the HDRC to start (enable interrupts, dma, etc.). 928 */ 929 #ifndef __UBOOT__ 930 void musb_start(struct musb *musb) 931 #else 932 int musb_start(struct musb *musb) 933 #endif 934 { 935 void __iomem *regs = musb->mregs; 936 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 937 #ifdef __UBOOT__ 938 int ret; 939 #endif 940 941 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 942 943 /* Set INT enable registers, enable interrupts */ 944 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 945 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 946 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 947 948 musb_writeb(regs, MUSB_TESTMODE, 0); 949 950 /* put into basic highspeed mode and start session */ 951 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 952 | MUSB_POWER_HSENAB 953 /* ENSUSPEND wedges tusb */ 954 /* | MUSB_POWER_ENSUSPEND */ 955 ); 956 957 musb->is_active = 0; 958 devctl = musb_readb(regs, MUSB_DEVCTL); 959 devctl &= ~MUSB_DEVCTL_SESSION; 960 961 if (is_otg_enabled(musb)) { 962 #ifndef __UBOOT__ 963 /* session started after: 964 * (a) ID-grounded irq, host mode; 965 * (b) vbus present/connect IRQ, peripheral mode; 966 * (c) peripheral initiates, using SRP 967 */ 968 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 969 musb->is_active = 1; 970 else 971 devctl |= MUSB_DEVCTL_SESSION; 972 #endif 973 974 } else if (is_host_enabled(musb)) { 975 /* assume ID pin is hard-wired to ground */ 976 devctl |= MUSB_DEVCTL_SESSION; 977 978 } else /* peripheral is enabled */ { 979 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 980 musb->is_active = 1; 981 } 982 983 #ifndef __UBOOT__ 984 musb_platform_enable(musb); 985 #else 986 ret = musb_platform_enable(musb); 987 if (ret) { 988 musb->is_active = 0; 989 return ret; 990 } 991 #endif 992 musb_writeb(regs, MUSB_DEVCTL, devctl); 993 994 #ifdef __UBOOT__ 995 return 0; 996 #endif 997 } 998 999 1000 static void musb_generic_disable(struct musb *musb) 1001 { 1002 void __iomem *mbase = musb->mregs; 1003 u16 temp; 1004 1005 /* disable interrupts */ 1006 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1007 musb_writew(mbase, MUSB_INTRTXE, 0); 1008 musb_writew(mbase, MUSB_INTRRXE, 0); 1009 1010 /* off */ 1011 musb_writeb(mbase, MUSB_DEVCTL, 0); 1012 1013 /* flush pending interrupts */ 1014 temp = musb_readb(mbase, MUSB_INTRUSB); 1015 temp = musb_readw(mbase, MUSB_INTRTX); 1016 temp = musb_readw(mbase, MUSB_INTRRX); 1017 1018 } 1019 1020 /* 1021 * Make the HDRC stop (disable interrupts, etc.); 1022 * reversible by musb_start 1023 * called on gadget driver unregister 1024 * with controller locked, irqs blocked 1025 * acts as a NOP unless some role activated the hardware 1026 */ 1027 void musb_stop(struct musb *musb) 1028 { 1029 /* stop IRQs, timers, ... */ 1030 musb_platform_disable(musb); 1031 musb_generic_disable(musb); 1032 dev_dbg(musb->controller, "HDRC disabled\n"); 1033 1034 /* FIXME 1035 * - mark host and/or peripheral drivers unusable/inactive 1036 * - disable DMA (and enable it in HdrcStart) 1037 * - make sure we can musb_start() after musb_stop(); with 1038 * OTG mode, gadget driver module rmmod/modprobe cycles that 1039 * - ... 1040 */ 1041 musb_platform_try_idle(musb, 0); 1042 } 1043 1044 #ifndef __UBOOT__ 1045 static void musb_shutdown(struct platform_device *pdev) 1046 { 1047 struct musb *musb = dev_to_musb(&pdev->dev); 1048 unsigned long flags; 1049 1050 pm_runtime_get_sync(musb->controller); 1051 1052 musb_gadget_cleanup(musb); 1053 1054 spin_lock_irqsave(&musb->lock, flags); 1055 musb_platform_disable(musb); 1056 musb_generic_disable(musb); 1057 spin_unlock_irqrestore(&musb->lock, flags); 1058 1059 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1060 usb_remove_hcd(musb_to_hcd(musb)); 1061 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1062 musb_platform_exit(musb); 1063 1064 pm_runtime_put(musb->controller); 1065 /* FIXME power down */ 1066 } 1067 #endif 1068 1069 1070 /*-------------------------------------------------------------------------*/ 1071 1072 /* 1073 * The silicon either has hard-wired endpoint configurations, or else 1074 * "dynamic fifo" sizing. The driver has support for both, though at this 1075 * writing only the dynamic sizing is very well tested. Since we switched 1076 * away from compile-time hardware parameters, we can no longer rely on 1077 * dead code elimination to leave only the relevant one in the object file. 1078 * 1079 * We don't currently use dynamic fifo setup capability to do anything 1080 * more than selecting one of a bunch of predefined configurations. 1081 */ 1082 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1083 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1084 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1085 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1086 || defined(CONFIG_USB_MUSB_AM35X) \ 1087 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1088 || defined(CONFIG_USB_MUSB_DSPS) \ 1089 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1090 static ushort __devinitdata fifo_mode = 4; 1091 #elif defined(CONFIG_USB_MUSB_UX500) \ 1092 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1093 static ushort __devinitdata fifo_mode = 5; 1094 #else 1095 static ushort __devinitdata fifo_mode = 2; 1096 #endif 1097 1098 /* "modprobe ... fifo_mode=1" etc */ 1099 module_param(fifo_mode, ushort, 0); 1100 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1101 1102 /* 1103 * tables defining fifo_mode values. define more if you like. 1104 * for host side, make sure both halves of ep1 are set up. 1105 */ 1106 1107 /* mode 0 - fits in 2KB */ 1108 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1109 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1110 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1111 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1112 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1113 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1114 }; 1115 1116 /* mode 1 - fits in 4KB */ 1117 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1118 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1119 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1120 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1121 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1122 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1123 }; 1124 1125 /* mode 2 - fits in 4KB */ 1126 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1127 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1128 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1129 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1130 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1131 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1132 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1133 }; 1134 1135 /* mode 3 - fits in 4KB */ 1136 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1137 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1138 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1139 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1140 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1141 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1142 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1143 }; 1144 1145 /* mode 4 - fits in 16KB */ 1146 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1147 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1148 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1149 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1150 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1151 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1152 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1153 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1154 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1155 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1156 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1157 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1158 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1159 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1160 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1161 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1162 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1163 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1164 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1165 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1166 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1167 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1168 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1169 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1170 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1171 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1172 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1173 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1174 }; 1175 1176 /* mode 5 - fits in 8KB */ 1177 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1178 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1179 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1180 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1181 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1182 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1183 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1184 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1185 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1186 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1187 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1188 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1189 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1190 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1191 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1192 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1193 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1194 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1195 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1196 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1197 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1198 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1199 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1200 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1201 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1202 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1203 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1204 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1205 }; 1206 1207 /* 1208 * configure a fifo; for non-shared endpoints, this may be called 1209 * once for a tx fifo and once for an rx fifo. 1210 * 1211 * returns negative errno or offset for next fifo. 1212 */ 1213 static int __devinit 1214 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1215 const struct musb_fifo_cfg *cfg, u16 offset) 1216 { 1217 void __iomem *mbase = musb->mregs; 1218 int size = 0; 1219 u16 maxpacket = cfg->maxpacket; 1220 u16 c_off = offset >> 3; 1221 u8 c_size; 1222 1223 /* expect hw_ep has already been zero-initialized */ 1224 1225 size = ffs(max(maxpacket, (u16) 8)) - 1; 1226 maxpacket = 1 << size; 1227 1228 c_size = size - 3; 1229 if (cfg->mode == BUF_DOUBLE) { 1230 if ((offset + (maxpacket << 1)) > 1231 (1 << (musb->config->ram_bits + 2))) 1232 return -EMSGSIZE; 1233 c_size |= MUSB_FIFOSZ_DPB; 1234 } else { 1235 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1236 return -EMSGSIZE; 1237 } 1238 1239 /* configure the FIFO */ 1240 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1241 1242 /* EP0 reserved endpoint for control, bidirectional; 1243 * EP1 reserved for bulk, two unidirection halves. 1244 */ 1245 if (hw_ep->epnum == 1) 1246 musb->bulk_ep = hw_ep; 1247 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1248 switch (cfg->style) { 1249 case FIFO_TX: 1250 musb_write_txfifosz(mbase, c_size); 1251 musb_write_txfifoadd(mbase, c_off); 1252 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1253 hw_ep->max_packet_sz_tx = maxpacket; 1254 break; 1255 case FIFO_RX: 1256 musb_write_rxfifosz(mbase, c_size); 1257 musb_write_rxfifoadd(mbase, c_off); 1258 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1259 hw_ep->max_packet_sz_rx = maxpacket; 1260 break; 1261 case FIFO_RXTX: 1262 musb_write_txfifosz(mbase, c_size); 1263 musb_write_txfifoadd(mbase, c_off); 1264 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1265 hw_ep->max_packet_sz_rx = maxpacket; 1266 1267 musb_write_rxfifosz(mbase, c_size); 1268 musb_write_rxfifoadd(mbase, c_off); 1269 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1270 hw_ep->max_packet_sz_tx = maxpacket; 1271 1272 hw_ep->is_shared_fifo = true; 1273 break; 1274 } 1275 1276 /* NOTE rx and tx endpoint irqs aren't managed separately, 1277 * which happens to be ok 1278 */ 1279 musb->epmask |= (1 << hw_ep->epnum); 1280 1281 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1282 } 1283 1284 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1285 .style = FIFO_RXTX, .maxpacket = 64, 1286 }; 1287 1288 static int __devinit ep_config_from_table(struct musb *musb) 1289 { 1290 const struct musb_fifo_cfg *cfg; 1291 unsigned i, n; 1292 int offset; 1293 struct musb_hw_ep *hw_ep = musb->endpoints; 1294 1295 if (musb->config->fifo_cfg) { 1296 cfg = musb->config->fifo_cfg; 1297 n = musb->config->fifo_cfg_size; 1298 goto done; 1299 } 1300 1301 switch (fifo_mode) { 1302 default: 1303 fifo_mode = 0; 1304 /* FALLTHROUGH */ 1305 case 0: 1306 cfg = mode_0_cfg; 1307 n = ARRAY_SIZE(mode_0_cfg); 1308 break; 1309 case 1: 1310 cfg = mode_1_cfg; 1311 n = ARRAY_SIZE(mode_1_cfg); 1312 break; 1313 case 2: 1314 cfg = mode_2_cfg; 1315 n = ARRAY_SIZE(mode_2_cfg); 1316 break; 1317 case 3: 1318 cfg = mode_3_cfg; 1319 n = ARRAY_SIZE(mode_3_cfg); 1320 break; 1321 case 4: 1322 cfg = mode_4_cfg; 1323 n = ARRAY_SIZE(mode_4_cfg); 1324 break; 1325 case 5: 1326 cfg = mode_5_cfg; 1327 n = ARRAY_SIZE(mode_5_cfg); 1328 break; 1329 } 1330 1331 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1332 1333 done: 1334 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1335 /* assert(offset > 0) */ 1336 1337 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1338 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1339 */ 1340 1341 for (i = 0; i < n; i++) { 1342 u8 epn = cfg->hw_ep_num; 1343 1344 if (epn >= musb->config->num_eps) { 1345 pr_debug("%s: invalid ep %d\n", 1346 musb_driver_name, epn); 1347 return -EINVAL; 1348 } 1349 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1350 if (offset < 0) { 1351 pr_debug("%s: mem overrun, ep %d\n", 1352 musb_driver_name, epn); 1353 return -EINVAL; 1354 } 1355 epn++; 1356 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1357 } 1358 1359 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, 1360 musb->config->num_eps * 2 - 1, offset, 1361 (1 << (musb->config->ram_bits + 2))); 1362 1363 if (!musb->bulk_ep) { 1364 pr_debug("%s: missing bulk\n", musb_driver_name); 1365 return -EINVAL; 1366 } 1367 1368 return 0; 1369 } 1370 1371 1372 /* 1373 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1374 * @param musb the controller 1375 */ 1376 static int __devinit ep_config_from_hw(struct musb *musb) 1377 { 1378 u8 epnum = 0; 1379 struct musb_hw_ep *hw_ep; 1380 void *mbase = musb->mregs; 1381 int ret = 0; 1382 1383 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1384 1385 /* FIXME pick up ep0 maxpacket size */ 1386 1387 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1388 musb_ep_select(mbase, epnum); 1389 hw_ep = musb->endpoints + epnum; 1390 1391 ret = musb_read_fifosize(musb, hw_ep, epnum); 1392 if (ret < 0) 1393 break; 1394 1395 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1396 1397 /* pick an RX/TX endpoint for bulk */ 1398 if (hw_ep->max_packet_sz_tx < 512 1399 || hw_ep->max_packet_sz_rx < 512) 1400 continue; 1401 1402 /* REVISIT: this algorithm is lazy, we should at least 1403 * try to pick a double buffered endpoint. 1404 */ 1405 if (musb->bulk_ep) 1406 continue; 1407 musb->bulk_ep = hw_ep; 1408 } 1409 1410 if (!musb->bulk_ep) { 1411 pr_debug("%s: missing bulk\n", musb_driver_name); 1412 return -EINVAL; 1413 } 1414 1415 return 0; 1416 } 1417 1418 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1419 1420 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1421 * configure endpoints, or take their config from silicon 1422 */ 1423 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1424 { 1425 u8 reg; 1426 char *type; 1427 char aInfo[90], aRevision[32], aDate[12]; 1428 void __iomem *mbase = musb->mregs; 1429 int status = 0; 1430 int i; 1431 1432 /* log core options (read using indexed model) */ 1433 reg = musb_read_configdata(mbase); 1434 1435 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1436 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1437 strcat(aInfo, ", dyn FIFOs"); 1438 musb->dyn_fifo = true; 1439 } 1440 #ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT 1441 if (reg & MUSB_CONFIGDATA_MPRXE) { 1442 strcat(aInfo, ", bulk combine"); 1443 musb->bulk_combine = true; 1444 } 1445 if (reg & MUSB_CONFIGDATA_MPTXE) { 1446 strcat(aInfo, ", bulk split"); 1447 musb->bulk_split = true; 1448 } 1449 #else 1450 musb->bulk_combine = false; 1451 musb->bulk_split = false; 1452 #endif 1453 if (reg & MUSB_CONFIGDATA_HBRXE) { 1454 strcat(aInfo, ", HB-ISO Rx"); 1455 musb->hb_iso_rx = true; 1456 } 1457 if (reg & MUSB_CONFIGDATA_HBTXE) { 1458 strcat(aInfo, ", HB-ISO Tx"); 1459 musb->hb_iso_tx = true; 1460 } 1461 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1462 strcat(aInfo, ", SoftConn"); 1463 1464 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1465 1466 aDate[0] = 0; 1467 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1468 musb->is_multipoint = 1; 1469 type = "M"; 1470 } else { 1471 musb->is_multipoint = 0; 1472 type = ""; 1473 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1474 printk(KERN_ERR 1475 "%s: kernel must blacklist external hubs\n", 1476 musb_driver_name); 1477 #endif 1478 } 1479 1480 /* log release info */ 1481 musb->hwvers = musb_read_hwvers(mbase); 1482 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1483 MUSB_HWVERS_MINOR(musb->hwvers), 1484 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1485 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, 1486 aRevision, aDate); 1487 1488 /* configure ep0 */ 1489 musb_configure_ep0(musb); 1490 1491 /* discover endpoint configuration */ 1492 musb->nr_endpoints = 1; 1493 musb->epmask = 1; 1494 1495 if (musb->dyn_fifo) 1496 status = ep_config_from_table(musb); 1497 else 1498 status = ep_config_from_hw(musb); 1499 1500 if (status < 0) 1501 return status; 1502 1503 /* finish init, and print endpoint config */ 1504 for (i = 0; i < musb->nr_endpoints; i++) { 1505 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1506 1507 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1508 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1509 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1510 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1511 hw_ep->fifo_sync_va = 1512 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1513 1514 if (i == 0) 1515 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1516 else 1517 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1518 #endif 1519 1520 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1521 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1522 hw_ep->rx_reinit = 1; 1523 hw_ep->tx_reinit = 1; 1524 1525 if (hw_ep->max_packet_sz_tx) { 1526 dev_dbg(musb->controller, 1527 "%s: hw_ep %d%s, %smax %d\n", 1528 musb_driver_name, i, 1529 hw_ep->is_shared_fifo ? "shared" : "tx", 1530 hw_ep->tx_double_buffered 1531 ? "doublebuffer, " : "", 1532 hw_ep->max_packet_sz_tx); 1533 } 1534 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1535 dev_dbg(musb->controller, 1536 "%s: hw_ep %d%s, %smax %d\n", 1537 musb_driver_name, i, 1538 "rx", 1539 hw_ep->rx_double_buffered 1540 ? "doublebuffer, " : "", 1541 hw_ep->max_packet_sz_rx); 1542 } 1543 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1544 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1545 } 1546 1547 return 0; 1548 } 1549 1550 /*-------------------------------------------------------------------------*/ 1551 1552 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1553 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1554 1555 static irqreturn_t generic_interrupt(int irq, void *__hci) 1556 { 1557 unsigned long flags; 1558 irqreturn_t retval = IRQ_NONE; 1559 struct musb *musb = __hci; 1560 1561 spin_lock_irqsave(&musb->lock, flags); 1562 1563 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1564 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1565 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1566 1567 if (musb->int_usb || musb->int_tx || musb->int_rx) 1568 retval = musb_interrupt(musb); 1569 1570 spin_unlock_irqrestore(&musb->lock, flags); 1571 1572 return retval; 1573 } 1574 1575 #else 1576 #define generic_interrupt NULL 1577 #endif 1578 1579 /* 1580 * handle all the irqs defined by the HDRC core. for now we expect: other 1581 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1582 * will be assigned, and the irq will already have been acked. 1583 * 1584 * called in irq context with spinlock held, irqs blocked 1585 */ 1586 irqreturn_t musb_interrupt(struct musb *musb) 1587 { 1588 irqreturn_t retval = IRQ_NONE; 1589 u8 devctl, power; 1590 int ep_num; 1591 u32 reg; 1592 1593 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1594 power = musb_readb(musb->mregs, MUSB_POWER); 1595 1596 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1597 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1598 musb->int_usb, musb->int_tx, musb->int_rx); 1599 1600 /* the core can interrupt us for multiple reasons; docs have 1601 * a generic interrupt flowchart to follow 1602 */ 1603 if (musb->int_usb) 1604 retval |= musb_stage0_irq(musb, musb->int_usb, 1605 devctl, power); 1606 1607 /* "stage 1" is handling endpoint irqs */ 1608 1609 /* handle endpoint 0 first */ 1610 if (musb->int_tx & 1) { 1611 if (devctl & MUSB_DEVCTL_HM) { 1612 if (is_host_capable()) 1613 retval |= musb_h_ep0_irq(musb); 1614 } else { 1615 if (is_peripheral_capable()) 1616 retval |= musb_g_ep0_irq(musb); 1617 } 1618 } 1619 1620 /* RX on endpoints 1-15 */ 1621 reg = musb->int_rx >> 1; 1622 ep_num = 1; 1623 while (reg) { 1624 if (reg & 1) { 1625 /* musb_ep_select(musb->mregs, ep_num); */ 1626 /* REVISIT just retval = ep->rx_irq(...) */ 1627 retval = IRQ_HANDLED; 1628 if (devctl & MUSB_DEVCTL_HM) { 1629 if (is_host_capable()) 1630 musb_host_rx(musb, ep_num); 1631 } else { 1632 if (is_peripheral_capable()) 1633 musb_g_rx(musb, ep_num); 1634 } 1635 } 1636 1637 reg >>= 1; 1638 ep_num++; 1639 } 1640 1641 /* TX on endpoints 1-15 */ 1642 reg = musb->int_tx >> 1; 1643 ep_num = 1; 1644 while (reg) { 1645 if (reg & 1) { 1646 /* musb_ep_select(musb->mregs, ep_num); */ 1647 /* REVISIT just retval |= ep->tx_irq(...) */ 1648 retval = IRQ_HANDLED; 1649 if (devctl & MUSB_DEVCTL_HM) { 1650 if (is_host_capable()) 1651 musb_host_tx(musb, ep_num); 1652 } else { 1653 if (is_peripheral_capable()) 1654 musb_g_tx(musb, ep_num); 1655 } 1656 } 1657 reg >>= 1; 1658 ep_num++; 1659 } 1660 1661 return retval; 1662 } 1663 EXPORT_SYMBOL_GPL(musb_interrupt); 1664 1665 #ifndef CONFIG_USB_MUSB_PIO_ONLY 1666 static bool __devinitdata use_dma = 1; 1667 1668 /* "modprobe ... use_dma=0" etc */ 1669 module_param(use_dma, bool, 0); 1670 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1671 1672 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1673 { 1674 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1675 1676 /* called with controller lock already held */ 1677 1678 if (!epnum) { 1679 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1680 if (!is_cppi_enabled()) { 1681 /* endpoint 0 */ 1682 if (devctl & MUSB_DEVCTL_HM) 1683 musb_h_ep0_irq(musb); 1684 else 1685 musb_g_ep0_irq(musb); 1686 } 1687 #endif 1688 } else { 1689 /* endpoints 1..15 */ 1690 if (transmit) { 1691 if (devctl & MUSB_DEVCTL_HM) { 1692 if (is_host_capable()) 1693 musb_host_tx(musb, epnum); 1694 } else { 1695 if (is_peripheral_capable()) 1696 musb_g_tx(musb, epnum); 1697 } 1698 } else { 1699 /* receive */ 1700 if (devctl & MUSB_DEVCTL_HM) { 1701 if (is_host_capable()) 1702 musb_host_rx(musb, epnum); 1703 } else { 1704 if (is_peripheral_capable()) 1705 musb_g_rx(musb, epnum); 1706 } 1707 } 1708 } 1709 } 1710 EXPORT_SYMBOL_GPL(musb_dma_completion); 1711 1712 #else 1713 #define use_dma 0 1714 #endif 1715 1716 /*-------------------------------------------------------------------------*/ 1717 1718 #ifdef CONFIG_SYSFS 1719 1720 static ssize_t 1721 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1722 { 1723 struct musb *musb = dev_to_musb(dev); 1724 unsigned long flags; 1725 int ret = -EINVAL; 1726 1727 spin_lock_irqsave(&musb->lock, flags); 1728 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1729 spin_unlock_irqrestore(&musb->lock, flags); 1730 1731 return ret; 1732 } 1733 1734 static ssize_t 1735 musb_mode_store(struct device *dev, struct device_attribute *attr, 1736 const char *buf, size_t n) 1737 { 1738 struct musb *musb = dev_to_musb(dev); 1739 unsigned long flags; 1740 int status; 1741 1742 spin_lock_irqsave(&musb->lock, flags); 1743 if (sysfs_streq(buf, "host")) 1744 status = musb_platform_set_mode(musb, MUSB_HOST); 1745 else if (sysfs_streq(buf, "peripheral")) 1746 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1747 else if (sysfs_streq(buf, "otg")) 1748 status = musb_platform_set_mode(musb, MUSB_OTG); 1749 else 1750 status = -EINVAL; 1751 spin_unlock_irqrestore(&musb->lock, flags); 1752 1753 return (status == 0) ? n : status; 1754 } 1755 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1756 1757 static ssize_t 1758 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1759 const char *buf, size_t n) 1760 { 1761 struct musb *musb = dev_to_musb(dev); 1762 unsigned long flags; 1763 unsigned long val; 1764 1765 if (sscanf(buf, "%lu", &val) < 1) { 1766 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1767 return -EINVAL; 1768 } 1769 1770 spin_lock_irqsave(&musb->lock, flags); 1771 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1772 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1773 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1774 musb->is_active = 0; 1775 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1776 spin_unlock_irqrestore(&musb->lock, flags); 1777 1778 return n; 1779 } 1780 1781 static ssize_t 1782 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1783 { 1784 struct musb *musb = dev_to_musb(dev); 1785 unsigned long flags; 1786 unsigned long val; 1787 int vbus; 1788 1789 spin_lock_irqsave(&musb->lock, flags); 1790 val = musb->a_wait_bcon; 1791 /* FIXME get_vbus_status() is normally #defined as false... 1792 * and is effectively TUSB-specific. 1793 */ 1794 vbus = musb_platform_get_vbus_status(musb); 1795 spin_unlock_irqrestore(&musb->lock, flags); 1796 1797 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1798 vbus ? "on" : "off", val); 1799 } 1800 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1801 1802 /* Gadget drivers can't know that a host is connected so they might want 1803 * to start SRP, but users can. This allows userspace to trigger SRP. 1804 */ 1805 static ssize_t 1806 musb_srp_store(struct device *dev, struct device_attribute *attr, 1807 const char *buf, size_t n) 1808 { 1809 struct musb *musb = dev_to_musb(dev); 1810 unsigned short srp; 1811 1812 if (sscanf(buf, "%hu", &srp) != 1 1813 || (srp != 1)) { 1814 dev_err(dev, "SRP: Value must be 1\n"); 1815 return -EINVAL; 1816 } 1817 1818 if (srp == 1) 1819 musb_g_wakeup(musb); 1820 1821 return n; 1822 } 1823 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1824 1825 static struct attribute *musb_attributes[] = { 1826 &dev_attr_mode.attr, 1827 &dev_attr_vbus.attr, 1828 &dev_attr_srp.attr, 1829 NULL 1830 }; 1831 1832 static const struct attribute_group musb_attr_group = { 1833 .attrs = musb_attributes, 1834 }; 1835 1836 #endif /* sysfs */ 1837 1838 #ifndef __UBOOT__ 1839 /* Only used to provide driver mode change events */ 1840 static void musb_irq_work(struct work_struct *data) 1841 { 1842 struct musb *musb = container_of(data, struct musb, irq_work); 1843 static int old_state; 1844 1845 if (musb->xceiv->state != old_state) { 1846 old_state = musb->xceiv->state; 1847 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1848 } 1849 } 1850 #endif 1851 1852 /* -------------------------------------------------------------------------- 1853 * Init support 1854 */ 1855 1856 static struct musb *__devinit 1857 allocate_instance(struct device *dev, 1858 struct musb_hdrc_config *config, void __iomem *mbase) 1859 { 1860 struct musb *musb; 1861 struct musb_hw_ep *ep; 1862 int epnum; 1863 #ifndef __UBOOT__ 1864 struct usb_hcd *hcd; 1865 1866 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1867 if (!hcd) 1868 return NULL; 1869 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1870 1871 musb = hcd_to_musb(hcd); 1872 #else 1873 musb = calloc(1, sizeof(*musb)); 1874 if (!musb) 1875 return NULL; 1876 #endif 1877 INIT_LIST_HEAD(&musb->control); 1878 INIT_LIST_HEAD(&musb->in_bulk); 1879 INIT_LIST_HEAD(&musb->out_bulk); 1880 1881 #ifndef __UBOOT__ 1882 hcd->uses_new_polling = 1; 1883 hcd->has_tt = 1; 1884 #endif 1885 1886 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1887 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1888 dev_set_drvdata(dev, musb); 1889 musb->mregs = mbase; 1890 musb->ctrl_base = mbase; 1891 musb->nIrq = -ENODEV; 1892 musb->config = config; 1893 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1894 for (epnum = 0, ep = musb->endpoints; 1895 epnum < musb->config->num_eps; 1896 epnum++, ep++) { 1897 ep->musb = musb; 1898 ep->epnum = epnum; 1899 } 1900 1901 musb->controller = dev; 1902 1903 return musb; 1904 } 1905 1906 static void musb_free(struct musb *musb) 1907 { 1908 /* this has multiple entry modes. it handles fault cleanup after 1909 * probe(), where things may be partially set up, as well as rmmod 1910 * cleanup after everything's been de-activated. 1911 */ 1912 1913 #ifdef CONFIG_SYSFS 1914 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1915 #endif 1916 1917 if (musb->nIrq >= 0) { 1918 if (musb->irq_wake) 1919 disable_irq_wake(musb->nIrq); 1920 free_irq(musb->nIrq, musb); 1921 } 1922 if (is_dma_capable() && musb->dma_controller) { 1923 struct dma_controller *c = musb->dma_controller; 1924 1925 (void) c->stop(c); 1926 dma_controller_destroy(c); 1927 } 1928 1929 kfree(musb); 1930 } 1931 1932 /* 1933 * Perform generic per-controller initialization. 1934 * 1935 * @pDevice: the controller (already clocked, etc) 1936 * @nIrq: irq 1937 * @mregs: virtual address of controller registers, 1938 * not yet corrected for platform-specific offsets 1939 */ 1940 #ifndef __UBOOT__ 1941 static int __devinit 1942 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1943 #else 1944 struct musb * 1945 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, 1946 void *ctrl) 1947 #endif 1948 { 1949 int status; 1950 struct musb *musb; 1951 #ifndef __UBOOT__ 1952 struct musb_hdrc_platform_data *plat = dev->platform_data; 1953 #else 1954 int nIrq = 0; 1955 #endif 1956 1957 /* The driver might handle more features than the board; OK. 1958 * Fail when the board needs a feature that's not enabled. 1959 */ 1960 if (!plat) { 1961 dev_dbg(dev, "no platform_data?\n"); 1962 status = -ENODEV; 1963 goto fail0; 1964 } 1965 1966 /* allocate */ 1967 musb = allocate_instance(dev, plat->config, ctrl); 1968 if (!musb) { 1969 status = -ENOMEM; 1970 goto fail0; 1971 } 1972 1973 pm_runtime_use_autosuspend(musb->controller); 1974 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1975 pm_runtime_enable(musb->controller); 1976 1977 spin_lock_init(&musb->lock); 1978 musb->board_mode = plat->mode; 1979 musb->board_set_power = plat->set_power; 1980 musb->min_power = plat->min_power; 1981 musb->ops = plat->platform_ops; 1982 1983 /* The musb_platform_init() call: 1984 * - adjusts musb->mregs and musb->isr if needed, 1985 * - may initialize an integrated tranceiver 1986 * - initializes musb->xceiv, usually by otg_get_phy() 1987 * - stops powering VBUS 1988 * 1989 * There are various transceiver configurations. Blackfin, 1990 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1991 * external/discrete ones in various flavors (twl4030 family, 1992 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1993 */ 1994 musb->isr = generic_interrupt; 1995 status = musb_platform_init(musb); 1996 if (status < 0) 1997 goto fail1; 1998 1999 if (!musb->isr) { 2000 status = -ENODEV; 2001 goto fail2; 2002 } 2003 2004 #ifndef __UBOOT__ 2005 if (!musb->xceiv->io_ops) { 2006 musb->xceiv->io_dev = musb->controller; 2007 musb->xceiv->io_priv = musb->mregs; 2008 musb->xceiv->io_ops = &musb_ulpi_access; 2009 } 2010 #endif 2011 2012 pm_runtime_get_sync(musb->controller); 2013 2014 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2015 if (use_dma && dev->dma_mask) { 2016 struct dma_controller *c; 2017 2018 c = dma_controller_create(musb, musb->mregs); 2019 musb->dma_controller = c; 2020 if (c) 2021 (void) c->start(c); 2022 } 2023 #endif 2024 #ifndef __UBOOT__ 2025 /* ideally this would be abstracted in platform setup */ 2026 if (!is_dma_capable() || !musb->dma_controller) 2027 dev->dma_mask = NULL; 2028 #endif 2029 2030 /* be sure interrupts are disabled before connecting ISR */ 2031 musb_platform_disable(musb); 2032 musb_generic_disable(musb); 2033 2034 /* setup musb parts of the core (especially endpoints) */ 2035 status = musb_core_init(plat->config->multipoint 2036 ? MUSB_CONTROLLER_MHDRC 2037 : MUSB_CONTROLLER_HDRC, musb); 2038 if (status < 0) 2039 goto fail3; 2040 2041 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2042 2043 /* Init IRQ workqueue before request_irq */ 2044 INIT_WORK(&musb->irq_work, musb_irq_work); 2045 2046 /* attach to the IRQ */ 2047 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2048 dev_err(dev, "request_irq %d failed!\n", nIrq); 2049 status = -ENODEV; 2050 goto fail3; 2051 } 2052 musb->nIrq = nIrq; 2053 /* FIXME this handles wakeup irqs wrong */ 2054 if (enable_irq_wake(nIrq) == 0) { 2055 musb->irq_wake = 1; 2056 device_init_wakeup(dev, 1); 2057 } else { 2058 musb->irq_wake = 0; 2059 } 2060 2061 #ifndef __UBOOT__ 2062 /* host side needs more setup */ 2063 if (is_host_enabled(musb)) { 2064 struct usb_hcd *hcd = musb_to_hcd(musb); 2065 2066 otg_set_host(musb->xceiv->otg, &hcd->self); 2067 2068 if (is_otg_enabled(musb)) 2069 hcd->self.otg_port = 1; 2070 musb->xceiv->otg->host = &hcd->self; 2071 hcd->power_budget = 2 * (plat->power ? : 250); 2072 2073 /* program PHY to use external vBus if required */ 2074 if (plat->extvbus) { 2075 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2076 busctl |= MUSB_ULPI_USE_EXTVBUS; 2077 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2078 } 2079 } 2080 #endif 2081 2082 /* For the host-only role, we can activate right away. 2083 * (We expect the ID pin to be forcibly grounded!!) 2084 * Otherwise, wait till the gadget driver hooks up. 2085 */ 2086 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2087 struct usb_hcd *hcd = musb_to_hcd(musb); 2088 2089 MUSB_HST_MODE(musb); 2090 #ifndef __UBOOT__ 2091 musb->xceiv->otg->default_a = 1; 2092 musb->xceiv->state = OTG_STATE_A_IDLE; 2093 2094 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2095 2096 hcd->self.uses_pio_for_control = 1; 2097 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2098 "HOST", status, 2099 musb_readb(musb->mregs, MUSB_DEVCTL), 2100 (musb_readb(musb->mregs, MUSB_DEVCTL) 2101 & MUSB_DEVCTL_BDEVICE 2102 ? 'B' : 'A')); 2103 #endif 2104 2105 } else /* peripheral is enabled */ { 2106 MUSB_DEV_MODE(musb); 2107 #ifndef __UBOOT__ 2108 musb->xceiv->otg->default_a = 0; 2109 musb->xceiv->state = OTG_STATE_B_IDLE; 2110 #endif 2111 2112 if (is_peripheral_capable()) 2113 status = musb_gadget_setup(musb); 2114 2115 #ifndef __UBOOT__ 2116 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2117 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2118 status, 2119 musb_readb(musb->mregs, MUSB_DEVCTL)); 2120 #endif 2121 2122 } 2123 if (status < 0) 2124 goto fail3; 2125 2126 status = musb_init_debugfs(musb); 2127 if (status < 0) 2128 goto fail4; 2129 2130 #ifdef CONFIG_SYSFS 2131 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2132 if (status) 2133 goto fail5; 2134 #endif 2135 2136 pm_runtime_put(musb->controller); 2137 2138 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", 2139 ({char *s; 2140 switch (musb->board_mode) { 2141 case MUSB_HOST: s = "Host"; break; 2142 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2143 default: s = "OTG"; break; 2144 }; s; }), 2145 ctrl, 2146 (is_dma_capable() && musb->dma_controller) 2147 ? "DMA" : "PIO", 2148 musb->nIrq); 2149 2150 #ifndef __UBOOT__ 2151 return 0; 2152 #else 2153 return status == 0 ? musb : NULL; 2154 #endif 2155 2156 fail5: 2157 musb_exit_debugfs(musb); 2158 2159 fail4: 2160 #ifndef __UBOOT__ 2161 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2162 usb_remove_hcd(musb_to_hcd(musb)); 2163 else 2164 #endif 2165 musb_gadget_cleanup(musb); 2166 2167 fail3: 2168 pm_runtime_put_sync(musb->controller); 2169 2170 fail2: 2171 if (musb->irq_wake) 2172 device_init_wakeup(dev, 0); 2173 musb_platform_exit(musb); 2174 2175 fail1: 2176 dev_err(musb->controller, 2177 "musb_init_controller failed with status %d\n", status); 2178 2179 musb_free(musb); 2180 2181 fail0: 2182 2183 #ifndef __UBOOT__ 2184 return status; 2185 #else 2186 return status == 0 ? musb : NULL; 2187 #endif 2188 2189 } 2190 2191 /*-------------------------------------------------------------------------*/ 2192 2193 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2194 * bridge to a platform device; this driver then suffices. 2195 */ 2196 2197 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2198 static u64 *orig_dma_mask; 2199 #endif 2200 2201 #ifndef __UBOOT__ 2202 static int __devinit musb_probe(struct platform_device *pdev) 2203 { 2204 struct device *dev = &pdev->dev; 2205 int irq = platform_get_irq_byname(pdev, "mc"); 2206 int status; 2207 struct resource *iomem; 2208 void __iomem *base; 2209 2210 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2211 if (!iomem || irq <= 0) 2212 return -ENODEV; 2213 2214 base = ioremap(iomem->start, resource_size(iomem)); 2215 if (!base) { 2216 dev_err(dev, "ioremap failed\n"); 2217 return -ENOMEM; 2218 } 2219 2220 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2221 /* clobbered by use_dma=n */ 2222 orig_dma_mask = dev->dma_mask; 2223 #endif 2224 status = musb_init_controller(dev, irq, base); 2225 if (status < 0) 2226 iounmap(base); 2227 2228 return status; 2229 } 2230 2231 static int __devexit musb_remove(struct platform_device *pdev) 2232 { 2233 struct musb *musb = dev_to_musb(&pdev->dev); 2234 void __iomem *ctrl_base = musb->ctrl_base; 2235 2236 /* this gets called on rmmod. 2237 * - Host mode: host may still be active 2238 * - Peripheral mode: peripheral is deactivated (or never-activated) 2239 * - OTG mode: both roles are deactivated (or never-activated) 2240 */ 2241 musb_exit_debugfs(musb); 2242 musb_shutdown(pdev); 2243 2244 musb_free(musb); 2245 iounmap(ctrl_base); 2246 device_init_wakeup(&pdev->dev, 0); 2247 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2248 pdev->dev.dma_mask = orig_dma_mask; 2249 #endif 2250 return 0; 2251 } 2252 2253 #ifdef CONFIG_PM 2254 2255 static void musb_save_context(struct musb *musb) 2256 { 2257 int i; 2258 void __iomem *musb_base = musb->mregs; 2259 void __iomem *epio; 2260 2261 if (is_host_enabled(musb)) { 2262 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2263 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2264 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2265 } 2266 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2267 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2268 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2269 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2270 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2271 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2272 2273 for (i = 0; i < musb->config->num_eps; ++i) { 2274 struct musb_hw_ep *hw_ep; 2275 2276 hw_ep = &musb->endpoints[i]; 2277 if (!hw_ep) 2278 continue; 2279 2280 epio = hw_ep->regs; 2281 if (!epio) 2282 continue; 2283 2284 musb_writeb(musb_base, MUSB_INDEX, i); 2285 musb->context.index_regs[i].txmaxp = 2286 musb_readw(epio, MUSB_TXMAXP); 2287 musb->context.index_regs[i].txcsr = 2288 musb_readw(epio, MUSB_TXCSR); 2289 musb->context.index_regs[i].rxmaxp = 2290 musb_readw(epio, MUSB_RXMAXP); 2291 musb->context.index_regs[i].rxcsr = 2292 musb_readw(epio, MUSB_RXCSR); 2293 2294 if (musb->dyn_fifo) { 2295 musb->context.index_regs[i].txfifoadd = 2296 musb_read_txfifoadd(musb_base); 2297 musb->context.index_regs[i].rxfifoadd = 2298 musb_read_rxfifoadd(musb_base); 2299 musb->context.index_regs[i].txfifosz = 2300 musb_read_txfifosz(musb_base); 2301 musb->context.index_regs[i].rxfifosz = 2302 musb_read_rxfifosz(musb_base); 2303 } 2304 if (is_host_enabled(musb)) { 2305 musb->context.index_regs[i].txtype = 2306 musb_readb(epio, MUSB_TXTYPE); 2307 musb->context.index_regs[i].txinterval = 2308 musb_readb(epio, MUSB_TXINTERVAL); 2309 musb->context.index_regs[i].rxtype = 2310 musb_readb(epio, MUSB_RXTYPE); 2311 musb->context.index_regs[i].rxinterval = 2312 musb_readb(epio, MUSB_RXINTERVAL); 2313 2314 musb->context.index_regs[i].txfunaddr = 2315 musb_read_txfunaddr(musb_base, i); 2316 musb->context.index_regs[i].txhubaddr = 2317 musb_read_txhubaddr(musb_base, i); 2318 musb->context.index_regs[i].txhubport = 2319 musb_read_txhubport(musb_base, i); 2320 2321 musb->context.index_regs[i].rxfunaddr = 2322 musb_read_rxfunaddr(musb_base, i); 2323 musb->context.index_regs[i].rxhubaddr = 2324 musb_read_rxhubaddr(musb_base, i); 2325 musb->context.index_regs[i].rxhubport = 2326 musb_read_rxhubport(musb_base, i); 2327 } 2328 } 2329 } 2330 2331 static void musb_restore_context(struct musb *musb) 2332 { 2333 int i; 2334 void __iomem *musb_base = musb->mregs; 2335 void __iomem *ep_target_regs; 2336 void __iomem *epio; 2337 2338 if (is_host_enabled(musb)) { 2339 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2340 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2341 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2342 } 2343 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2344 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2345 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2346 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2347 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2348 2349 for (i = 0; i < musb->config->num_eps; ++i) { 2350 struct musb_hw_ep *hw_ep; 2351 2352 hw_ep = &musb->endpoints[i]; 2353 if (!hw_ep) 2354 continue; 2355 2356 epio = hw_ep->regs; 2357 if (!epio) 2358 continue; 2359 2360 musb_writeb(musb_base, MUSB_INDEX, i); 2361 musb_writew(epio, MUSB_TXMAXP, 2362 musb->context.index_regs[i].txmaxp); 2363 musb_writew(epio, MUSB_TXCSR, 2364 musb->context.index_regs[i].txcsr); 2365 musb_writew(epio, MUSB_RXMAXP, 2366 musb->context.index_regs[i].rxmaxp); 2367 musb_writew(epio, MUSB_RXCSR, 2368 musb->context.index_regs[i].rxcsr); 2369 2370 if (musb->dyn_fifo) { 2371 musb_write_txfifosz(musb_base, 2372 musb->context.index_regs[i].txfifosz); 2373 musb_write_rxfifosz(musb_base, 2374 musb->context.index_regs[i].rxfifosz); 2375 musb_write_txfifoadd(musb_base, 2376 musb->context.index_regs[i].txfifoadd); 2377 musb_write_rxfifoadd(musb_base, 2378 musb->context.index_regs[i].rxfifoadd); 2379 } 2380 2381 if (is_host_enabled(musb)) { 2382 musb_writeb(epio, MUSB_TXTYPE, 2383 musb->context.index_regs[i].txtype); 2384 musb_writeb(epio, MUSB_TXINTERVAL, 2385 musb->context.index_regs[i].txinterval); 2386 musb_writeb(epio, MUSB_RXTYPE, 2387 musb->context.index_regs[i].rxtype); 2388 musb_writeb(epio, MUSB_RXINTERVAL, 2389 2390 musb->context.index_regs[i].rxinterval); 2391 musb_write_txfunaddr(musb_base, i, 2392 musb->context.index_regs[i].txfunaddr); 2393 musb_write_txhubaddr(musb_base, i, 2394 musb->context.index_regs[i].txhubaddr); 2395 musb_write_txhubport(musb_base, i, 2396 musb->context.index_regs[i].txhubport); 2397 2398 ep_target_regs = 2399 musb_read_target_reg_base(i, musb_base); 2400 2401 musb_write_rxfunaddr(ep_target_regs, 2402 musb->context.index_regs[i].rxfunaddr); 2403 musb_write_rxhubaddr(ep_target_regs, 2404 musb->context.index_regs[i].rxhubaddr); 2405 musb_write_rxhubport(ep_target_regs, 2406 musb->context.index_regs[i].rxhubport); 2407 } 2408 } 2409 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2410 } 2411 2412 static int musb_suspend(struct device *dev) 2413 { 2414 struct musb *musb = dev_to_musb(dev); 2415 unsigned long flags; 2416 2417 spin_lock_irqsave(&musb->lock, flags); 2418 2419 if (is_peripheral_active(musb)) { 2420 /* FIXME force disconnect unless we know USB will wake 2421 * the system up quickly enough to respond ... 2422 */ 2423 } else if (is_host_active(musb)) { 2424 /* we know all the children are suspended; sometimes 2425 * they will even be wakeup-enabled. 2426 */ 2427 } 2428 2429 spin_unlock_irqrestore(&musb->lock, flags); 2430 return 0; 2431 } 2432 2433 static int musb_resume_noirq(struct device *dev) 2434 { 2435 /* for static cmos like DaVinci, register values were preserved 2436 * unless for some reason the whole soc powered down or the USB 2437 * module got reset through the PSC (vs just being disabled). 2438 */ 2439 return 0; 2440 } 2441 2442 static int musb_runtime_suspend(struct device *dev) 2443 { 2444 struct musb *musb = dev_to_musb(dev); 2445 2446 musb_save_context(musb); 2447 2448 return 0; 2449 } 2450 2451 static int musb_runtime_resume(struct device *dev) 2452 { 2453 struct musb *musb = dev_to_musb(dev); 2454 static int first = 1; 2455 2456 /* 2457 * When pm_runtime_get_sync called for the first time in driver 2458 * init, some of the structure is still not initialized which is 2459 * used in restore function. But clock needs to be 2460 * enabled before any register access, so 2461 * pm_runtime_get_sync has to be called. 2462 * Also context restore without save does not make 2463 * any sense 2464 */ 2465 if (!first) 2466 musb_restore_context(musb); 2467 first = 0; 2468 2469 return 0; 2470 } 2471 2472 static const struct dev_pm_ops musb_dev_pm_ops = { 2473 .suspend = musb_suspend, 2474 .resume_noirq = musb_resume_noirq, 2475 .runtime_suspend = musb_runtime_suspend, 2476 .runtime_resume = musb_runtime_resume, 2477 }; 2478 2479 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2480 #else 2481 #define MUSB_DEV_PM_OPS NULL 2482 #endif 2483 2484 static struct platform_driver musb_driver = { 2485 .driver = { 2486 .name = (char *)musb_driver_name, 2487 .bus = &platform_bus_type, 2488 .owner = THIS_MODULE, 2489 .pm = MUSB_DEV_PM_OPS, 2490 }, 2491 .probe = musb_probe, 2492 .remove = __devexit_p(musb_remove), 2493 .shutdown = musb_shutdown, 2494 }; 2495 2496 /*-------------------------------------------------------------------------*/ 2497 2498 static int __init musb_init(void) 2499 { 2500 if (usb_disabled()) 2501 return 0; 2502 2503 pr_info("%s: version " MUSB_VERSION ", " 2504 "?dma?" 2505 ", " 2506 "otg (peripheral+host)", 2507 musb_driver_name); 2508 return platform_driver_register(&musb_driver); 2509 } 2510 module_init(musb_init); 2511 2512 static void __exit musb_cleanup(void) 2513 { 2514 platform_driver_unregister(&musb_driver); 2515 } 2516 module_exit(musb_cleanup); 2517 #endif 2518