1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82 /* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92 #define __UBOOT__ 93 #ifndef __UBOOT__ 94 #include <linux/module.h> 95 #include <linux/kernel.h> 96 #include <linux/sched.h> 97 #include <linux/slab.h> 98 #include <linux/init.h> 99 #include <linux/list.h> 100 #include <linux/kobject.h> 101 #include <linux/prefetch.h> 102 #include <linux/platform_device.h> 103 #include <linux/io.h> 104 #else 105 #include <common.h> 106 #include <usb.h> 107 #include <asm/errno.h> 108 #include <linux/usb/ch9.h> 109 #include <linux/usb/gadget.h> 110 #include <linux/usb/musb.h> 111 #include <asm/io.h> 112 #include "linux-compat.h" 113 #include "usb-compat.h" 114 #endif 115 116 #include "musb_core.h" 117 118 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 119 120 121 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 122 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 123 124 #define MUSB_VERSION "6.0" 125 126 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 127 128 #define MUSB_DRIVER_NAME "musb-hdrc" 129 const char musb_driver_name[] = MUSB_DRIVER_NAME; 130 131 MODULE_DESCRIPTION(DRIVER_INFO); 132 MODULE_AUTHOR(DRIVER_AUTHOR); 133 MODULE_LICENSE("GPL"); 134 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 135 136 137 #ifndef __UBOOT__ 138 /*-------------------------------------------------------------------------*/ 139 140 static inline struct musb *dev_to_musb(struct device *dev) 141 { 142 return dev_get_drvdata(dev); 143 } 144 #endif 145 146 /*-------------------------------------------------------------------------*/ 147 148 #ifndef __UBOOT__ 149 #ifndef CONFIG_BLACKFIN 150 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 151 { 152 void __iomem *addr = phy->io_priv; 153 int i = 0; 154 u8 r; 155 u8 power; 156 int ret; 157 158 pm_runtime_get_sync(phy->io_dev); 159 160 /* Make sure the transceiver is not in low power mode */ 161 power = musb_readb(addr, MUSB_POWER); 162 power &= ~MUSB_POWER_SUSPENDM; 163 musb_writeb(addr, MUSB_POWER, power); 164 165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 167 */ 168 169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 172 173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 174 & MUSB_ULPI_REG_CMPLT)) { 175 i++; 176 if (i == 10000) { 177 ret = -ETIMEDOUT; 178 goto out; 179 } 180 181 } 182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 183 r &= ~MUSB_ULPI_REG_CMPLT; 184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 185 186 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 187 188 out: 189 pm_runtime_put(phy->io_dev); 190 191 return ret; 192 } 193 194 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 195 { 196 void __iomem *addr = phy->io_priv; 197 int i = 0; 198 u8 r = 0; 199 u8 power; 200 int ret = 0; 201 202 pm_runtime_get_sync(phy->io_dev); 203 204 /* Make sure the transceiver is not in low power mode */ 205 power = musb_readb(addr, MUSB_POWER); 206 power &= ~MUSB_POWER_SUSPENDM; 207 musb_writeb(addr, MUSB_POWER, power); 208 209 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 210 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 211 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 212 213 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 214 & MUSB_ULPI_REG_CMPLT)) { 215 i++; 216 if (i == 10000) { 217 ret = -ETIMEDOUT; 218 goto out; 219 } 220 } 221 222 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 223 r &= ~MUSB_ULPI_REG_CMPLT; 224 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 225 226 out: 227 pm_runtime_put(phy->io_dev); 228 229 return ret; 230 } 231 #else 232 #define musb_ulpi_read NULL 233 #define musb_ulpi_write NULL 234 #endif 235 236 static struct usb_phy_io_ops musb_ulpi_access = { 237 .read = musb_ulpi_read, 238 .write = musb_ulpi_write, 239 }; 240 #endif 241 242 /*-------------------------------------------------------------------------*/ 243 244 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 245 246 /* 247 * Load an endpoint's FIFO 248 */ 249 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 250 { 251 struct musb *musb = hw_ep->musb; 252 void __iomem *fifo = hw_ep->fifo; 253 254 prefetch((u8 *)src); 255 256 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 257 'T', hw_ep->epnum, fifo, len, src); 258 259 /* we can't assume unaligned reads work */ 260 if (likely((0x01 & (unsigned long) src) == 0)) { 261 u16 index = 0; 262 263 /* best case is 32bit-aligned source address */ 264 if ((0x02 & (unsigned long) src) == 0) { 265 if (len >= 4) { 266 writesl(fifo, src + index, len >> 2); 267 index += len & ~0x03; 268 } 269 if (len & 0x02) { 270 musb_writew(fifo, 0, *(u16 *)&src[index]); 271 index += 2; 272 } 273 } else { 274 if (len >= 2) { 275 writesw(fifo, src + index, len >> 1); 276 index += len & ~0x01; 277 } 278 } 279 if (len & 0x01) 280 musb_writeb(fifo, 0, src[index]); 281 } else { 282 /* byte aligned */ 283 writesb(fifo, src, len); 284 } 285 } 286 287 #if !defined(CONFIG_USB_MUSB_AM35X) 288 /* 289 * Unload an endpoint's FIFO 290 */ 291 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 292 { 293 struct musb *musb = hw_ep->musb; 294 void __iomem *fifo = hw_ep->fifo; 295 296 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 297 'R', hw_ep->epnum, fifo, len, dst); 298 299 /* we can't assume unaligned writes work */ 300 if (likely((0x01 & (unsigned long) dst) == 0)) { 301 u16 index = 0; 302 303 /* best case is 32bit-aligned destination address */ 304 if ((0x02 & (unsigned long) dst) == 0) { 305 if (len >= 4) { 306 readsl(fifo, dst, len >> 2); 307 index = len & ~0x03; 308 } 309 if (len & 0x02) { 310 *(u16 *)&dst[index] = musb_readw(fifo, 0); 311 index += 2; 312 } 313 } else { 314 if (len >= 2) { 315 readsw(fifo, dst, len >> 1); 316 index = len & ~0x01; 317 } 318 } 319 if (len & 0x01) 320 dst[index] = musb_readb(fifo, 0); 321 } else { 322 /* byte aligned */ 323 readsb(fifo, dst, len); 324 } 325 } 326 #endif 327 328 #endif /* normal PIO */ 329 330 331 /*-------------------------------------------------------------------------*/ 332 333 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 334 static const u8 musb_test_packet[53] = { 335 /* implicit SYNC then DATA0 to start */ 336 337 /* JKJKJKJK x9 */ 338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 339 /* JJKKJJKK x8 */ 340 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 341 /* JJJJKKKK x8 */ 342 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 343 /* JJJJJJJKKKKKKK x8 */ 344 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 345 /* JJJJJJJK x8 */ 346 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 347 /* JKKKKKKK x10, JK */ 348 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 349 350 /* implicit CRC16 then EOP to end */ 351 }; 352 353 void musb_load_testpacket(struct musb *musb) 354 { 355 void __iomem *regs = musb->endpoints[0].regs; 356 357 musb_ep_select(musb->mregs, 0); 358 musb_write_fifo(musb->control_ep, 359 sizeof(musb_test_packet), musb_test_packet); 360 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 361 } 362 363 #ifndef __UBOOT__ 364 /*-------------------------------------------------------------------------*/ 365 366 /* 367 * Handles OTG hnp timeouts, such as b_ase0_brst 368 */ 369 void musb_otg_timer_func(unsigned long data) 370 { 371 struct musb *musb = (struct musb *)data; 372 unsigned long flags; 373 374 spin_lock_irqsave(&musb->lock, flags); 375 switch (musb->xceiv->state) { 376 case OTG_STATE_B_WAIT_ACON: 377 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 378 musb_g_disconnect(musb); 379 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 380 musb->is_active = 0; 381 break; 382 case OTG_STATE_A_SUSPEND: 383 case OTG_STATE_A_WAIT_BCON: 384 dev_dbg(musb->controller, "HNP: %s timeout\n", 385 otg_state_string(musb->xceiv->state)); 386 musb_platform_set_vbus(musb, 0); 387 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 388 break; 389 default: 390 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 391 otg_state_string(musb->xceiv->state)); 392 } 393 musb->ignore_disconnect = 0; 394 spin_unlock_irqrestore(&musb->lock, flags); 395 } 396 397 /* 398 * Stops the HNP transition. Caller must take care of locking. 399 */ 400 void musb_hnp_stop(struct musb *musb) 401 { 402 struct usb_hcd *hcd = musb_to_hcd(musb); 403 void __iomem *mbase = musb->mregs; 404 u8 reg; 405 406 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 407 408 switch (musb->xceiv->state) { 409 case OTG_STATE_A_PERIPHERAL: 410 musb_g_disconnect(musb); 411 dev_dbg(musb->controller, "HNP: back to %s\n", 412 otg_state_string(musb->xceiv->state)); 413 break; 414 case OTG_STATE_B_HOST: 415 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 416 hcd->self.is_b_host = 0; 417 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 418 MUSB_DEV_MODE(musb); 419 reg = musb_readb(mbase, MUSB_POWER); 420 reg |= MUSB_POWER_SUSPENDM; 421 musb_writeb(mbase, MUSB_POWER, reg); 422 /* REVISIT: Start SESSION_REQUEST here? */ 423 break; 424 default: 425 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 426 otg_state_string(musb->xceiv->state)); 427 } 428 429 /* 430 * When returning to A state after HNP, avoid hub_port_rebounce(), 431 * which cause occasional OPT A "Did not receive reset after connect" 432 * errors. 433 */ 434 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 435 } 436 #endif 437 438 /* 439 * Interrupt Service Routine to record USB "global" interrupts. 440 * Since these do not happen often and signify things of 441 * paramount importance, it seems OK to check them individually; 442 * the order of the tests is specified in the manual 443 * 444 * @param musb instance pointer 445 * @param int_usb register contents 446 * @param devctl 447 * @param power 448 */ 449 450 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 451 u8 devctl, u8 power) 452 { 453 #ifndef __UBOOT__ 454 struct usb_otg *otg = musb->xceiv->otg; 455 #endif 456 irqreturn_t handled = IRQ_NONE; 457 458 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 459 int_usb); 460 461 #ifndef __UBOOT__ 462 /* in host mode, the peripheral may issue remote wakeup. 463 * in peripheral mode, the host may resume the link. 464 * spurious RESUME irqs happen too, paired with SUSPEND. 465 */ 466 if (int_usb & MUSB_INTR_RESUME) { 467 handled = IRQ_HANDLED; 468 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 469 470 if (devctl & MUSB_DEVCTL_HM) { 471 void __iomem *mbase = musb->mregs; 472 473 switch (musb->xceiv->state) { 474 case OTG_STATE_A_SUSPEND: 475 /* remote wakeup? later, GetPortStatus 476 * will stop RESUME signaling 477 */ 478 479 if (power & MUSB_POWER_SUSPENDM) { 480 /* spurious */ 481 musb->int_usb &= ~MUSB_INTR_SUSPEND; 482 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 483 break; 484 } 485 486 power &= ~MUSB_POWER_SUSPENDM; 487 musb_writeb(mbase, MUSB_POWER, 488 power | MUSB_POWER_RESUME); 489 490 musb->port1_status |= 491 (USB_PORT_STAT_C_SUSPEND << 16) 492 | MUSB_PORT_STAT_RESUME; 493 musb->rh_timer = jiffies 494 + msecs_to_jiffies(20); 495 496 musb->xceiv->state = OTG_STATE_A_HOST; 497 musb->is_active = 1; 498 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 499 break; 500 case OTG_STATE_B_WAIT_ACON: 501 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 502 musb->is_active = 1; 503 MUSB_DEV_MODE(musb); 504 break; 505 default: 506 WARNING("bogus %s RESUME (%s)\n", 507 "host", 508 otg_state_string(musb->xceiv->state)); 509 } 510 } else { 511 switch (musb->xceiv->state) { 512 case OTG_STATE_A_SUSPEND: 513 /* possibly DISCONNECT is upcoming */ 514 musb->xceiv->state = OTG_STATE_A_HOST; 515 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 516 break; 517 case OTG_STATE_B_WAIT_ACON: 518 case OTG_STATE_B_PERIPHERAL: 519 /* disconnect while suspended? we may 520 * not get a disconnect irq... 521 */ 522 if ((devctl & MUSB_DEVCTL_VBUS) 523 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 524 ) { 525 musb->int_usb |= MUSB_INTR_DISCONNECT; 526 musb->int_usb &= ~MUSB_INTR_SUSPEND; 527 break; 528 } 529 musb_g_resume(musb); 530 break; 531 case OTG_STATE_B_IDLE: 532 musb->int_usb &= ~MUSB_INTR_SUSPEND; 533 break; 534 default: 535 WARNING("bogus %s RESUME (%s)\n", 536 "peripheral", 537 otg_state_string(musb->xceiv->state)); 538 } 539 } 540 } 541 542 /* see manual for the order of the tests */ 543 if (int_usb & MUSB_INTR_SESSREQ) { 544 void __iomem *mbase = musb->mregs; 545 546 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 547 && (devctl & MUSB_DEVCTL_BDEVICE)) { 548 dev_dbg(musb->controller, "SessReq while on B state\n"); 549 return IRQ_HANDLED; 550 } 551 552 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 553 otg_state_string(musb->xceiv->state)); 554 555 /* IRQ arrives from ID pin sense or (later, if VBUS power 556 * is removed) SRP. responses are time critical: 557 * - turn on VBUS (with silicon-specific mechanism) 558 * - go through A_WAIT_VRISE 559 * - ... to A_WAIT_BCON. 560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 561 */ 562 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 563 musb->ep0_stage = MUSB_EP0_START; 564 musb->xceiv->state = OTG_STATE_A_IDLE; 565 MUSB_HST_MODE(musb); 566 musb_platform_set_vbus(musb, 1); 567 568 handled = IRQ_HANDLED; 569 } 570 571 if (int_usb & MUSB_INTR_VBUSERROR) { 572 int ignore = 0; 573 574 /* During connection as an A-Device, we may see a short 575 * current spikes causing voltage drop, because of cable 576 * and peripheral capacitance combined with vbus draw. 577 * (So: less common with truly self-powered devices, where 578 * vbus doesn't act like a power supply.) 579 * 580 * Such spikes are short; usually less than ~500 usec, max 581 * of ~2 msec. That is, they're not sustained overcurrent 582 * errors, though they're reported using VBUSERROR irqs. 583 * 584 * Workarounds: (a) hardware: use self powered devices. 585 * (b) software: ignore non-repeated VBUS errors. 586 * 587 * REVISIT: do delays from lots of DEBUG_KERNEL checks 588 * make trouble here, keeping VBUS < 4.4V ? 589 */ 590 switch (musb->xceiv->state) { 591 case OTG_STATE_A_HOST: 592 /* recovery is dicey once we've gotten past the 593 * initial stages of enumeration, but if VBUS 594 * stayed ok at the other end of the link, and 595 * another reset is due (at least for high speed, 596 * to redo the chirp etc), it might work OK... 597 */ 598 case OTG_STATE_A_WAIT_BCON: 599 case OTG_STATE_A_WAIT_VRISE: 600 if (musb->vbuserr_retry) { 601 void __iomem *mbase = musb->mregs; 602 603 musb->vbuserr_retry--; 604 ignore = 1; 605 devctl |= MUSB_DEVCTL_SESSION; 606 musb_writeb(mbase, MUSB_DEVCTL, devctl); 607 } else { 608 musb->port1_status |= 609 USB_PORT_STAT_OVERCURRENT 610 | (USB_PORT_STAT_C_OVERCURRENT << 16); 611 } 612 break; 613 default: 614 break; 615 } 616 617 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 618 otg_state_string(musb->xceiv->state), 619 devctl, 620 ({ char *s; 621 switch (devctl & MUSB_DEVCTL_VBUS) { 622 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 623 s = "<SessEnd"; break; 624 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 625 s = "<AValid"; break; 626 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 627 s = "<VBusValid"; break; 628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 629 default: 630 s = "VALID"; break; 631 }; s; }), 632 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 633 musb->port1_status); 634 635 /* go through A_WAIT_VFALL then start a new session */ 636 if (!ignore) 637 musb_platform_set_vbus(musb, 0); 638 handled = IRQ_HANDLED; 639 } 640 641 if (int_usb & MUSB_INTR_SUSPEND) { 642 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 643 otg_state_string(musb->xceiv->state), devctl, power); 644 handled = IRQ_HANDLED; 645 646 switch (musb->xceiv->state) { 647 case OTG_STATE_A_PERIPHERAL: 648 /* We also come here if the cable is removed, since 649 * this silicon doesn't report ID-no-longer-grounded. 650 * 651 * We depend on T(a_wait_bcon) to shut us down, and 652 * hope users don't do anything dicey during this 653 * undesired detour through A_WAIT_BCON. 654 */ 655 musb_hnp_stop(musb); 656 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 657 musb_root_disconnect(musb); 658 musb_platform_try_idle(musb, jiffies 659 + msecs_to_jiffies(musb->a_wait_bcon 660 ? : OTG_TIME_A_WAIT_BCON)); 661 662 break; 663 case OTG_STATE_B_IDLE: 664 if (!musb->is_active) 665 break; 666 case OTG_STATE_B_PERIPHERAL: 667 musb_g_suspend(musb); 668 musb->is_active = is_otg_enabled(musb) 669 && otg->gadget->b_hnp_enable; 670 if (musb->is_active) { 671 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 672 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 673 mod_timer(&musb->otg_timer, jiffies 674 + msecs_to_jiffies( 675 OTG_TIME_B_ASE0_BRST)); 676 } 677 break; 678 case OTG_STATE_A_WAIT_BCON: 679 if (musb->a_wait_bcon != 0) 680 musb_platform_try_idle(musb, jiffies 681 + msecs_to_jiffies(musb->a_wait_bcon)); 682 break; 683 case OTG_STATE_A_HOST: 684 musb->xceiv->state = OTG_STATE_A_SUSPEND; 685 musb->is_active = is_otg_enabled(musb) 686 && otg->host->b_hnp_enable; 687 break; 688 case OTG_STATE_B_HOST: 689 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 690 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 691 break; 692 default: 693 /* "should not happen" */ 694 musb->is_active = 0; 695 break; 696 } 697 } 698 #endif 699 700 if (int_usb & MUSB_INTR_CONNECT) { 701 struct usb_hcd *hcd = musb_to_hcd(musb); 702 703 handled = IRQ_HANDLED; 704 musb->is_active = 1; 705 706 musb->ep0_stage = MUSB_EP0_START; 707 708 /* flush endpoints when transitioning from Device Mode */ 709 if (is_peripheral_active(musb)) { 710 /* REVISIT HNP; just force disconnect */ 711 } 712 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 713 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 714 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 715 #ifndef __UBOOT__ 716 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 717 |USB_PORT_STAT_HIGH_SPEED 718 |USB_PORT_STAT_ENABLE 719 ); 720 musb->port1_status |= USB_PORT_STAT_CONNECTION 721 |(USB_PORT_STAT_C_CONNECTION << 16); 722 723 /* high vs full speed is just a guess until after reset */ 724 if (devctl & MUSB_DEVCTL_LSDEV) 725 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 726 727 /* indicate new connection to OTG machine */ 728 switch (musb->xceiv->state) { 729 case OTG_STATE_B_PERIPHERAL: 730 if (int_usb & MUSB_INTR_SUSPEND) { 731 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 732 int_usb &= ~MUSB_INTR_SUSPEND; 733 goto b_host; 734 } else 735 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 736 break; 737 case OTG_STATE_B_WAIT_ACON: 738 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 739 b_host: 740 musb->xceiv->state = OTG_STATE_B_HOST; 741 hcd->self.is_b_host = 1; 742 musb->ignore_disconnect = 0; 743 del_timer(&musb->otg_timer); 744 break; 745 default: 746 if ((devctl & MUSB_DEVCTL_VBUS) 747 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 748 musb->xceiv->state = OTG_STATE_A_HOST; 749 hcd->self.is_b_host = 0; 750 } 751 break; 752 } 753 754 /* poke the root hub */ 755 MUSB_HST_MODE(musb); 756 if (hcd->status_urb) 757 usb_hcd_poll_rh_status(hcd); 758 else 759 usb_hcd_resume_root_hub(hcd); 760 761 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 762 otg_state_string(musb->xceiv->state), devctl); 763 #endif 764 } 765 766 #ifndef __UBOOT__ 767 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 768 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 769 otg_state_string(musb->xceiv->state), 770 MUSB_MODE(musb), devctl); 771 handled = IRQ_HANDLED; 772 773 switch (musb->xceiv->state) { 774 case OTG_STATE_A_HOST: 775 case OTG_STATE_A_SUSPEND: 776 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 777 musb_root_disconnect(musb); 778 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 779 musb_platform_try_idle(musb, jiffies 780 + msecs_to_jiffies(musb->a_wait_bcon)); 781 break; 782 case OTG_STATE_B_HOST: 783 /* REVISIT this behaves for "real disconnect" 784 * cases; make sure the other transitions from 785 * from B_HOST act right too. The B_HOST code 786 * in hnp_stop() is currently not used... 787 */ 788 musb_root_disconnect(musb); 789 musb_to_hcd(musb)->self.is_b_host = 0; 790 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 791 MUSB_DEV_MODE(musb); 792 musb_g_disconnect(musb); 793 break; 794 case OTG_STATE_A_PERIPHERAL: 795 musb_hnp_stop(musb); 796 musb_root_disconnect(musb); 797 /* FALLTHROUGH */ 798 case OTG_STATE_B_WAIT_ACON: 799 /* FALLTHROUGH */ 800 case OTG_STATE_B_PERIPHERAL: 801 case OTG_STATE_B_IDLE: 802 musb_g_disconnect(musb); 803 break; 804 default: 805 WARNING("unhandled DISCONNECT transition (%s)\n", 806 otg_state_string(musb->xceiv->state)); 807 break; 808 } 809 } 810 811 /* mentor saves a bit: bus reset and babble share the same irq. 812 * only host sees babble; only peripheral sees bus reset. 813 */ 814 if (int_usb & MUSB_INTR_RESET) { 815 handled = IRQ_HANDLED; 816 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 817 /* 818 * Looks like non-HS BABBLE can be ignored, but 819 * HS BABBLE is an error condition. For HS the solution 820 * is to avoid babble in the first place and fix what 821 * caused BABBLE. When HS BABBLE happens we can only 822 * stop the session. 823 */ 824 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 825 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 826 else { 827 ERR("Stopping host session -- babble\n"); 828 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 829 } 830 } else if (is_peripheral_capable()) { 831 dev_dbg(musb->controller, "BUS RESET as %s\n", 832 otg_state_string(musb->xceiv->state)); 833 switch (musb->xceiv->state) { 834 case OTG_STATE_A_SUSPEND: 835 /* We need to ignore disconnect on suspend 836 * otherwise tusb 2.0 won't reconnect after a 837 * power cycle, which breaks otg compliance. 838 */ 839 musb->ignore_disconnect = 1; 840 musb_g_reset(musb); 841 /* FALLTHROUGH */ 842 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 843 /* never use invalid T(a_wait_bcon) */ 844 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 845 otg_state_string(musb->xceiv->state), 846 TA_WAIT_BCON(musb)); 847 mod_timer(&musb->otg_timer, jiffies 848 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 849 break; 850 case OTG_STATE_A_PERIPHERAL: 851 musb->ignore_disconnect = 0; 852 del_timer(&musb->otg_timer); 853 musb_g_reset(musb); 854 break; 855 case OTG_STATE_B_WAIT_ACON: 856 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 857 otg_state_string(musb->xceiv->state)); 858 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 859 musb_g_reset(musb); 860 break; 861 case OTG_STATE_B_IDLE: 862 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 863 /* FALLTHROUGH */ 864 case OTG_STATE_B_PERIPHERAL: 865 musb_g_reset(musb); 866 break; 867 default: 868 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 869 otg_state_string(musb->xceiv->state)); 870 } 871 } 872 } 873 #endif 874 875 #if 0 876 /* REVISIT ... this would be for multiplexing periodic endpoints, or 877 * supporting transfer phasing to prevent exceeding ISO bandwidth 878 * limits of a given frame or microframe. 879 * 880 * It's not needed for peripheral side, which dedicates endpoints; 881 * though it _might_ use SOF irqs for other purposes. 882 * 883 * And it's not currently needed for host side, which also dedicates 884 * endpoints, relies on TX/RX interval registers, and isn't claimed 885 * to support ISO transfers yet. 886 */ 887 if (int_usb & MUSB_INTR_SOF) { 888 void __iomem *mbase = musb->mregs; 889 struct musb_hw_ep *ep; 890 u8 epnum; 891 u16 frame; 892 893 dev_dbg(musb->controller, "START_OF_FRAME\n"); 894 handled = IRQ_HANDLED; 895 896 /* start any periodic Tx transfers waiting for current frame */ 897 frame = musb_readw(mbase, MUSB_FRAME); 898 ep = musb->endpoints; 899 for (epnum = 1; (epnum < musb->nr_endpoints) 900 && (musb->epmask >= (1 << epnum)); 901 epnum++, ep++) { 902 /* 903 * FIXME handle framecounter wraps (12 bits) 904 * eliminate duplicated StartUrb logic 905 */ 906 if (ep->dwWaitFrame >= frame) { 907 ep->dwWaitFrame = 0; 908 pr_debug("SOF --> periodic TX%s on %d\n", 909 ep->tx_channel ? " DMA" : "", 910 epnum); 911 if (!ep->tx_channel) 912 musb_h_tx_start(musb, epnum); 913 else 914 cppi_hostdma_start(musb, epnum); 915 } 916 } /* end of for loop */ 917 } 918 #endif 919 920 schedule_work(&musb->irq_work); 921 922 return handled; 923 } 924 925 /*-------------------------------------------------------------------------*/ 926 927 /* 928 * Program the HDRC to start (enable interrupts, dma, etc.). 929 */ 930 void musb_start(struct musb *musb) 931 { 932 void __iomem *regs = musb->mregs; 933 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 934 935 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 936 937 /* Set INT enable registers, enable interrupts */ 938 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 939 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 940 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 941 942 musb_writeb(regs, MUSB_TESTMODE, 0); 943 944 /* put into basic highspeed mode and start session */ 945 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 946 | MUSB_POWER_HSENAB 947 /* ENSUSPEND wedges tusb */ 948 /* | MUSB_POWER_ENSUSPEND */ 949 ); 950 951 musb->is_active = 0; 952 devctl = musb_readb(regs, MUSB_DEVCTL); 953 devctl &= ~MUSB_DEVCTL_SESSION; 954 955 if (is_otg_enabled(musb)) { 956 #ifndef __UBOOT__ 957 /* session started after: 958 * (a) ID-grounded irq, host mode; 959 * (b) vbus present/connect IRQ, peripheral mode; 960 * (c) peripheral initiates, using SRP 961 */ 962 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 963 musb->is_active = 1; 964 else 965 devctl |= MUSB_DEVCTL_SESSION; 966 #endif 967 968 } else if (is_host_enabled(musb)) { 969 /* assume ID pin is hard-wired to ground */ 970 devctl |= MUSB_DEVCTL_SESSION; 971 972 } else /* peripheral is enabled */ { 973 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 974 musb->is_active = 1; 975 } 976 musb_platform_enable(musb); 977 musb_writeb(regs, MUSB_DEVCTL, devctl); 978 } 979 980 981 static void musb_generic_disable(struct musb *musb) 982 { 983 void __iomem *mbase = musb->mregs; 984 u16 temp; 985 986 /* disable interrupts */ 987 musb_writeb(mbase, MUSB_INTRUSBE, 0); 988 musb_writew(mbase, MUSB_INTRTXE, 0); 989 musb_writew(mbase, MUSB_INTRRXE, 0); 990 991 /* off */ 992 musb_writeb(mbase, MUSB_DEVCTL, 0); 993 994 /* flush pending interrupts */ 995 temp = musb_readb(mbase, MUSB_INTRUSB); 996 temp = musb_readw(mbase, MUSB_INTRTX); 997 temp = musb_readw(mbase, MUSB_INTRRX); 998 999 } 1000 1001 /* 1002 * Make the HDRC stop (disable interrupts, etc.); 1003 * reversible by musb_start 1004 * called on gadget driver unregister 1005 * with controller locked, irqs blocked 1006 * acts as a NOP unless some role activated the hardware 1007 */ 1008 void musb_stop(struct musb *musb) 1009 { 1010 /* stop IRQs, timers, ... */ 1011 musb_platform_disable(musb); 1012 musb_generic_disable(musb); 1013 dev_dbg(musb->controller, "HDRC disabled\n"); 1014 1015 /* FIXME 1016 * - mark host and/or peripheral drivers unusable/inactive 1017 * - disable DMA (and enable it in HdrcStart) 1018 * - make sure we can musb_start() after musb_stop(); with 1019 * OTG mode, gadget driver module rmmod/modprobe cycles that 1020 * - ... 1021 */ 1022 musb_platform_try_idle(musb, 0); 1023 } 1024 1025 #ifndef __UBOOT__ 1026 static void musb_shutdown(struct platform_device *pdev) 1027 { 1028 struct musb *musb = dev_to_musb(&pdev->dev); 1029 unsigned long flags; 1030 1031 pm_runtime_get_sync(musb->controller); 1032 1033 musb_gadget_cleanup(musb); 1034 1035 spin_lock_irqsave(&musb->lock, flags); 1036 musb_platform_disable(musb); 1037 musb_generic_disable(musb); 1038 spin_unlock_irqrestore(&musb->lock, flags); 1039 1040 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1041 usb_remove_hcd(musb_to_hcd(musb)); 1042 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1043 musb_platform_exit(musb); 1044 1045 pm_runtime_put(musb->controller); 1046 /* FIXME power down */ 1047 } 1048 #endif 1049 1050 1051 /*-------------------------------------------------------------------------*/ 1052 1053 /* 1054 * The silicon either has hard-wired endpoint configurations, or else 1055 * "dynamic fifo" sizing. The driver has support for both, though at this 1056 * writing only the dynamic sizing is very well tested. Since we switched 1057 * away from compile-time hardware parameters, we can no longer rely on 1058 * dead code elimination to leave only the relevant one in the object file. 1059 * 1060 * We don't currently use dynamic fifo setup capability to do anything 1061 * more than selecting one of a bunch of predefined configurations. 1062 */ 1063 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1064 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1065 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1066 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1067 || defined(CONFIG_USB_MUSB_AM35X) \ 1068 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1069 || defined(CONFIG_USB_MUSB_DSPS) \ 1070 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1071 static ushort __devinitdata fifo_mode = 4; 1072 #elif defined(CONFIG_USB_MUSB_UX500) \ 1073 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1074 static ushort __devinitdata fifo_mode = 5; 1075 #else 1076 static ushort __devinitdata fifo_mode = 2; 1077 #endif 1078 1079 /* "modprobe ... fifo_mode=1" etc */ 1080 module_param(fifo_mode, ushort, 0); 1081 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1082 1083 /* 1084 * tables defining fifo_mode values. define more if you like. 1085 * for host side, make sure both halves of ep1 are set up. 1086 */ 1087 1088 /* mode 0 - fits in 2KB */ 1089 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1090 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1091 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1092 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1093 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1094 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1095 }; 1096 1097 /* mode 1 - fits in 4KB */ 1098 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1101 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1102 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1103 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1104 }; 1105 1106 /* mode 2 - fits in 4KB */ 1107 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1108 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1109 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1110 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1111 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1112 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1113 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1114 }; 1115 1116 /* mode 3 - fits in 4KB */ 1117 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1118 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1119 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1120 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1121 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1122 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1123 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1124 }; 1125 1126 /* mode 4 - fits in 16KB */ 1127 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1128 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1129 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1130 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1131 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1132 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1133 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1134 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1135 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1136 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1137 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1138 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1139 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1140 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1141 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1142 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1143 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1144 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1145 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1146 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1147 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1148 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1149 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1150 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1151 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1152 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1153 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1154 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1155 }; 1156 1157 /* mode 5 - fits in 8KB */ 1158 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1159 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1160 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1161 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1162 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1163 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1164 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1165 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1166 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1167 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1168 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1169 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1170 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1171 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1172 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1173 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1174 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1175 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1176 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1177 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1178 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1179 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1180 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1181 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1182 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1183 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1184 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1185 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1186 }; 1187 1188 /* 1189 * configure a fifo; for non-shared endpoints, this may be called 1190 * once for a tx fifo and once for an rx fifo. 1191 * 1192 * returns negative errno or offset for next fifo. 1193 */ 1194 static int __devinit 1195 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1196 const struct musb_fifo_cfg *cfg, u16 offset) 1197 { 1198 void __iomem *mbase = musb->mregs; 1199 int size = 0; 1200 u16 maxpacket = cfg->maxpacket; 1201 u16 c_off = offset >> 3; 1202 u8 c_size; 1203 1204 /* expect hw_ep has already been zero-initialized */ 1205 1206 size = ffs(max(maxpacket, (u16) 8)) - 1; 1207 maxpacket = 1 << size; 1208 1209 c_size = size - 3; 1210 if (cfg->mode == BUF_DOUBLE) { 1211 if ((offset + (maxpacket << 1)) > 1212 (1 << (musb->config->ram_bits + 2))) 1213 return -EMSGSIZE; 1214 c_size |= MUSB_FIFOSZ_DPB; 1215 } else { 1216 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1217 return -EMSGSIZE; 1218 } 1219 1220 /* configure the FIFO */ 1221 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1222 1223 /* EP0 reserved endpoint for control, bidirectional; 1224 * EP1 reserved for bulk, two unidirection halves. 1225 */ 1226 if (hw_ep->epnum == 1) 1227 musb->bulk_ep = hw_ep; 1228 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1229 switch (cfg->style) { 1230 case FIFO_TX: 1231 musb_write_txfifosz(mbase, c_size); 1232 musb_write_txfifoadd(mbase, c_off); 1233 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1234 hw_ep->max_packet_sz_tx = maxpacket; 1235 break; 1236 case FIFO_RX: 1237 musb_write_rxfifosz(mbase, c_size); 1238 musb_write_rxfifoadd(mbase, c_off); 1239 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1240 hw_ep->max_packet_sz_rx = maxpacket; 1241 break; 1242 case FIFO_RXTX: 1243 musb_write_txfifosz(mbase, c_size); 1244 musb_write_txfifoadd(mbase, c_off); 1245 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1246 hw_ep->max_packet_sz_rx = maxpacket; 1247 1248 musb_write_rxfifosz(mbase, c_size); 1249 musb_write_rxfifoadd(mbase, c_off); 1250 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1251 hw_ep->max_packet_sz_tx = maxpacket; 1252 1253 hw_ep->is_shared_fifo = true; 1254 break; 1255 } 1256 1257 /* NOTE rx and tx endpoint irqs aren't managed separately, 1258 * which happens to be ok 1259 */ 1260 musb->epmask |= (1 << hw_ep->epnum); 1261 1262 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1263 } 1264 1265 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1266 .style = FIFO_RXTX, .maxpacket = 64, 1267 }; 1268 1269 static int __devinit ep_config_from_table(struct musb *musb) 1270 { 1271 const struct musb_fifo_cfg *cfg; 1272 unsigned i, n; 1273 int offset; 1274 struct musb_hw_ep *hw_ep = musb->endpoints; 1275 1276 if (musb->config->fifo_cfg) { 1277 cfg = musb->config->fifo_cfg; 1278 n = musb->config->fifo_cfg_size; 1279 goto done; 1280 } 1281 1282 switch (fifo_mode) { 1283 default: 1284 fifo_mode = 0; 1285 /* FALLTHROUGH */ 1286 case 0: 1287 cfg = mode_0_cfg; 1288 n = ARRAY_SIZE(mode_0_cfg); 1289 break; 1290 case 1: 1291 cfg = mode_1_cfg; 1292 n = ARRAY_SIZE(mode_1_cfg); 1293 break; 1294 case 2: 1295 cfg = mode_2_cfg; 1296 n = ARRAY_SIZE(mode_2_cfg); 1297 break; 1298 case 3: 1299 cfg = mode_3_cfg; 1300 n = ARRAY_SIZE(mode_3_cfg); 1301 break; 1302 case 4: 1303 cfg = mode_4_cfg; 1304 n = ARRAY_SIZE(mode_4_cfg); 1305 break; 1306 case 5: 1307 cfg = mode_5_cfg; 1308 n = ARRAY_SIZE(mode_5_cfg); 1309 break; 1310 } 1311 1312 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1313 musb_driver_name, fifo_mode); 1314 1315 1316 done: 1317 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1318 /* assert(offset > 0) */ 1319 1320 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1321 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1322 */ 1323 1324 for (i = 0; i < n; i++) { 1325 u8 epn = cfg->hw_ep_num; 1326 1327 if (epn >= musb->config->num_eps) { 1328 pr_debug("%s: invalid ep %d\n", 1329 musb_driver_name, epn); 1330 return -EINVAL; 1331 } 1332 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1333 if (offset < 0) { 1334 pr_debug("%s: mem overrun, ep %d\n", 1335 musb_driver_name, epn); 1336 return -EINVAL; 1337 } 1338 epn++; 1339 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1340 } 1341 1342 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1343 musb_driver_name, 1344 n + 1, musb->config->num_eps * 2 - 1, 1345 offset, (1 << (musb->config->ram_bits + 2))); 1346 1347 if (!musb->bulk_ep) { 1348 pr_debug("%s: missing bulk\n", musb_driver_name); 1349 return -EINVAL; 1350 } 1351 1352 return 0; 1353 } 1354 1355 1356 /* 1357 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1358 * @param musb the controller 1359 */ 1360 static int __devinit ep_config_from_hw(struct musb *musb) 1361 { 1362 u8 epnum = 0; 1363 struct musb_hw_ep *hw_ep; 1364 void *mbase = musb->mregs; 1365 int ret = 0; 1366 1367 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1368 1369 /* FIXME pick up ep0 maxpacket size */ 1370 1371 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1372 musb_ep_select(mbase, epnum); 1373 hw_ep = musb->endpoints + epnum; 1374 1375 ret = musb_read_fifosize(musb, hw_ep, epnum); 1376 if (ret < 0) 1377 break; 1378 1379 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1380 1381 /* pick an RX/TX endpoint for bulk */ 1382 if (hw_ep->max_packet_sz_tx < 512 1383 || hw_ep->max_packet_sz_rx < 512) 1384 continue; 1385 1386 /* REVISIT: this algorithm is lazy, we should at least 1387 * try to pick a double buffered endpoint. 1388 */ 1389 if (musb->bulk_ep) 1390 continue; 1391 musb->bulk_ep = hw_ep; 1392 } 1393 1394 if (!musb->bulk_ep) { 1395 pr_debug("%s: missing bulk\n", musb_driver_name); 1396 return -EINVAL; 1397 } 1398 1399 return 0; 1400 } 1401 1402 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1403 1404 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1405 * configure endpoints, or take their config from silicon 1406 */ 1407 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1408 { 1409 u8 reg; 1410 char *type; 1411 char aInfo[90], aRevision[32], aDate[12]; 1412 void __iomem *mbase = musb->mregs; 1413 int status = 0; 1414 int i; 1415 1416 /* log core options (read using indexed model) */ 1417 reg = musb_read_configdata(mbase); 1418 1419 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1420 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1421 strcat(aInfo, ", dyn FIFOs"); 1422 musb->dyn_fifo = true; 1423 } 1424 if (reg & MUSB_CONFIGDATA_MPRXE) { 1425 strcat(aInfo, ", bulk combine"); 1426 musb->bulk_combine = true; 1427 } 1428 if (reg & MUSB_CONFIGDATA_MPTXE) { 1429 strcat(aInfo, ", bulk split"); 1430 musb->bulk_split = true; 1431 } 1432 if (reg & MUSB_CONFIGDATA_HBRXE) { 1433 strcat(aInfo, ", HB-ISO Rx"); 1434 musb->hb_iso_rx = true; 1435 } 1436 if (reg & MUSB_CONFIGDATA_HBTXE) { 1437 strcat(aInfo, ", HB-ISO Tx"); 1438 musb->hb_iso_tx = true; 1439 } 1440 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1441 strcat(aInfo, ", SoftConn"); 1442 1443 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1444 musb_driver_name, reg, aInfo); 1445 1446 aDate[0] = 0; 1447 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1448 musb->is_multipoint = 1; 1449 type = "M"; 1450 } else { 1451 musb->is_multipoint = 0; 1452 type = ""; 1453 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1454 printk(KERN_ERR 1455 "%s: kernel must blacklist external hubs\n", 1456 musb_driver_name); 1457 #endif 1458 } 1459 1460 /* log release info */ 1461 musb->hwvers = musb_read_hwvers(mbase); 1462 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1463 MUSB_HWVERS_MINOR(musb->hwvers), 1464 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1465 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1466 musb_driver_name, type, aRevision, aDate); 1467 1468 /* configure ep0 */ 1469 musb_configure_ep0(musb); 1470 1471 /* discover endpoint configuration */ 1472 musb->nr_endpoints = 1; 1473 musb->epmask = 1; 1474 1475 if (musb->dyn_fifo) 1476 status = ep_config_from_table(musb); 1477 else 1478 status = ep_config_from_hw(musb); 1479 1480 if (status < 0) 1481 return status; 1482 1483 /* finish init, and print endpoint config */ 1484 for (i = 0; i < musb->nr_endpoints; i++) { 1485 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1486 1487 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1488 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1489 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1490 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1491 hw_ep->fifo_sync_va = 1492 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1493 1494 if (i == 0) 1495 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1496 else 1497 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1498 #endif 1499 1500 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1501 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1502 hw_ep->rx_reinit = 1; 1503 hw_ep->tx_reinit = 1; 1504 1505 if (hw_ep->max_packet_sz_tx) { 1506 dev_dbg(musb->controller, 1507 "%s: hw_ep %d%s, %smax %d\n", 1508 musb_driver_name, i, 1509 hw_ep->is_shared_fifo ? "shared" : "tx", 1510 hw_ep->tx_double_buffered 1511 ? "doublebuffer, " : "", 1512 hw_ep->max_packet_sz_tx); 1513 } 1514 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1515 dev_dbg(musb->controller, 1516 "%s: hw_ep %d%s, %smax %d\n", 1517 musb_driver_name, i, 1518 "rx", 1519 hw_ep->rx_double_buffered 1520 ? "doublebuffer, " : "", 1521 hw_ep->max_packet_sz_rx); 1522 } 1523 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1524 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1525 } 1526 1527 return 0; 1528 } 1529 1530 /*-------------------------------------------------------------------------*/ 1531 1532 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1533 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1534 1535 static irqreturn_t generic_interrupt(int irq, void *__hci) 1536 { 1537 unsigned long flags; 1538 irqreturn_t retval = IRQ_NONE; 1539 struct musb *musb = __hci; 1540 1541 spin_lock_irqsave(&musb->lock, flags); 1542 1543 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1544 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1545 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1546 1547 if (musb->int_usb || musb->int_tx || musb->int_rx) 1548 retval = musb_interrupt(musb); 1549 1550 spin_unlock_irqrestore(&musb->lock, flags); 1551 1552 return retval; 1553 } 1554 1555 #else 1556 #define generic_interrupt NULL 1557 #endif 1558 1559 /* 1560 * handle all the irqs defined by the HDRC core. for now we expect: other 1561 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1562 * will be assigned, and the irq will already have been acked. 1563 * 1564 * called in irq context with spinlock held, irqs blocked 1565 */ 1566 irqreturn_t musb_interrupt(struct musb *musb) 1567 { 1568 irqreturn_t retval = IRQ_NONE; 1569 u8 devctl, power; 1570 int ep_num; 1571 u32 reg; 1572 1573 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1574 power = musb_readb(musb->mregs, MUSB_POWER); 1575 1576 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1577 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1578 musb->int_usb, musb->int_tx, musb->int_rx); 1579 1580 /* the core can interrupt us for multiple reasons; docs have 1581 * a generic interrupt flowchart to follow 1582 */ 1583 if (musb->int_usb) 1584 retval |= musb_stage0_irq(musb, musb->int_usb, 1585 devctl, power); 1586 1587 /* "stage 1" is handling endpoint irqs */ 1588 1589 /* handle endpoint 0 first */ 1590 if (musb->int_tx & 1) { 1591 if (devctl & MUSB_DEVCTL_HM) { 1592 if (is_host_capable()) 1593 retval |= musb_h_ep0_irq(musb); 1594 } else { 1595 if (is_peripheral_capable()) 1596 retval |= musb_g_ep0_irq(musb); 1597 } 1598 } 1599 1600 /* RX on endpoints 1-15 */ 1601 reg = musb->int_rx >> 1; 1602 ep_num = 1; 1603 while (reg) { 1604 if (reg & 1) { 1605 /* musb_ep_select(musb->mregs, ep_num); */ 1606 /* REVISIT just retval = ep->rx_irq(...) */ 1607 retval = IRQ_HANDLED; 1608 if (devctl & MUSB_DEVCTL_HM) { 1609 if (is_host_capable()) 1610 musb_host_rx(musb, ep_num); 1611 } else { 1612 if (is_peripheral_capable()) 1613 musb_g_rx(musb, ep_num); 1614 } 1615 } 1616 1617 reg >>= 1; 1618 ep_num++; 1619 } 1620 1621 /* TX on endpoints 1-15 */ 1622 reg = musb->int_tx >> 1; 1623 ep_num = 1; 1624 while (reg) { 1625 if (reg & 1) { 1626 /* musb_ep_select(musb->mregs, ep_num); */ 1627 /* REVISIT just retval |= ep->tx_irq(...) */ 1628 retval = IRQ_HANDLED; 1629 if (devctl & MUSB_DEVCTL_HM) { 1630 if (is_host_capable()) 1631 musb_host_tx(musb, ep_num); 1632 } else { 1633 if (is_peripheral_capable()) 1634 musb_g_tx(musb, ep_num); 1635 } 1636 } 1637 reg >>= 1; 1638 ep_num++; 1639 } 1640 1641 return retval; 1642 } 1643 EXPORT_SYMBOL_GPL(musb_interrupt); 1644 1645 #ifndef CONFIG_MUSB_PIO_ONLY 1646 static bool __devinitdata use_dma = 1; 1647 1648 /* "modprobe ... use_dma=0" etc */ 1649 module_param(use_dma, bool, 0); 1650 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1651 1652 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1653 { 1654 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1655 1656 /* called with controller lock already held */ 1657 1658 if (!epnum) { 1659 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1660 if (!is_cppi_enabled()) { 1661 /* endpoint 0 */ 1662 if (devctl & MUSB_DEVCTL_HM) 1663 musb_h_ep0_irq(musb); 1664 else 1665 musb_g_ep0_irq(musb); 1666 } 1667 #endif 1668 } else { 1669 /* endpoints 1..15 */ 1670 if (transmit) { 1671 if (devctl & MUSB_DEVCTL_HM) { 1672 if (is_host_capable()) 1673 musb_host_tx(musb, epnum); 1674 } else { 1675 if (is_peripheral_capable()) 1676 musb_g_tx(musb, epnum); 1677 } 1678 } else { 1679 /* receive */ 1680 if (devctl & MUSB_DEVCTL_HM) { 1681 if (is_host_capable()) 1682 musb_host_rx(musb, epnum); 1683 } else { 1684 if (is_peripheral_capable()) 1685 musb_g_rx(musb, epnum); 1686 } 1687 } 1688 } 1689 } 1690 EXPORT_SYMBOL_GPL(musb_dma_completion); 1691 1692 #else 1693 #define use_dma 0 1694 #endif 1695 1696 /*-------------------------------------------------------------------------*/ 1697 1698 #ifdef CONFIG_SYSFS 1699 1700 static ssize_t 1701 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1702 { 1703 struct musb *musb = dev_to_musb(dev); 1704 unsigned long flags; 1705 int ret = -EINVAL; 1706 1707 spin_lock_irqsave(&musb->lock, flags); 1708 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1709 spin_unlock_irqrestore(&musb->lock, flags); 1710 1711 return ret; 1712 } 1713 1714 static ssize_t 1715 musb_mode_store(struct device *dev, struct device_attribute *attr, 1716 const char *buf, size_t n) 1717 { 1718 struct musb *musb = dev_to_musb(dev); 1719 unsigned long flags; 1720 int status; 1721 1722 spin_lock_irqsave(&musb->lock, flags); 1723 if (sysfs_streq(buf, "host")) 1724 status = musb_platform_set_mode(musb, MUSB_HOST); 1725 else if (sysfs_streq(buf, "peripheral")) 1726 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1727 else if (sysfs_streq(buf, "otg")) 1728 status = musb_platform_set_mode(musb, MUSB_OTG); 1729 else 1730 status = -EINVAL; 1731 spin_unlock_irqrestore(&musb->lock, flags); 1732 1733 return (status == 0) ? n : status; 1734 } 1735 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1736 1737 static ssize_t 1738 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1739 const char *buf, size_t n) 1740 { 1741 struct musb *musb = dev_to_musb(dev); 1742 unsigned long flags; 1743 unsigned long val; 1744 1745 if (sscanf(buf, "%lu", &val) < 1) { 1746 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1747 return -EINVAL; 1748 } 1749 1750 spin_lock_irqsave(&musb->lock, flags); 1751 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1752 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1753 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1754 musb->is_active = 0; 1755 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1756 spin_unlock_irqrestore(&musb->lock, flags); 1757 1758 return n; 1759 } 1760 1761 static ssize_t 1762 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1763 { 1764 struct musb *musb = dev_to_musb(dev); 1765 unsigned long flags; 1766 unsigned long val; 1767 int vbus; 1768 1769 spin_lock_irqsave(&musb->lock, flags); 1770 val = musb->a_wait_bcon; 1771 /* FIXME get_vbus_status() is normally #defined as false... 1772 * and is effectively TUSB-specific. 1773 */ 1774 vbus = musb_platform_get_vbus_status(musb); 1775 spin_unlock_irqrestore(&musb->lock, flags); 1776 1777 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1778 vbus ? "on" : "off", val); 1779 } 1780 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1781 1782 /* Gadget drivers can't know that a host is connected so they might want 1783 * to start SRP, but users can. This allows userspace to trigger SRP. 1784 */ 1785 static ssize_t 1786 musb_srp_store(struct device *dev, struct device_attribute *attr, 1787 const char *buf, size_t n) 1788 { 1789 struct musb *musb = dev_to_musb(dev); 1790 unsigned short srp; 1791 1792 if (sscanf(buf, "%hu", &srp) != 1 1793 || (srp != 1)) { 1794 dev_err(dev, "SRP: Value must be 1\n"); 1795 return -EINVAL; 1796 } 1797 1798 if (srp == 1) 1799 musb_g_wakeup(musb); 1800 1801 return n; 1802 } 1803 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1804 1805 static struct attribute *musb_attributes[] = { 1806 &dev_attr_mode.attr, 1807 &dev_attr_vbus.attr, 1808 &dev_attr_srp.attr, 1809 NULL 1810 }; 1811 1812 static const struct attribute_group musb_attr_group = { 1813 .attrs = musb_attributes, 1814 }; 1815 1816 #endif /* sysfs */ 1817 1818 #ifndef __UBOOT__ 1819 /* Only used to provide driver mode change events */ 1820 static void musb_irq_work(struct work_struct *data) 1821 { 1822 struct musb *musb = container_of(data, struct musb, irq_work); 1823 static int old_state; 1824 1825 if (musb->xceiv->state != old_state) { 1826 old_state = musb->xceiv->state; 1827 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1828 } 1829 } 1830 #endif 1831 1832 /* -------------------------------------------------------------------------- 1833 * Init support 1834 */ 1835 1836 static struct musb *__devinit 1837 allocate_instance(struct device *dev, 1838 struct musb_hdrc_config *config, void __iomem *mbase) 1839 { 1840 struct musb *musb; 1841 struct musb_hw_ep *ep; 1842 int epnum; 1843 #ifndef __UBOOT__ 1844 struct usb_hcd *hcd; 1845 1846 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1847 if (!hcd) 1848 return NULL; 1849 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1850 1851 musb = hcd_to_musb(hcd); 1852 #else 1853 musb = calloc(1, sizeof(*musb)); 1854 if (!musb) 1855 return NULL; 1856 #endif 1857 INIT_LIST_HEAD(&musb->control); 1858 INIT_LIST_HEAD(&musb->in_bulk); 1859 INIT_LIST_HEAD(&musb->out_bulk); 1860 1861 #ifndef __UBOOT__ 1862 hcd->uses_new_polling = 1; 1863 hcd->has_tt = 1; 1864 #endif 1865 1866 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1867 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1868 dev_set_drvdata(dev, musb); 1869 musb->mregs = mbase; 1870 musb->ctrl_base = mbase; 1871 musb->nIrq = -ENODEV; 1872 musb->config = config; 1873 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1874 for (epnum = 0, ep = musb->endpoints; 1875 epnum < musb->config->num_eps; 1876 epnum++, ep++) { 1877 ep->musb = musb; 1878 ep->epnum = epnum; 1879 } 1880 1881 musb->controller = dev; 1882 1883 return musb; 1884 } 1885 1886 static void musb_free(struct musb *musb) 1887 { 1888 /* this has multiple entry modes. it handles fault cleanup after 1889 * probe(), where things may be partially set up, as well as rmmod 1890 * cleanup after everything's been de-activated. 1891 */ 1892 1893 #ifdef CONFIG_SYSFS 1894 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1895 #endif 1896 1897 if (musb->nIrq >= 0) { 1898 if (musb->irq_wake) 1899 disable_irq_wake(musb->nIrq); 1900 free_irq(musb->nIrq, musb); 1901 } 1902 if (is_dma_capable() && musb->dma_controller) { 1903 struct dma_controller *c = musb->dma_controller; 1904 1905 (void) c->stop(c); 1906 dma_controller_destroy(c); 1907 } 1908 1909 kfree(musb); 1910 } 1911 1912 /* 1913 * Perform generic per-controller initialization. 1914 * 1915 * @pDevice: the controller (already clocked, etc) 1916 * @nIrq: irq 1917 * @mregs: virtual address of controller registers, 1918 * not yet corrected for platform-specific offsets 1919 */ 1920 #ifndef __UBOOT__ 1921 static int __devinit 1922 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1923 #else 1924 struct musb * 1925 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, 1926 void *ctrl) 1927 #endif 1928 { 1929 int status; 1930 struct musb *musb; 1931 #ifndef __UBOOT__ 1932 struct musb_hdrc_platform_data *plat = dev->platform_data; 1933 #else 1934 int nIrq = 0; 1935 #endif 1936 1937 /* The driver might handle more features than the board; OK. 1938 * Fail when the board needs a feature that's not enabled. 1939 */ 1940 if (!plat) { 1941 dev_dbg(dev, "no platform_data?\n"); 1942 status = -ENODEV; 1943 goto fail0; 1944 } 1945 1946 /* allocate */ 1947 musb = allocate_instance(dev, plat->config, ctrl); 1948 if (!musb) { 1949 status = -ENOMEM; 1950 goto fail0; 1951 } 1952 1953 pm_runtime_use_autosuspend(musb->controller); 1954 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1955 pm_runtime_enable(musb->controller); 1956 1957 spin_lock_init(&musb->lock); 1958 musb->board_mode = plat->mode; 1959 musb->board_set_power = plat->set_power; 1960 musb->min_power = plat->min_power; 1961 musb->ops = plat->platform_ops; 1962 1963 /* The musb_platform_init() call: 1964 * - adjusts musb->mregs and musb->isr if needed, 1965 * - may initialize an integrated tranceiver 1966 * - initializes musb->xceiv, usually by otg_get_phy() 1967 * - stops powering VBUS 1968 * 1969 * There are various transceiver configurations. Blackfin, 1970 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1971 * external/discrete ones in various flavors (twl4030 family, 1972 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1973 */ 1974 musb->isr = generic_interrupt; 1975 status = musb_platform_init(musb); 1976 if (status < 0) 1977 goto fail1; 1978 1979 if (!musb->isr) { 1980 status = -ENODEV; 1981 goto fail2; 1982 } 1983 1984 #ifndef __UBOOT__ 1985 if (!musb->xceiv->io_ops) { 1986 musb->xceiv->io_dev = musb->controller; 1987 musb->xceiv->io_priv = musb->mregs; 1988 musb->xceiv->io_ops = &musb_ulpi_access; 1989 } 1990 #endif 1991 1992 pm_runtime_get_sync(musb->controller); 1993 1994 #ifndef CONFIG_MUSB_PIO_ONLY 1995 if (use_dma && dev->dma_mask) { 1996 struct dma_controller *c; 1997 1998 c = dma_controller_create(musb, musb->mregs); 1999 musb->dma_controller = c; 2000 if (c) 2001 (void) c->start(c); 2002 } 2003 #endif 2004 #ifndef __UBOOT__ 2005 /* ideally this would be abstracted in platform setup */ 2006 if (!is_dma_capable() || !musb->dma_controller) 2007 dev->dma_mask = NULL; 2008 #endif 2009 2010 /* be sure interrupts are disabled before connecting ISR */ 2011 musb_platform_disable(musb); 2012 musb_generic_disable(musb); 2013 2014 /* setup musb parts of the core (especially endpoints) */ 2015 status = musb_core_init(plat->config->multipoint 2016 ? MUSB_CONTROLLER_MHDRC 2017 : MUSB_CONTROLLER_HDRC, musb); 2018 if (status < 0) 2019 goto fail3; 2020 2021 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2022 2023 /* Init IRQ workqueue before request_irq */ 2024 INIT_WORK(&musb->irq_work, musb_irq_work); 2025 2026 /* attach to the IRQ */ 2027 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2028 dev_err(dev, "request_irq %d failed!\n", nIrq); 2029 status = -ENODEV; 2030 goto fail3; 2031 } 2032 musb->nIrq = nIrq; 2033 /* FIXME this handles wakeup irqs wrong */ 2034 if (enable_irq_wake(nIrq) == 0) { 2035 musb->irq_wake = 1; 2036 device_init_wakeup(dev, 1); 2037 } else { 2038 musb->irq_wake = 0; 2039 } 2040 2041 #ifndef __UBOOT__ 2042 /* host side needs more setup */ 2043 if (is_host_enabled(musb)) { 2044 struct usb_hcd *hcd = musb_to_hcd(musb); 2045 2046 otg_set_host(musb->xceiv->otg, &hcd->self); 2047 2048 if (is_otg_enabled(musb)) 2049 hcd->self.otg_port = 1; 2050 musb->xceiv->otg->host = &hcd->self; 2051 hcd->power_budget = 2 * (plat->power ? : 250); 2052 2053 /* program PHY to use external vBus if required */ 2054 if (plat->extvbus) { 2055 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2056 busctl |= MUSB_ULPI_USE_EXTVBUS; 2057 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2058 } 2059 } 2060 #endif 2061 2062 /* For the host-only role, we can activate right away. 2063 * (We expect the ID pin to be forcibly grounded!!) 2064 * Otherwise, wait till the gadget driver hooks up. 2065 */ 2066 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2067 struct usb_hcd *hcd = musb_to_hcd(musb); 2068 2069 MUSB_HST_MODE(musb); 2070 #ifndef __UBOOT__ 2071 musb->xceiv->otg->default_a = 1; 2072 musb->xceiv->state = OTG_STATE_A_IDLE; 2073 2074 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2075 2076 hcd->self.uses_pio_for_control = 1; 2077 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2078 "HOST", status, 2079 musb_readb(musb->mregs, MUSB_DEVCTL), 2080 (musb_readb(musb->mregs, MUSB_DEVCTL) 2081 & MUSB_DEVCTL_BDEVICE 2082 ? 'B' : 'A')); 2083 #endif 2084 2085 } else /* peripheral is enabled */ { 2086 MUSB_DEV_MODE(musb); 2087 #ifndef __UBOOT__ 2088 musb->xceiv->otg->default_a = 0; 2089 musb->xceiv->state = OTG_STATE_B_IDLE; 2090 #endif 2091 2092 if (is_peripheral_capable()) 2093 status = musb_gadget_setup(musb); 2094 2095 #ifndef __UBOOT__ 2096 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2097 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2098 status, 2099 musb_readb(musb->mregs, MUSB_DEVCTL)); 2100 #endif 2101 2102 } 2103 if (status < 0) 2104 goto fail3; 2105 2106 status = musb_init_debugfs(musb); 2107 if (status < 0) 2108 goto fail4; 2109 2110 #ifdef CONFIG_SYSFS 2111 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2112 if (status) 2113 goto fail5; 2114 #endif 2115 2116 pm_runtime_put(musb->controller); 2117 2118 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2119 ({char *s; 2120 switch (musb->board_mode) { 2121 case MUSB_HOST: s = "Host"; break; 2122 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2123 default: s = "OTG"; break; 2124 }; s; }), 2125 ctrl, 2126 (is_dma_capable() && musb->dma_controller) 2127 ? "DMA" : "PIO", 2128 musb->nIrq); 2129 2130 #ifndef __UBOOT__ 2131 return 0; 2132 #else 2133 return status == 0 ? musb : NULL; 2134 #endif 2135 2136 fail5: 2137 musb_exit_debugfs(musb); 2138 2139 fail4: 2140 #ifndef __UBOOT__ 2141 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2142 usb_remove_hcd(musb_to_hcd(musb)); 2143 else 2144 #endif 2145 musb_gadget_cleanup(musb); 2146 2147 fail3: 2148 pm_runtime_put_sync(musb->controller); 2149 2150 fail2: 2151 if (musb->irq_wake) 2152 device_init_wakeup(dev, 0); 2153 musb_platform_exit(musb); 2154 2155 fail1: 2156 dev_err(musb->controller, 2157 "musb_init_controller failed with status %d\n", status); 2158 2159 musb_free(musb); 2160 2161 fail0: 2162 2163 #ifndef __UBOOT__ 2164 return status; 2165 #else 2166 return status == 0 ? musb : NULL; 2167 #endif 2168 2169 } 2170 2171 /*-------------------------------------------------------------------------*/ 2172 2173 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2174 * bridge to a platform device; this driver then suffices. 2175 */ 2176 2177 #ifndef CONFIG_MUSB_PIO_ONLY 2178 static u64 *orig_dma_mask; 2179 #endif 2180 2181 #ifndef __UBOOT__ 2182 static int __devinit musb_probe(struct platform_device *pdev) 2183 { 2184 struct device *dev = &pdev->dev; 2185 int irq = platform_get_irq_byname(pdev, "mc"); 2186 int status; 2187 struct resource *iomem; 2188 void __iomem *base; 2189 2190 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2191 if (!iomem || irq <= 0) 2192 return -ENODEV; 2193 2194 base = ioremap(iomem->start, resource_size(iomem)); 2195 if (!base) { 2196 dev_err(dev, "ioremap failed\n"); 2197 return -ENOMEM; 2198 } 2199 2200 #ifndef CONFIG_MUSB_PIO_ONLY 2201 /* clobbered by use_dma=n */ 2202 orig_dma_mask = dev->dma_mask; 2203 #endif 2204 status = musb_init_controller(dev, irq, base); 2205 if (status < 0) 2206 iounmap(base); 2207 2208 return status; 2209 } 2210 2211 static int __devexit musb_remove(struct platform_device *pdev) 2212 { 2213 struct musb *musb = dev_to_musb(&pdev->dev); 2214 void __iomem *ctrl_base = musb->ctrl_base; 2215 2216 /* this gets called on rmmod. 2217 * - Host mode: host may still be active 2218 * - Peripheral mode: peripheral is deactivated (or never-activated) 2219 * - OTG mode: both roles are deactivated (or never-activated) 2220 */ 2221 musb_exit_debugfs(musb); 2222 musb_shutdown(pdev); 2223 2224 musb_free(musb); 2225 iounmap(ctrl_base); 2226 device_init_wakeup(&pdev->dev, 0); 2227 #ifndef CONFIG_MUSB_PIO_ONLY 2228 pdev->dev.dma_mask = orig_dma_mask; 2229 #endif 2230 return 0; 2231 } 2232 2233 #ifdef CONFIG_PM 2234 2235 static void musb_save_context(struct musb *musb) 2236 { 2237 int i; 2238 void __iomem *musb_base = musb->mregs; 2239 void __iomem *epio; 2240 2241 if (is_host_enabled(musb)) { 2242 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2243 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2244 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2245 } 2246 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2247 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2248 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2249 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2250 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2251 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2252 2253 for (i = 0; i < musb->config->num_eps; ++i) { 2254 struct musb_hw_ep *hw_ep; 2255 2256 hw_ep = &musb->endpoints[i]; 2257 if (!hw_ep) 2258 continue; 2259 2260 epio = hw_ep->regs; 2261 if (!epio) 2262 continue; 2263 2264 musb_writeb(musb_base, MUSB_INDEX, i); 2265 musb->context.index_regs[i].txmaxp = 2266 musb_readw(epio, MUSB_TXMAXP); 2267 musb->context.index_regs[i].txcsr = 2268 musb_readw(epio, MUSB_TXCSR); 2269 musb->context.index_regs[i].rxmaxp = 2270 musb_readw(epio, MUSB_RXMAXP); 2271 musb->context.index_regs[i].rxcsr = 2272 musb_readw(epio, MUSB_RXCSR); 2273 2274 if (musb->dyn_fifo) { 2275 musb->context.index_regs[i].txfifoadd = 2276 musb_read_txfifoadd(musb_base); 2277 musb->context.index_regs[i].rxfifoadd = 2278 musb_read_rxfifoadd(musb_base); 2279 musb->context.index_regs[i].txfifosz = 2280 musb_read_txfifosz(musb_base); 2281 musb->context.index_regs[i].rxfifosz = 2282 musb_read_rxfifosz(musb_base); 2283 } 2284 if (is_host_enabled(musb)) { 2285 musb->context.index_regs[i].txtype = 2286 musb_readb(epio, MUSB_TXTYPE); 2287 musb->context.index_regs[i].txinterval = 2288 musb_readb(epio, MUSB_TXINTERVAL); 2289 musb->context.index_regs[i].rxtype = 2290 musb_readb(epio, MUSB_RXTYPE); 2291 musb->context.index_regs[i].rxinterval = 2292 musb_readb(epio, MUSB_RXINTERVAL); 2293 2294 musb->context.index_regs[i].txfunaddr = 2295 musb_read_txfunaddr(musb_base, i); 2296 musb->context.index_regs[i].txhubaddr = 2297 musb_read_txhubaddr(musb_base, i); 2298 musb->context.index_regs[i].txhubport = 2299 musb_read_txhubport(musb_base, i); 2300 2301 musb->context.index_regs[i].rxfunaddr = 2302 musb_read_rxfunaddr(musb_base, i); 2303 musb->context.index_regs[i].rxhubaddr = 2304 musb_read_rxhubaddr(musb_base, i); 2305 musb->context.index_regs[i].rxhubport = 2306 musb_read_rxhubport(musb_base, i); 2307 } 2308 } 2309 } 2310 2311 static void musb_restore_context(struct musb *musb) 2312 { 2313 int i; 2314 void __iomem *musb_base = musb->mregs; 2315 void __iomem *ep_target_regs; 2316 void __iomem *epio; 2317 2318 if (is_host_enabled(musb)) { 2319 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2320 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2321 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2322 } 2323 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2324 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2325 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2326 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2327 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2328 2329 for (i = 0; i < musb->config->num_eps; ++i) { 2330 struct musb_hw_ep *hw_ep; 2331 2332 hw_ep = &musb->endpoints[i]; 2333 if (!hw_ep) 2334 continue; 2335 2336 epio = hw_ep->regs; 2337 if (!epio) 2338 continue; 2339 2340 musb_writeb(musb_base, MUSB_INDEX, i); 2341 musb_writew(epio, MUSB_TXMAXP, 2342 musb->context.index_regs[i].txmaxp); 2343 musb_writew(epio, MUSB_TXCSR, 2344 musb->context.index_regs[i].txcsr); 2345 musb_writew(epio, MUSB_RXMAXP, 2346 musb->context.index_regs[i].rxmaxp); 2347 musb_writew(epio, MUSB_RXCSR, 2348 musb->context.index_regs[i].rxcsr); 2349 2350 if (musb->dyn_fifo) { 2351 musb_write_txfifosz(musb_base, 2352 musb->context.index_regs[i].txfifosz); 2353 musb_write_rxfifosz(musb_base, 2354 musb->context.index_regs[i].rxfifosz); 2355 musb_write_txfifoadd(musb_base, 2356 musb->context.index_regs[i].txfifoadd); 2357 musb_write_rxfifoadd(musb_base, 2358 musb->context.index_regs[i].rxfifoadd); 2359 } 2360 2361 if (is_host_enabled(musb)) { 2362 musb_writeb(epio, MUSB_TXTYPE, 2363 musb->context.index_regs[i].txtype); 2364 musb_writeb(epio, MUSB_TXINTERVAL, 2365 musb->context.index_regs[i].txinterval); 2366 musb_writeb(epio, MUSB_RXTYPE, 2367 musb->context.index_regs[i].rxtype); 2368 musb_writeb(epio, MUSB_RXINTERVAL, 2369 2370 musb->context.index_regs[i].rxinterval); 2371 musb_write_txfunaddr(musb_base, i, 2372 musb->context.index_regs[i].txfunaddr); 2373 musb_write_txhubaddr(musb_base, i, 2374 musb->context.index_regs[i].txhubaddr); 2375 musb_write_txhubport(musb_base, i, 2376 musb->context.index_regs[i].txhubport); 2377 2378 ep_target_regs = 2379 musb_read_target_reg_base(i, musb_base); 2380 2381 musb_write_rxfunaddr(ep_target_regs, 2382 musb->context.index_regs[i].rxfunaddr); 2383 musb_write_rxhubaddr(ep_target_regs, 2384 musb->context.index_regs[i].rxhubaddr); 2385 musb_write_rxhubport(ep_target_regs, 2386 musb->context.index_regs[i].rxhubport); 2387 } 2388 } 2389 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2390 } 2391 2392 static int musb_suspend(struct device *dev) 2393 { 2394 struct musb *musb = dev_to_musb(dev); 2395 unsigned long flags; 2396 2397 spin_lock_irqsave(&musb->lock, flags); 2398 2399 if (is_peripheral_active(musb)) { 2400 /* FIXME force disconnect unless we know USB will wake 2401 * the system up quickly enough to respond ... 2402 */ 2403 } else if (is_host_active(musb)) { 2404 /* we know all the children are suspended; sometimes 2405 * they will even be wakeup-enabled. 2406 */ 2407 } 2408 2409 spin_unlock_irqrestore(&musb->lock, flags); 2410 return 0; 2411 } 2412 2413 static int musb_resume_noirq(struct device *dev) 2414 { 2415 /* for static cmos like DaVinci, register values were preserved 2416 * unless for some reason the whole soc powered down or the USB 2417 * module got reset through the PSC (vs just being disabled). 2418 */ 2419 return 0; 2420 } 2421 2422 static int musb_runtime_suspend(struct device *dev) 2423 { 2424 struct musb *musb = dev_to_musb(dev); 2425 2426 musb_save_context(musb); 2427 2428 return 0; 2429 } 2430 2431 static int musb_runtime_resume(struct device *dev) 2432 { 2433 struct musb *musb = dev_to_musb(dev); 2434 static int first = 1; 2435 2436 /* 2437 * When pm_runtime_get_sync called for the first time in driver 2438 * init, some of the structure is still not initialized which is 2439 * used in restore function. But clock needs to be 2440 * enabled before any register access, so 2441 * pm_runtime_get_sync has to be called. 2442 * Also context restore without save does not make 2443 * any sense 2444 */ 2445 if (!first) 2446 musb_restore_context(musb); 2447 first = 0; 2448 2449 return 0; 2450 } 2451 2452 static const struct dev_pm_ops musb_dev_pm_ops = { 2453 .suspend = musb_suspend, 2454 .resume_noirq = musb_resume_noirq, 2455 .runtime_suspend = musb_runtime_suspend, 2456 .runtime_resume = musb_runtime_resume, 2457 }; 2458 2459 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2460 #else 2461 #define MUSB_DEV_PM_OPS NULL 2462 #endif 2463 2464 static struct platform_driver musb_driver = { 2465 .driver = { 2466 .name = (char *)musb_driver_name, 2467 .bus = &platform_bus_type, 2468 .owner = THIS_MODULE, 2469 .pm = MUSB_DEV_PM_OPS, 2470 }, 2471 .probe = musb_probe, 2472 .remove = __devexit_p(musb_remove), 2473 .shutdown = musb_shutdown, 2474 }; 2475 2476 /*-------------------------------------------------------------------------*/ 2477 2478 static int __init musb_init(void) 2479 { 2480 if (usb_disabled()) 2481 return 0; 2482 2483 pr_info("%s: version " MUSB_VERSION ", " 2484 "?dma?" 2485 ", " 2486 "otg (peripheral+host)", 2487 musb_driver_name); 2488 return platform_driver_register(&musb_driver); 2489 } 2490 module_init(musb_init); 2491 2492 static void __exit musb_cleanup(void) 2493 { 2494 platform_driver_unregister(&musb_driver); 2495 } 2496 module_exit(musb_cleanup); 2497 #endif 2498