1 /* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 /* 12 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 13 * 14 * This consists of a Host Controller Driver (HCD) and a peripheral 15 * controller driver implementing the "Gadget" API; OTG support is 16 * in the works. These are normal Linux-USB controller drivers which 17 * use IRQs and have no dedicated thread. 18 * 19 * This version of the driver has only been used with products from 20 * Texas Instruments. Those products integrate the Inventra logic 21 * with other DMA, IRQ, and bus modules, as well as other logic that 22 * needs to be reflected in this driver. 23 * 24 * 25 * NOTE: the original Mentor code here was pretty much a collection 26 * of mechanisms that don't seem to have been fully integrated/working 27 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 28 * Key open issues include: 29 * 30 * - Lack of host-side transaction scheduling, for all transfer types. 31 * The hardware doesn't do it; instead, software must. 32 * 33 * This is not an issue for OTG devices that don't support external 34 * hubs, but for more "normal" USB hosts it's a user issue that the 35 * "multipoint" support doesn't scale in the expected ways. That 36 * includes DaVinci EVM in a common non-OTG mode. 37 * 38 * * Control and bulk use dedicated endpoints, and there's as 39 * yet no mechanism to either (a) reclaim the hardware when 40 * peripherals are NAKing, which gets complicated with bulk 41 * endpoints, or (b) use more than a single bulk endpoint in 42 * each direction. 43 * 44 * RESULT: one device may be perceived as blocking another one. 45 * 46 * * Interrupt and isochronous will dynamically allocate endpoint 47 * hardware, but (a) there's no record keeping for bandwidth; 48 * (b) in the common case that few endpoints are available, there 49 * is no mechanism to reuse endpoints to talk to multiple devices. 50 * 51 * RESULT: At one extreme, bandwidth can be overcommitted in 52 * some hardware configurations, no faults will be reported. 53 * At the other extreme, the bandwidth capabilities which do 54 * exist tend to be severely undercommitted. You can't yet hook 55 * up both a keyboard and a mouse to an external USB hub. 56 */ 57 58 /* 59 * This gets many kinds of configuration information: 60 * - Kconfig for everything user-configurable 61 * - platform_device for addressing, irq, and platform_data 62 * - platform_data is mostly for board-specific informarion 63 * (plus recentrly, SOC or family details) 64 * 65 * Most of the conditional compilation will (someday) vanish. 66 */ 67 68 #ifndef __UBOOT__ 69 #include <linux/module.h> 70 #include <linux/kernel.h> 71 #include <linux/sched.h> 72 #include <linux/slab.h> 73 #include <linux/init.h> 74 #include <linux/list.h> 75 #include <linux/kobject.h> 76 #include <linux/prefetch.h> 77 #include <linux/platform_device.h> 78 #include <linux/io.h> 79 #else 80 #include <common.h> 81 #include <usb.h> 82 #include <asm/errno.h> 83 #include <linux/usb/ch9.h> 84 #include <linux/usb/gadget.h> 85 #include <linux/usb/musb.h> 86 #include <asm/io.h> 87 #include "linux-compat.h" 88 #include "usb-compat.h" 89 #endif 90 91 #include "musb_core.h" 92 93 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 94 95 96 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 97 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 98 99 #define MUSB_VERSION "6.0" 100 101 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 102 103 #define MUSB_DRIVER_NAME "musb-hdrc" 104 const char musb_driver_name[] = MUSB_DRIVER_NAME; 105 106 MODULE_DESCRIPTION(DRIVER_INFO); 107 MODULE_AUTHOR(DRIVER_AUTHOR); 108 MODULE_LICENSE("GPL"); 109 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 110 111 112 #ifndef __UBOOT__ 113 /*-------------------------------------------------------------------------*/ 114 115 static inline struct musb *dev_to_musb(struct device *dev) 116 { 117 return dev_get_drvdata(dev); 118 } 119 #endif 120 121 /*-------------------------------------------------------------------------*/ 122 123 #ifndef __UBOOT__ 124 #ifndef CONFIG_BLACKFIN 125 static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 126 { 127 void __iomem *addr = phy->io_priv; 128 int i = 0; 129 u8 r; 130 u8 power; 131 int ret; 132 133 pm_runtime_get_sync(phy->io_dev); 134 135 /* Make sure the transceiver is not in low power mode */ 136 power = musb_readb(addr, MUSB_POWER); 137 power &= ~MUSB_POWER_SUSPENDM; 138 musb_writeb(addr, MUSB_POWER, power); 139 140 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 141 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 142 */ 143 144 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 145 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 146 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 147 148 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 149 & MUSB_ULPI_REG_CMPLT)) { 150 i++; 151 if (i == 10000) { 152 ret = -ETIMEDOUT; 153 goto out; 154 } 155 156 } 157 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 158 r &= ~MUSB_ULPI_REG_CMPLT; 159 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 160 161 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 162 163 out: 164 pm_runtime_put(phy->io_dev); 165 166 return ret; 167 } 168 169 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 170 { 171 void __iomem *addr = phy->io_priv; 172 int i = 0; 173 u8 r = 0; 174 u8 power; 175 int ret = 0; 176 177 pm_runtime_get_sync(phy->io_dev); 178 179 /* Make sure the transceiver is not in low power mode */ 180 power = musb_readb(addr, MUSB_POWER); 181 power &= ~MUSB_POWER_SUSPENDM; 182 musb_writeb(addr, MUSB_POWER, power); 183 184 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 185 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 186 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 187 188 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 189 & MUSB_ULPI_REG_CMPLT)) { 190 i++; 191 if (i == 10000) { 192 ret = -ETIMEDOUT; 193 goto out; 194 } 195 } 196 197 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 198 r &= ~MUSB_ULPI_REG_CMPLT; 199 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 200 201 out: 202 pm_runtime_put(phy->io_dev); 203 204 return ret; 205 } 206 #else 207 #define musb_ulpi_read NULL 208 #define musb_ulpi_write NULL 209 #endif 210 211 static struct usb_phy_io_ops musb_ulpi_access = { 212 .read = musb_ulpi_read, 213 .write = musb_ulpi_write, 214 }; 215 #endif 216 217 /*-------------------------------------------------------------------------*/ 218 219 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 220 221 /* 222 * Load an endpoint's FIFO 223 */ 224 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 225 { 226 struct musb *musb = hw_ep->musb; 227 void __iomem *fifo = hw_ep->fifo; 228 229 prefetch((u8 *)src); 230 231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 232 'T', hw_ep->epnum, fifo, len, src); 233 234 /* we can't assume unaligned reads work */ 235 if (likely((0x01 & (unsigned long) src) == 0)) { 236 u16 index = 0; 237 238 /* best case is 32bit-aligned source address */ 239 if ((0x02 & (unsigned long) src) == 0) { 240 if (len >= 4) { 241 writesl(fifo, src + index, len >> 2); 242 index += len & ~0x03; 243 } 244 if (len & 0x02) { 245 musb_writew(fifo, 0, *(u16 *)&src[index]); 246 index += 2; 247 } 248 } else { 249 if (len >= 2) { 250 writesw(fifo, src + index, len >> 1); 251 index += len & ~0x01; 252 } 253 } 254 if (len & 0x01) 255 musb_writeb(fifo, 0, src[index]); 256 } else { 257 /* byte aligned */ 258 writesb(fifo, src, len); 259 } 260 } 261 262 #if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32) 263 /* 264 * Unload an endpoint's FIFO 265 */ 266 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 267 { 268 struct musb *musb = hw_ep->musb; 269 void __iomem *fifo = hw_ep->fifo; 270 271 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 272 'R', hw_ep->epnum, fifo, len, dst); 273 274 /* we can't assume unaligned writes work */ 275 if (likely((0x01 & (unsigned long) dst) == 0)) { 276 u16 index = 0; 277 278 /* best case is 32bit-aligned destination address */ 279 if ((0x02 & (unsigned long) dst) == 0) { 280 if (len >= 4) { 281 readsl(fifo, dst, len >> 2); 282 index = len & ~0x03; 283 } 284 if (len & 0x02) { 285 *(u16 *)&dst[index] = musb_readw(fifo, 0); 286 index += 2; 287 } 288 } else { 289 if (len >= 2) { 290 readsw(fifo, dst, len >> 1); 291 index = len & ~0x01; 292 } 293 } 294 if (len & 0x01) 295 dst[index] = musb_readb(fifo, 0); 296 } else { 297 /* byte aligned */ 298 readsb(fifo, dst, len); 299 } 300 } 301 #endif 302 303 #endif /* normal PIO */ 304 305 306 /*-------------------------------------------------------------------------*/ 307 308 /* for high speed test mode; see USB 2.0 spec 7.1.20 */ 309 static const u8 musb_test_packet[53] = { 310 /* implicit SYNC then DATA0 to start */ 311 312 /* JKJKJKJK x9 */ 313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 314 /* JJKKJJKK x8 */ 315 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 316 /* JJJJKKKK x8 */ 317 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 318 /* JJJJJJJKKKKKKK x8 */ 319 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 320 /* JJJJJJJK x8 */ 321 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 322 /* JKKKKKKK x10, JK */ 323 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 324 325 /* implicit CRC16 then EOP to end */ 326 }; 327 328 void musb_load_testpacket(struct musb *musb) 329 { 330 void __iomem *regs = musb->endpoints[0].regs; 331 332 musb_ep_select(musb->mregs, 0); 333 musb_write_fifo(musb->control_ep, 334 sizeof(musb_test_packet), musb_test_packet); 335 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 336 } 337 338 #ifndef __UBOOT__ 339 /*-------------------------------------------------------------------------*/ 340 341 /* 342 * Handles OTG hnp timeouts, such as b_ase0_brst 343 */ 344 void musb_otg_timer_func(unsigned long data) 345 { 346 struct musb *musb = (struct musb *)data; 347 unsigned long flags; 348 349 spin_lock_irqsave(&musb->lock, flags); 350 switch (musb->xceiv->state) { 351 case OTG_STATE_B_WAIT_ACON: 352 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 353 musb_g_disconnect(musb); 354 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 355 musb->is_active = 0; 356 break; 357 case OTG_STATE_A_SUSPEND: 358 case OTG_STATE_A_WAIT_BCON: 359 dev_dbg(musb->controller, "HNP: %s timeout\n", 360 otg_state_string(musb->xceiv->state)); 361 musb_platform_set_vbus(musb, 0); 362 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 363 break; 364 default: 365 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 366 otg_state_string(musb->xceiv->state)); 367 } 368 musb->ignore_disconnect = 0; 369 spin_unlock_irqrestore(&musb->lock, flags); 370 } 371 372 /* 373 * Stops the HNP transition. Caller must take care of locking. 374 */ 375 void musb_hnp_stop(struct musb *musb) 376 { 377 struct usb_hcd *hcd = musb_to_hcd(musb); 378 void __iomem *mbase = musb->mregs; 379 u8 reg; 380 381 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 382 383 switch (musb->xceiv->state) { 384 case OTG_STATE_A_PERIPHERAL: 385 musb_g_disconnect(musb); 386 dev_dbg(musb->controller, "HNP: back to %s\n", 387 otg_state_string(musb->xceiv->state)); 388 break; 389 case OTG_STATE_B_HOST: 390 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 391 hcd->self.is_b_host = 0; 392 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 393 MUSB_DEV_MODE(musb); 394 reg = musb_readb(mbase, MUSB_POWER); 395 reg |= MUSB_POWER_SUSPENDM; 396 musb_writeb(mbase, MUSB_POWER, reg); 397 /* REVISIT: Start SESSION_REQUEST here? */ 398 break; 399 default: 400 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 401 otg_state_string(musb->xceiv->state)); 402 } 403 404 /* 405 * When returning to A state after HNP, avoid hub_port_rebounce(), 406 * which cause occasional OPT A "Did not receive reset after connect" 407 * errors. 408 */ 409 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 410 } 411 #endif 412 413 /* 414 * Interrupt Service Routine to record USB "global" interrupts. 415 * Since these do not happen often and signify things of 416 * paramount importance, it seems OK to check them individually; 417 * the order of the tests is specified in the manual 418 * 419 * @param musb instance pointer 420 * @param int_usb register contents 421 * @param devctl 422 * @param power 423 */ 424 425 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 426 u8 devctl, u8 power) 427 { 428 #ifndef __UBOOT__ 429 struct usb_otg *otg = musb->xceiv->otg; 430 #endif 431 irqreturn_t handled = IRQ_NONE; 432 433 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 434 int_usb); 435 436 #ifndef __UBOOT__ 437 /* in host mode, the peripheral may issue remote wakeup. 438 * in peripheral mode, the host may resume the link. 439 * spurious RESUME irqs happen too, paired with SUSPEND. 440 */ 441 if (int_usb & MUSB_INTR_RESUME) { 442 handled = IRQ_HANDLED; 443 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 444 445 if (devctl & MUSB_DEVCTL_HM) { 446 void __iomem *mbase = musb->mregs; 447 448 switch (musb->xceiv->state) { 449 case OTG_STATE_A_SUSPEND: 450 /* remote wakeup? later, GetPortStatus 451 * will stop RESUME signaling 452 */ 453 454 if (power & MUSB_POWER_SUSPENDM) { 455 /* spurious */ 456 musb->int_usb &= ~MUSB_INTR_SUSPEND; 457 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 458 break; 459 } 460 461 power &= ~MUSB_POWER_SUSPENDM; 462 musb_writeb(mbase, MUSB_POWER, 463 power | MUSB_POWER_RESUME); 464 465 musb->port1_status |= 466 (USB_PORT_STAT_C_SUSPEND << 16) 467 | MUSB_PORT_STAT_RESUME; 468 musb->rh_timer = jiffies 469 + msecs_to_jiffies(20); 470 471 musb->xceiv->state = OTG_STATE_A_HOST; 472 musb->is_active = 1; 473 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 474 break; 475 case OTG_STATE_B_WAIT_ACON: 476 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 477 musb->is_active = 1; 478 MUSB_DEV_MODE(musb); 479 break; 480 default: 481 WARNING("bogus %s RESUME (%s)\n", 482 "host", 483 otg_state_string(musb->xceiv->state)); 484 } 485 } else { 486 switch (musb->xceiv->state) { 487 case OTG_STATE_A_SUSPEND: 488 /* possibly DISCONNECT is upcoming */ 489 musb->xceiv->state = OTG_STATE_A_HOST; 490 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 491 break; 492 case OTG_STATE_B_WAIT_ACON: 493 case OTG_STATE_B_PERIPHERAL: 494 /* disconnect while suspended? we may 495 * not get a disconnect irq... 496 */ 497 if ((devctl & MUSB_DEVCTL_VBUS) 498 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 499 ) { 500 musb->int_usb |= MUSB_INTR_DISCONNECT; 501 musb->int_usb &= ~MUSB_INTR_SUSPEND; 502 break; 503 } 504 musb_g_resume(musb); 505 break; 506 case OTG_STATE_B_IDLE: 507 musb->int_usb &= ~MUSB_INTR_SUSPEND; 508 break; 509 default: 510 WARNING("bogus %s RESUME (%s)\n", 511 "peripheral", 512 otg_state_string(musb->xceiv->state)); 513 } 514 } 515 } 516 517 /* see manual for the order of the tests */ 518 if (int_usb & MUSB_INTR_SESSREQ) { 519 void __iomem *mbase = musb->mregs; 520 521 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 522 && (devctl & MUSB_DEVCTL_BDEVICE)) { 523 dev_dbg(musb->controller, "SessReq while on B state\n"); 524 return IRQ_HANDLED; 525 } 526 527 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 528 otg_state_string(musb->xceiv->state)); 529 530 /* IRQ arrives from ID pin sense or (later, if VBUS power 531 * is removed) SRP. responses are time critical: 532 * - turn on VBUS (with silicon-specific mechanism) 533 * - go through A_WAIT_VRISE 534 * - ... to A_WAIT_BCON. 535 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 536 */ 537 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 538 musb->ep0_stage = MUSB_EP0_START; 539 musb->xceiv->state = OTG_STATE_A_IDLE; 540 MUSB_HST_MODE(musb); 541 musb_platform_set_vbus(musb, 1); 542 543 handled = IRQ_HANDLED; 544 } 545 546 if (int_usb & MUSB_INTR_VBUSERROR) { 547 int ignore = 0; 548 549 /* During connection as an A-Device, we may see a short 550 * current spikes causing voltage drop, because of cable 551 * and peripheral capacitance combined with vbus draw. 552 * (So: less common with truly self-powered devices, where 553 * vbus doesn't act like a power supply.) 554 * 555 * Such spikes are short; usually less than ~500 usec, max 556 * of ~2 msec. That is, they're not sustained overcurrent 557 * errors, though they're reported using VBUSERROR irqs. 558 * 559 * Workarounds: (a) hardware: use self powered devices. 560 * (b) software: ignore non-repeated VBUS errors. 561 * 562 * REVISIT: do delays from lots of DEBUG_KERNEL checks 563 * make trouble here, keeping VBUS < 4.4V ? 564 */ 565 switch (musb->xceiv->state) { 566 case OTG_STATE_A_HOST: 567 /* recovery is dicey once we've gotten past the 568 * initial stages of enumeration, but if VBUS 569 * stayed ok at the other end of the link, and 570 * another reset is due (at least for high speed, 571 * to redo the chirp etc), it might work OK... 572 */ 573 case OTG_STATE_A_WAIT_BCON: 574 case OTG_STATE_A_WAIT_VRISE: 575 if (musb->vbuserr_retry) { 576 void __iomem *mbase = musb->mregs; 577 578 musb->vbuserr_retry--; 579 ignore = 1; 580 devctl |= MUSB_DEVCTL_SESSION; 581 musb_writeb(mbase, MUSB_DEVCTL, devctl); 582 } else { 583 musb->port1_status |= 584 USB_PORT_STAT_OVERCURRENT 585 | (USB_PORT_STAT_C_OVERCURRENT << 16); 586 } 587 break; 588 default: 589 break; 590 } 591 592 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 593 otg_state_string(musb->xceiv->state), 594 devctl, 595 ({ char *s; 596 switch (devctl & MUSB_DEVCTL_VBUS) { 597 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 598 s = "<SessEnd"; break; 599 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 600 s = "<AValid"; break; 601 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 602 s = "<VBusValid"; break; 603 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 604 default: 605 s = "VALID"; break; 606 }; s; }), 607 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 608 musb->port1_status); 609 610 /* go through A_WAIT_VFALL then start a new session */ 611 if (!ignore) 612 musb_platform_set_vbus(musb, 0); 613 handled = IRQ_HANDLED; 614 } 615 616 if (int_usb & MUSB_INTR_SUSPEND) { 617 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 618 otg_state_string(musb->xceiv->state), devctl, power); 619 handled = IRQ_HANDLED; 620 621 switch (musb->xceiv->state) { 622 case OTG_STATE_A_PERIPHERAL: 623 /* We also come here if the cable is removed, since 624 * this silicon doesn't report ID-no-longer-grounded. 625 * 626 * We depend on T(a_wait_bcon) to shut us down, and 627 * hope users don't do anything dicey during this 628 * undesired detour through A_WAIT_BCON. 629 */ 630 musb_hnp_stop(musb); 631 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 632 musb_root_disconnect(musb); 633 musb_platform_try_idle(musb, jiffies 634 + msecs_to_jiffies(musb->a_wait_bcon 635 ? : OTG_TIME_A_WAIT_BCON)); 636 637 break; 638 case OTG_STATE_B_IDLE: 639 if (!musb->is_active) 640 break; 641 case OTG_STATE_B_PERIPHERAL: 642 musb_g_suspend(musb); 643 musb->is_active = is_otg_enabled(musb) 644 && otg->gadget->b_hnp_enable; 645 if (musb->is_active) { 646 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 647 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 648 mod_timer(&musb->otg_timer, jiffies 649 + msecs_to_jiffies( 650 OTG_TIME_B_ASE0_BRST)); 651 } 652 break; 653 case OTG_STATE_A_WAIT_BCON: 654 if (musb->a_wait_bcon != 0) 655 musb_platform_try_idle(musb, jiffies 656 + msecs_to_jiffies(musb->a_wait_bcon)); 657 break; 658 case OTG_STATE_A_HOST: 659 musb->xceiv->state = OTG_STATE_A_SUSPEND; 660 musb->is_active = is_otg_enabled(musb) 661 && otg->host->b_hnp_enable; 662 break; 663 case OTG_STATE_B_HOST: 664 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 665 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 666 break; 667 default: 668 /* "should not happen" */ 669 musb->is_active = 0; 670 break; 671 } 672 } 673 #endif 674 675 if (int_usb & MUSB_INTR_CONNECT) { 676 struct usb_hcd *hcd = musb_to_hcd(musb); 677 678 handled = IRQ_HANDLED; 679 musb->is_active = 1; 680 681 musb->ep0_stage = MUSB_EP0_START; 682 683 /* flush endpoints when transitioning from Device Mode */ 684 if (is_peripheral_active(musb)) { 685 /* REVISIT HNP; just force disconnect */ 686 } 687 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 688 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 689 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 690 #ifndef __UBOOT__ 691 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 692 |USB_PORT_STAT_HIGH_SPEED 693 |USB_PORT_STAT_ENABLE 694 ); 695 musb->port1_status |= USB_PORT_STAT_CONNECTION 696 |(USB_PORT_STAT_C_CONNECTION << 16); 697 698 /* high vs full speed is just a guess until after reset */ 699 if (devctl & MUSB_DEVCTL_LSDEV) 700 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 701 702 /* indicate new connection to OTG machine */ 703 switch (musb->xceiv->state) { 704 case OTG_STATE_B_PERIPHERAL: 705 if (int_usb & MUSB_INTR_SUSPEND) { 706 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 707 int_usb &= ~MUSB_INTR_SUSPEND; 708 goto b_host; 709 } else 710 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 711 break; 712 case OTG_STATE_B_WAIT_ACON: 713 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 714 b_host: 715 musb->xceiv->state = OTG_STATE_B_HOST; 716 hcd->self.is_b_host = 1; 717 musb->ignore_disconnect = 0; 718 del_timer(&musb->otg_timer); 719 break; 720 default: 721 if ((devctl & MUSB_DEVCTL_VBUS) 722 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 723 musb->xceiv->state = OTG_STATE_A_HOST; 724 hcd->self.is_b_host = 0; 725 } 726 break; 727 } 728 729 /* poke the root hub */ 730 MUSB_HST_MODE(musb); 731 if (hcd->status_urb) 732 usb_hcd_poll_rh_status(hcd); 733 else 734 usb_hcd_resume_root_hub(hcd); 735 736 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 737 otg_state_string(musb->xceiv->state), devctl); 738 #endif 739 } 740 741 #ifndef __UBOOT__ 742 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 743 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 744 otg_state_string(musb->xceiv->state), 745 MUSB_MODE(musb), devctl); 746 handled = IRQ_HANDLED; 747 748 switch (musb->xceiv->state) { 749 case OTG_STATE_A_HOST: 750 case OTG_STATE_A_SUSPEND: 751 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 752 musb_root_disconnect(musb); 753 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 754 musb_platform_try_idle(musb, jiffies 755 + msecs_to_jiffies(musb->a_wait_bcon)); 756 break; 757 case OTG_STATE_B_HOST: 758 /* REVISIT this behaves for "real disconnect" 759 * cases; make sure the other transitions from 760 * from B_HOST act right too. The B_HOST code 761 * in hnp_stop() is currently not used... 762 */ 763 musb_root_disconnect(musb); 764 musb_to_hcd(musb)->self.is_b_host = 0; 765 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 766 MUSB_DEV_MODE(musb); 767 musb_g_disconnect(musb); 768 break; 769 case OTG_STATE_A_PERIPHERAL: 770 musb_hnp_stop(musb); 771 musb_root_disconnect(musb); 772 /* FALLTHROUGH */ 773 case OTG_STATE_B_WAIT_ACON: 774 /* FALLTHROUGH */ 775 case OTG_STATE_B_PERIPHERAL: 776 case OTG_STATE_B_IDLE: 777 musb_g_disconnect(musb); 778 break; 779 default: 780 WARNING("unhandled DISCONNECT transition (%s)\n", 781 otg_state_string(musb->xceiv->state)); 782 break; 783 } 784 } 785 786 /* mentor saves a bit: bus reset and babble share the same irq. 787 * only host sees babble; only peripheral sees bus reset. 788 */ 789 if (int_usb & MUSB_INTR_RESET) { 790 handled = IRQ_HANDLED; 791 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 792 /* 793 * Looks like non-HS BABBLE can be ignored, but 794 * HS BABBLE is an error condition. For HS the solution 795 * is to avoid babble in the first place and fix what 796 * caused BABBLE. When HS BABBLE happens we can only 797 * stop the session. 798 */ 799 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 800 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 801 else { 802 ERR("Stopping host session -- babble\n"); 803 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 804 } 805 } else if (is_peripheral_capable()) { 806 dev_dbg(musb->controller, "BUS RESET as %s\n", 807 otg_state_string(musb->xceiv->state)); 808 switch (musb->xceiv->state) { 809 case OTG_STATE_A_SUSPEND: 810 /* We need to ignore disconnect on suspend 811 * otherwise tusb 2.0 won't reconnect after a 812 * power cycle, which breaks otg compliance. 813 */ 814 musb->ignore_disconnect = 1; 815 musb_g_reset(musb); 816 /* FALLTHROUGH */ 817 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 818 /* never use invalid T(a_wait_bcon) */ 819 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 820 otg_state_string(musb->xceiv->state), 821 TA_WAIT_BCON(musb)); 822 mod_timer(&musb->otg_timer, jiffies 823 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 824 break; 825 case OTG_STATE_A_PERIPHERAL: 826 musb->ignore_disconnect = 0; 827 del_timer(&musb->otg_timer); 828 musb_g_reset(musb); 829 break; 830 case OTG_STATE_B_WAIT_ACON: 831 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 832 otg_state_string(musb->xceiv->state)); 833 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 834 musb_g_reset(musb); 835 break; 836 case OTG_STATE_B_IDLE: 837 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 838 /* FALLTHROUGH */ 839 case OTG_STATE_B_PERIPHERAL: 840 musb_g_reset(musb); 841 break; 842 default: 843 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 844 otg_state_string(musb->xceiv->state)); 845 } 846 } 847 } 848 #endif 849 850 #if 0 851 /* REVISIT ... this would be for multiplexing periodic endpoints, or 852 * supporting transfer phasing to prevent exceeding ISO bandwidth 853 * limits of a given frame or microframe. 854 * 855 * It's not needed for peripheral side, which dedicates endpoints; 856 * though it _might_ use SOF irqs for other purposes. 857 * 858 * And it's not currently needed for host side, which also dedicates 859 * endpoints, relies on TX/RX interval registers, and isn't claimed 860 * to support ISO transfers yet. 861 */ 862 if (int_usb & MUSB_INTR_SOF) { 863 void __iomem *mbase = musb->mregs; 864 struct musb_hw_ep *ep; 865 u8 epnum; 866 u16 frame; 867 868 dev_dbg(musb->controller, "START_OF_FRAME\n"); 869 handled = IRQ_HANDLED; 870 871 /* start any periodic Tx transfers waiting for current frame */ 872 frame = musb_readw(mbase, MUSB_FRAME); 873 ep = musb->endpoints; 874 for (epnum = 1; (epnum < musb->nr_endpoints) 875 && (musb->epmask >= (1 << epnum)); 876 epnum++, ep++) { 877 /* 878 * FIXME handle framecounter wraps (12 bits) 879 * eliminate duplicated StartUrb logic 880 */ 881 if (ep->dwWaitFrame >= frame) { 882 ep->dwWaitFrame = 0; 883 pr_debug("SOF --> periodic TX%s on %d\n", 884 ep->tx_channel ? " DMA" : "", 885 epnum); 886 if (!ep->tx_channel) 887 musb_h_tx_start(musb, epnum); 888 else 889 cppi_hostdma_start(musb, epnum); 890 } 891 } /* end of for loop */ 892 } 893 #endif 894 895 schedule_work(&musb->irq_work); 896 897 return handled; 898 } 899 900 /*-------------------------------------------------------------------------*/ 901 902 /* 903 * Program the HDRC to start (enable interrupts, dma, etc.). 904 */ 905 #ifndef __UBOOT__ 906 void musb_start(struct musb *musb) 907 #else 908 int musb_start(struct musb *musb) 909 #endif 910 { 911 void __iomem *regs = musb->mregs; 912 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 913 #ifdef __UBOOT__ 914 int ret; 915 #endif 916 917 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 918 919 /* Set INT enable registers, enable interrupts */ 920 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 921 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 922 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 923 924 musb_writeb(regs, MUSB_TESTMODE, 0); 925 926 /* put into basic highspeed mode and start session */ 927 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 928 | MUSB_POWER_HSENAB 929 /* ENSUSPEND wedges tusb */ 930 /* | MUSB_POWER_ENSUSPEND */ 931 ); 932 933 musb->is_active = 0; 934 devctl = musb_readb(regs, MUSB_DEVCTL); 935 devctl &= ~MUSB_DEVCTL_SESSION; 936 937 if (is_otg_enabled(musb)) { 938 #ifndef __UBOOT__ 939 /* session started after: 940 * (a) ID-grounded irq, host mode; 941 * (b) vbus present/connect IRQ, peripheral mode; 942 * (c) peripheral initiates, using SRP 943 */ 944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 945 musb->is_active = 1; 946 else 947 devctl |= MUSB_DEVCTL_SESSION; 948 #endif 949 950 } else if (is_host_enabled(musb)) { 951 /* assume ID pin is hard-wired to ground */ 952 devctl |= MUSB_DEVCTL_SESSION; 953 954 } else /* peripheral is enabled */ { 955 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 956 musb->is_active = 1; 957 } 958 959 #ifndef __UBOOT__ 960 musb_platform_enable(musb); 961 #else 962 ret = musb_platform_enable(musb); 963 if (ret) { 964 musb->is_active = 0; 965 return ret; 966 } 967 #endif 968 musb_writeb(regs, MUSB_DEVCTL, devctl); 969 970 #ifdef __UBOOT__ 971 return 0; 972 #endif 973 } 974 975 976 static void musb_generic_disable(struct musb *musb) 977 { 978 void __iomem *mbase = musb->mregs; 979 u16 temp; 980 981 /* disable interrupts */ 982 musb_writeb(mbase, MUSB_INTRUSBE, 0); 983 musb_writew(mbase, MUSB_INTRTXE, 0); 984 musb_writew(mbase, MUSB_INTRRXE, 0); 985 986 /* off */ 987 musb_writeb(mbase, MUSB_DEVCTL, 0); 988 989 /* flush pending interrupts */ 990 temp = musb_readb(mbase, MUSB_INTRUSB); 991 temp = musb_readw(mbase, MUSB_INTRTX); 992 temp = musb_readw(mbase, MUSB_INTRRX); 993 994 } 995 996 /* 997 * Make the HDRC stop (disable interrupts, etc.); 998 * reversible by musb_start 999 * called on gadget driver unregister 1000 * with controller locked, irqs blocked 1001 * acts as a NOP unless some role activated the hardware 1002 */ 1003 void musb_stop(struct musb *musb) 1004 { 1005 /* stop IRQs, timers, ... */ 1006 musb_platform_disable(musb); 1007 musb_generic_disable(musb); 1008 dev_dbg(musb->controller, "HDRC disabled\n"); 1009 1010 /* FIXME 1011 * - mark host and/or peripheral drivers unusable/inactive 1012 * - disable DMA (and enable it in HdrcStart) 1013 * - make sure we can musb_start() after musb_stop(); with 1014 * OTG mode, gadget driver module rmmod/modprobe cycles that 1015 * - ... 1016 */ 1017 musb_platform_try_idle(musb, 0); 1018 } 1019 1020 #ifndef __UBOOT__ 1021 static void musb_shutdown(struct platform_device *pdev) 1022 { 1023 struct musb *musb = dev_to_musb(&pdev->dev); 1024 unsigned long flags; 1025 1026 pm_runtime_get_sync(musb->controller); 1027 1028 musb_gadget_cleanup(musb); 1029 1030 spin_lock_irqsave(&musb->lock, flags); 1031 musb_platform_disable(musb); 1032 musb_generic_disable(musb); 1033 spin_unlock_irqrestore(&musb->lock, flags); 1034 1035 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1036 usb_remove_hcd(musb_to_hcd(musb)); 1037 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1038 musb_platform_exit(musb); 1039 1040 pm_runtime_put(musb->controller); 1041 /* FIXME power down */ 1042 } 1043 #endif 1044 1045 1046 /*-------------------------------------------------------------------------*/ 1047 1048 /* 1049 * The silicon either has hard-wired endpoint configurations, or else 1050 * "dynamic fifo" sizing. The driver has support for both, though at this 1051 * writing only the dynamic sizing is very well tested. Since we switched 1052 * away from compile-time hardware parameters, we can no longer rely on 1053 * dead code elimination to leave only the relevant one in the object file. 1054 * 1055 * We don't currently use dynamic fifo setup capability to do anything 1056 * more than selecting one of a bunch of predefined configurations. 1057 */ 1058 #if defined(CONFIG_USB_MUSB_TUSB6010) \ 1059 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1060 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1061 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1062 || defined(CONFIG_USB_MUSB_AM35X) \ 1063 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ 1064 || defined(CONFIG_USB_MUSB_DSPS) \ 1065 || defined(CONFIG_USB_MUSB_DSPS_MODULE) 1066 static ushort __devinitdata fifo_mode = 4; 1067 #elif defined(CONFIG_USB_MUSB_UX500) \ 1068 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1069 static ushort __devinitdata fifo_mode = 5; 1070 #else 1071 static ushort __devinitdata fifo_mode = 2; 1072 #endif 1073 1074 /* "modprobe ... fifo_mode=1" etc */ 1075 module_param(fifo_mode, ushort, 0); 1076 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1077 1078 /* 1079 * tables defining fifo_mode values. define more if you like. 1080 * for host side, make sure both halves of ep1 are set up. 1081 */ 1082 1083 /* mode 0 - fits in 2KB */ 1084 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1085 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1086 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1087 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1088 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1089 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1090 }; 1091 1092 /* mode 1 - fits in 4KB */ 1093 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1094 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1095 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1096 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1097 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1098 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1099 }; 1100 1101 /* mode 2 - fits in 4KB */ 1102 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1103 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1104 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1105 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1106 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1107 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1108 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1109 }; 1110 1111 /* mode 3 - fits in 4KB */ 1112 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1113 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1114 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1115 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1116 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1117 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1118 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1119 }; 1120 1121 /* mode 4 - fits in 16KB */ 1122 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1123 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1124 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1125 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1126 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1127 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1128 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1129 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1130 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1131 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1132 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1133 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1134 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1135 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1136 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1137 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1138 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1139 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1140 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1141 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1142 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1143 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1144 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1145 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1146 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1147 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1148 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1149 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1150 }; 1151 1152 /* mode 5 - fits in 8KB */ 1153 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1154 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1155 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1156 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1157 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1158 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1159 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1160 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1161 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1162 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1163 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1164 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1165 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1166 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1167 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1168 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1169 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1170 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1171 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1172 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1173 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1174 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1175 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1176 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1177 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1178 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1179 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1180 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1181 }; 1182 1183 /* 1184 * configure a fifo; for non-shared endpoints, this may be called 1185 * once for a tx fifo and once for an rx fifo. 1186 * 1187 * returns negative errno or offset for next fifo. 1188 */ 1189 static int __devinit 1190 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1191 const struct musb_fifo_cfg *cfg, u16 offset) 1192 { 1193 void __iomem *mbase = musb->mregs; 1194 int size = 0; 1195 u16 maxpacket = cfg->maxpacket; 1196 u16 c_off = offset >> 3; 1197 u8 c_size; 1198 1199 /* expect hw_ep has already been zero-initialized */ 1200 1201 size = ffs(max(maxpacket, (u16) 8)) - 1; 1202 maxpacket = 1 << size; 1203 1204 c_size = size - 3; 1205 if (cfg->mode == BUF_DOUBLE) { 1206 if ((offset + (maxpacket << 1)) > 1207 (1 << (musb->config->ram_bits + 2))) 1208 return -EMSGSIZE; 1209 c_size |= MUSB_FIFOSZ_DPB; 1210 } else { 1211 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1212 return -EMSGSIZE; 1213 } 1214 1215 /* configure the FIFO */ 1216 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1217 1218 /* EP0 reserved endpoint for control, bidirectional; 1219 * EP1 reserved for bulk, two unidirection halves. 1220 */ 1221 if (hw_ep->epnum == 1) 1222 musb->bulk_ep = hw_ep; 1223 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1224 switch (cfg->style) { 1225 case FIFO_TX: 1226 musb_write_txfifosz(mbase, c_size); 1227 musb_write_txfifoadd(mbase, c_off); 1228 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1229 hw_ep->max_packet_sz_tx = maxpacket; 1230 break; 1231 case FIFO_RX: 1232 musb_write_rxfifosz(mbase, c_size); 1233 musb_write_rxfifoadd(mbase, c_off); 1234 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1235 hw_ep->max_packet_sz_rx = maxpacket; 1236 break; 1237 case FIFO_RXTX: 1238 musb_write_txfifosz(mbase, c_size); 1239 musb_write_txfifoadd(mbase, c_off); 1240 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1241 hw_ep->max_packet_sz_rx = maxpacket; 1242 1243 musb_write_rxfifosz(mbase, c_size); 1244 musb_write_rxfifoadd(mbase, c_off); 1245 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1246 hw_ep->max_packet_sz_tx = maxpacket; 1247 1248 hw_ep->is_shared_fifo = true; 1249 break; 1250 } 1251 1252 /* NOTE rx and tx endpoint irqs aren't managed separately, 1253 * which happens to be ok 1254 */ 1255 musb->epmask |= (1 << hw_ep->epnum); 1256 1257 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1258 } 1259 1260 static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1261 .style = FIFO_RXTX, .maxpacket = 64, 1262 }; 1263 1264 static int __devinit ep_config_from_table(struct musb *musb) 1265 { 1266 const struct musb_fifo_cfg *cfg; 1267 unsigned i, n; 1268 int offset; 1269 struct musb_hw_ep *hw_ep = musb->endpoints; 1270 1271 if (musb->config->fifo_cfg) { 1272 cfg = musb->config->fifo_cfg; 1273 n = musb->config->fifo_cfg_size; 1274 goto done; 1275 } 1276 1277 switch (fifo_mode) { 1278 default: 1279 fifo_mode = 0; 1280 /* FALLTHROUGH */ 1281 case 0: 1282 cfg = mode_0_cfg; 1283 n = ARRAY_SIZE(mode_0_cfg); 1284 break; 1285 case 1: 1286 cfg = mode_1_cfg; 1287 n = ARRAY_SIZE(mode_1_cfg); 1288 break; 1289 case 2: 1290 cfg = mode_2_cfg; 1291 n = ARRAY_SIZE(mode_2_cfg); 1292 break; 1293 case 3: 1294 cfg = mode_3_cfg; 1295 n = ARRAY_SIZE(mode_3_cfg); 1296 break; 1297 case 4: 1298 cfg = mode_4_cfg; 1299 n = ARRAY_SIZE(mode_4_cfg); 1300 break; 1301 case 5: 1302 cfg = mode_5_cfg; 1303 n = ARRAY_SIZE(mode_5_cfg); 1304 break; 1305 } 1306 1307 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); 1308 1309 done: 1310 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1311 /* assert(offset > 0) */ 1312 1313 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1314 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1315 */ 1316 1317 for (i = 0; i < n; i++) { 1318 u8 epn = cfg->hw_ep_num; 1319 1320 if (epn >= musb->config->num_eps) { 1321 pr_debug("%s: invalid ep %d\n", 1322 musb_driver_name, epn); 1323 return -EINVAL; 1324 } 1325 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1326 if (offset < 0) { 1327 pr_debug("%s: mem overrun, ep %d\n", 1328 musb_driver_name, epn); 1329 return -EINVAL; 1330 } 1331 epn++; 1332 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1333 } 1334 1335 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1, 1336 musb->config->num_eps * 2 - 1, offset, 1337 (1 << (musb->config->ram_bits + 2))); 1338 1339 if (!musb->bulk_ep) { 1340 pr_debug("%s: missing bulk\n", musb_driver_name); 1341 return -EINVAL; 1342 } 1343 1344 return 0; 1345 } 1346 1347 1348 /* 1349 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1350 * @param musb the controller 1351 */ 1352 static int __devinit ep_config_from_hw(struct musb *musb) 1353 { 1354 u8 epnum = 0; 1355 struct musb_hw_ep *hw_ep; 1356 void *mbase = musb->mregs; 1357 int ret = 0; 1358 1359 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1360 1361 /* FIXME pick up ep0 maxpacket size */ 1362 1363 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1364 musb_ep_select(mbase, epnum); 1365 hw_ep = musb->endpoints + epnum; 1366 1367 ret = musb_read_fifosize(musb, hw_ep, epnum); 1368 if (ret < 0) 1369 break; 1370 1371 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1372 1373 /* pick an RX/TX endpoint for bulk */ 1374 if (hw_ep->max_packet_sz_tx < 512 1375 || hw_ep->max_packet_sz_rx < 512) 1376 continue; 1377 1378 /* REVISIT: this algorithm is lazy, we should at least 1379 * try to pick a double buffered endpoint. 1380 */ 1381 if (musb->bulk_ep) 1382 continue; 1383 musb->bulk_ep = hw_ep; 1384 } 1385 1386 if (!musb->bulk_ep) { 1387 pr_debug("%s: missing bulk\n", musb_driver_name); 1388 return -EINVAL; 1389 } 1390 1391 return 0; 1392 } 1393 1394 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1395 1396 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1397 * configure endpoints, or take their config from silicon 1398 */ 1399 static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1400 { 1401 u8 reg; 1402 char *type; 1403 char aInfo[90], aRevision[32], aDate[12]; 1404 void __iomem *mbase = musb->mregs; 1405 int status = 0; 1406 int i; 1407 1408 /* log core options (read using indexed model) */ 1409 reg = musb_read_configdata(mbase); 1410 1411 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1412 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1413 strcat(aInfo, ", dyn FIFOs"); 1414 musb->dyn_fifo = true; 1415 } 1416 #ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT 1417 if (reg & MUSB_CONFIGDATA_MPRXE) { 1418 strcat(aInfo, ", bulk combine"); 1419 musb->bulk_combine = true; 1420 } 1421 if (reg & MUSB_CONFIGDATA_MPTXE) { 1422 strcat(aInfo, ", bulk split"); 1423 musb->bulk_split = true; 1424 } 1425 #else 1426 musb->bulk_combine = false; 1427 musb->bulk_split = false; 1428 #endif 1429 if (reg & MUSB_CONFIGDATA_HBRXE) { 1430 strcat(aInfo, ", HB-ISO Rx"); 1431 musb->hb_iso_rx = true; 1432 } 1433 if (reg & MUSB_CONFIGDATA_HBTXE) { 1434 strcat(aInfo, ", HB-ISO Tx"); 1435 musb->hb_iso_tx = true; 1436 } 1437 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1438 strcat(aInfo, ", SoftConn"); 1439 1440 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); 1441 1442 aDate[0] = 0; 1443 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1444 musb->is_multipoint = 1; 1445 type = "M"; 1446 } else { 1447 musb->is_multipoint = 0; 1448 type = ""; 1449 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1450 printk(KERN_ERR 1451 "%s: kernel must blacklist external hubs\n", 1452 musb_driver_name); 1453 #endif 1454 } 1455 1456 /* log release info */ 1457 musb->hwvers = musb_read_hwvers(mbase); 1458 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1459 MUSB_HWVERS_MINOR(musb->hwvers), 1460 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1461 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type, 1462 aRevision, aDate); 1463 1464 /* configure ep0 */ 1465 musb_configure_ep0(musb); 1466 1467 /* discover endpoint configuration */ 1468 musb->nr_endpoints = 1; 1469 musb->epmask = 1; 1470 1471 if (musb->dyn_fifo) 1472 status = ep_config_from_table(musb); 1473 else 1474 status = ep_config_from_hw(musb); 1475 1476 if (status < 0) 1477 return status; 1478 1479 /* finish init, and print endpoint config */ 1480 for (i = 0; i < musb->nr_endpoints; i++) { 1481 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1482 1483 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1484 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1485 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1486 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1487 hw_ep->fifo_sync_va = 1488 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1489 1490 if (i == 0) 1491 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1492 else 1493 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1494 #endif 1495 1496 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1497 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1498 hw_ep->rx_reinit = 1; 1499 hw_ep->tx_reinit = 1; 1500 1501 if (hw_ep->max_packet_sz_tx) { 1502 dev_dbg(musb->controller, 1503 "%s: hw_ep %d%s, %smax %d\n", 1504 musb_driver_name, i, 1505 hw_ep->is_shared_fifo ? "shared" : "tx", 1506 hw_ep->tx_double_buffered 1507 ? "doublebuffer, " : "", 1508 hw_ep->max_packet_sz_tx); 1509 } 1510 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1511 dev_dbg(musb->controller, 1512 "%s: hw_ep %d%s, %smax %d\n", 1513 musb_driver_name, i, 1514 "rx", 1515 hw_ep->rx_double_buffered 1516 ? "doublebuffer, " : "", 1517 hw_ep->max_packet_sz_rx); 1518 } 1519 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1520 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1521 } 1522 1523 return 0; 1524 } 1525 1526 /*-------------------------------------------------------------------------*/ 1527 1528 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1529 defined(CONFIG_ARCH_OMAP4) 1530 1531 static irqreturn_t generic_interrupt(int irq, void *__hci) 1532 { 1533 unsigned long flags; 1534 irqreturn_t retval = IRQ_NONE; 1535 struct musb *musb = __hci; 1536 1537 spin_lock_irqsave(&musb->lock, flags); 1538 1539 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1540 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1541 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1542 1543 if (musb->int_usb || musb->int_tx || musb->int_rx) 1544 retval = musb_interrupt(musb); 1545 1546 spin_unlock_irqrestore(&musb->lock, flags); 1547 1548 return retval; 1549 } 1550 1551 #else 1552 #define generic_interrupt NULL 1553 #endif 1554 1555 /* 1556 * handle all the irqs defined by the HDRC core. for now we expect: other 1557 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1558 * will be assigned, and the irq will already have been acked. 1559 * 1560 * called in irq context with spinlock held, irqs blocked 1561 */ 1562 irqreturn_t musb_interrupt(struct musb *musb) 1563 { 1564 irqreturn_t retval = IRQ_NONE; 1565 u8 devctl, power; 1566 int ep_num; 1567 u32 reg; 1568 1569 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1570 power = musb_readb(musb->mregs, MUSB_POWER); 1571 1572 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1573 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1574 musb->int_usb, musb->int_tx, musb->int_rx); 1575 1576 /* the core can interrupt us for multiple reasons; docs have 1577 * a generic interrupt flowchart to follow 1578 */ 1579 if (musb->int_usb) 1580 retval |= musb_stage0_irq(musb, musb->int_usb, 1581 devctl, power); 1582 1583 /* "stage 1" is handling endpoint irqs */ 1584 1585 /* handle endpoint 0 first */ 1586 if (musb->int_tx & 1) { 1587 if (devctl & MUSB_DEVCTL_HM) { 1588 if (is_host_capable()) 1589 retval |= musb_h_ep0_irq(musb); 1590 } else { 1591 if (is_peripheral_capable()) 1592 retval |= musb_g_ep0_irq(musb); 1593 } 1594 } 1595 1596 /* RX on endpoints 1-15 */ 1597 reg = musb->int_rx >> 1; 1598 ep_num = 1; 1599 while (reg) { 1600 if (reg & 1) { 1601 /* musb_ep_select(musb->mregs, ep_num); */ 1602 /* REVISIT just retval = ep->rx_irq(...) */ 1603 retval = IRQ_HANDLED; 1604 if (devctl & MUSB_DEVCTL_HM) { 1605 if (is_host_capable()) 1606 musb_host_rx(musb, ep_num); 1607 } else { 1608 if (is_peripheral_capable()) 1609 musb_g_rx(musb, ep_num); 1610 } 1611 } 1612 1613 reg >>= 1; 1614 ep_num++; 1615 } 1616 1617 /* TX on endpoints 1-15 */ 1618 reg = musb->int_tx >> 1; 1619 ep_num = 1; 1620 while (reg) { 1621 if (reg & 1) { 1622 /* musb_ep_select(musb->mregs, ep_num); */ 1623 /* REVISIT just retval |= ep->tx_irq(...) */ 1624 retval = IRQ_HANDLED; 1625 if (devctl & MUSB_DEVCTL_HM) { 1626 if (is_host_capable()) 1627 musb_host_tx(musb, ep_num); 1628 } else { 1629 if (is_peripheral_capable()) 1630 musb_g_tx(musb, ep_num); 1631 } 1632 } 1633 reg >>= 1; 1634 ep_num++; 1635 } 1636 1637 return retval; 1638 } 1639 EXPORT_SYMBOL_GPL(musb_interrupt); 1640 1641 #ifndef CONFIG_USB_MUSB_PIO_ONLY 1642 static bool __devinitdata use_dma = 1; 1643 1644 /* "modprobe ... use_dma=0" etc */ 1645 module_param(use_dma, bool, 0); 1646 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1647 1648 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1649 { 1650 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1651 1652 /* called with controller lock already held */ 1653 1654 if (!epnum) { 1655 #ifndef CONFIG_USB_TUSB_OMAP_DMA 1656 if (!is_cppi_enabled()) { 1657 /* endpoint 0 */ 1658 if (devctl & MUSB_DEVCTL_HM) 1659 musb_h_ep0_irq(musb); 1660 else 1661 musb_g_ep0_irq(musb); 1662 } 1663 #endif 1664 } else { 1665 /* endpoints 1..15 */ 1666 if (transmit) { 1667 if (devctl & MUSB_DEVCTL_HM) { 1668 if (is_host_capable()) 1669 musb_host_tx(musb, epnum); 1670 } else { 1671 if (is_peripheral_capable()) 1672 musb_g_tx(musb, epnum); 1673 } 1674 } else { 1675 /* receive */ 1676 if (devctl & MUSB_DEVCTL_HM) { 1677 if (is_host_capable()) 1678 musb_host_rx(musb, epnum); 1679 } else { 1680 if (is_peripheral_capable()) 1681 musb_g_rx(musb, epnum); 1682 } 1683 } 1684 } 1685 } 1686 EXPORT_SYMBOL_GPL(musb_dma_completion); 1687 1688 #else 1689 #define use_dma 0 1690 #endif 1691 1692 /*-------------------------------------------------------------------------*/ 1693 1694 #ifdef CONFIG_SYSFS 1695 1696 static ssize_t 1697 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1698 { 1699 struct musb *musb = dev_to_musb(dev); 1700 unsigned long flags; 1701 int ret = -EINVAL; 1702 1703 spin_lock_irqsave(&musb->lock, flags); 1704 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1705 spin_unlock_irqrestore(&musb->lock, flags); 1706 1707 return ret; 1708 } 1709 1710 static ssize_t 1711 musb_mode_store(struct device *dev, struct device_attribute *attr, 1712 const char *buf, size_t n) 1713 { 1714 struct musb *musb = dev_to_musb(dev); 1715 unsigned long flags; 1716 int status; 1717 1718 spin_lock_irqsave(&musb->lock, flags); 1719 if (sysfs_streq(buf, "host")) 1720 status = musb_platform_set_mode(musb, MUSB_HOST); 1721 else if (sysfs_streq(buf, "peripheral")) 1722 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1723 else if (sysfs_streq(buf, "otg")) 1724 status = musb_platform_set_mode(musb, MUSB_OTG); 1725 else 1726 status = -EINVAL; 1727 spin_unlock_irqrestore(&musb->lock, flags); 1728 1729 return (status == 0) ? n : status; 1730 } 1731 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1732 1733 static ssize_t 1734 musb_vbus_store(struct device *dev, struct device_attribute *attr, 1735 const char *buf, size_t n) 1736 { 1737 struct musb *musb = dev_to_musb(dev); 1738 unsigned long flags; 1739 unsigned long val; 1740 1741 if (sscanf(buf, "%lu", &val) < 1) { 1742 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1743 return -EINVAL; 1744 } 1745 1746 spin_lock_irqsave(&musb->lock, flags); 1747 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1748 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1749 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1750 musb->is_active = 0; 1751 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1752 spin_unlock_irqrestore(&musb->lock, flags); 1753 1754 return n; 1755 } 1756 1757 static ssize_t 1758 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1759 { 1760 struct musb *musb = dev_to_musb(dev); 1761 unsigned long flags; 1762 unsigned long val; 1763 int vbus; 1764 1765 spin_lock_irqsave(&musb->lock, flags); 1766 val = musb->a_wait_bcon; 1767 /* FIXME get_vbus_status() is normally #defined as false... 1768 * and is effectively TUSB-specific. 1769 */ 1770 vbus = musb_platform_get_vbus_status(musb); 1771 spin_unlock_irqrestore(&musb->lock, flags); 1772 1773 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1774 vbus ? "on" : "off", val); 1775 } 1776 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1777 1778 /* Gadget drivers can't know that a host is connected so they might want 1779 * to start SRP, but users can. This allows userspace to trigger SRP. 1780 */ 1781 static ssize_t 1782 musb_srp_store(struct device *dev, struct device_attribute *attr, 1783 const char *buf, size_t n) 1784 { 1785 struct musb *musb = dev_to_musb(dev); 1786 unsigned short srp; 1787 1788 if (sscanf(buf, "%hu", &srp) != 1 1789 || (srp != 1)) { 1790 dev_err(dev, "SRP: Value must be 1\n"); 1791 return -EINVAL; 1792 } 1793 1794 if (srp == 1) 1795 musb_g_wakeup(musb); 1796 1797 return n; 1798 } 1799 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1800 1801 static struct attribute *musb_attributes[] = { 1802 &dev_attr_mode.attr, 1803 &dev_attr_vbus.attr, 1804 &dev_attr_srp.attr, 1805 NULL 1806 }; 1807 1808 static const struct attribute_group musb_attr_group = { 1809 .attrs = musb_attributes, 1810 }; 1811 1812 #endif /* sysfs */ 1813 1814 #ifndef __UBOOT__ 1815 /* Only used to provide driver mode change events */ 1816 static void musb_irq_work(struct work_struct *data) 1817 { 1818 struct musb *musb = container_of(data, struct musb, irq_work); 1819 static int old_state; 1820 1821 if (musb->xceiv->state != old_state) { 1822 old_state = musb->xceiv->state; 1823 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1824 } 1825 } 1826 #endif 1827 1828 /* -------------------------------------------------------------------------- 1829 * Init support 1830 */ 1831 1832 static struct musb *__devinit 1833 allocate_instance(struct device *dev, 1834 struct musb_hdrc_config *config, void __iomem *mbase) 1835 { 1836 struct musb *musb; 1837 struct musb_hw_ep *ep; 1838 int epnum; 1839 #ifndef __UBOOT__ 1840 struct usb_hcd *hcd; 1841 1842 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1843 if (!hcd) 1844 return NULL; 1845 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1846 1847 musb = hcd_to_musb(hcd); 1848 #else 1849 musb = calloc(1, sizeof(*musb)); 1850 if (!musb) 1851 return NULL; 1852 #endif 1853 INIT_LIST_HEAD(&musb->control); 1854 INIT_LIST_HEAD(&musb->in_bulk); 1855 INIT_LIST_HEAD(&musb->out_bulk); 1856 1857 #ifndef __UBOOT__ 1858 hcd->uses_new_polling = 1; 1859 hcd->has_tt = 1; 1860 #endif 1861 1862 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1863 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1864 dev_set_drvdata(dev, musb); 1865 musb->mregs = mbase; 1866 musb->ctrl_base = mbase; 1867 musb->nIrq = -ENODEV; 1868 musb->config = config; 1869 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1870 for (epnum = 0, ep = musb->endpoints; 1871 epnum < musb->config->num_eps; 1872 epnum++, ep++) { 1873 ep->musb = musb; 1874 ep->epnum = epnum; 1875 } 1876 1877 musb->controller = dev; 1878 1879 return musb; 1880 } 1881 1882 static void musb_free(struct musb *musb) 1883 { 1884 /* this has multiple entry modes. it handles fault cleanup after 1885 * probe(), where things may be partially set up, as well as rmmod 1886 * cleanup after everything's been de-activated. 1887 */ 1888 1889 #ifdef CONFIG_SYSFS 1890 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1891 #endif 1892 1893 if (musb->nIrq >= 0) { 1894 if (musb->irq_wake) 1895 disable_irq_wake(musb->nIrq); 1896 free_irq(musb->nIrq, musb); 1897 } 1898 if (is_dma_capable() && musb->dma_controller) { 1899 struct dma_controller *c = musb->dma_controller; 1900 1901 (void) c->stop(c); 1902 dma_controller_destroy(c); 1903 } 1904 1905 kfree(musb); 1906 } 1907 1908 /* 1909 * Perform generic per-controller initialization. 1910 * 1911 * @pDevice: the controller (already clocked, etc) 1912 * @nIrq: irq 1913 * @mregs: virtual address of controller registers, 1914 * not yet corrected for platform-specific offsets 1915 */ 1916 #ifndef __UBOOT__ 1917 static int __devinit 1918 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1919 #else 1920 struct musb * 1921 musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev, 1922 void *ctrl) 1923 #endif 1924 { 1925 int status; 1926 struct musb *musb; 1927 #ifndef __UBOOT__ 1928 struct musb_hdrc_platform_data *plat = dev->platform_data; 1929 #else 1930 int nIrq = 0; 1931 #endif 1932 1933 /* The driver might handle more features than the board; OK. 1934 * Fail when the board needs a feature that's not enabled. 1935 */ 1936 if (!plat) { 1937 dev_dbg(dev, "no platform_data?\n"); 1938 status = -ENODEV; 1939 goto fail0; 1940 } 1941 1942 /* allocate */ 1943 musb = allocate_instance(dev, plat->config, ctrl); 1944 if (!musb) { 1945 status = -ENOMEM; 1946 goto fail0; 1947 } 1948 1949 pm_runtime_use_autosuspend(musb->controller); 1950 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1951 pm_runtime_enable(musb->controller); 1952 1953 spin_lock_init(&musb->lock); 1954 musb->board_mode = plat->mode; 1955 musb->board_set_power = plat->set_power; 1956 musb->min_power = plat->min_power; 1957 musb->ops = plat->platform_ops; 1958 1959 /* The musb_platform_init() call: 1960 * - adjusts musb->mregs and musb->isr if needed, 1961 * - may initialize an integrated tranceiver 1962 * - initializes musb->xceiv, usually by otg_get_phy() 1963 * - stops powering VBUS 1964 * 1965 * There are various transceiver configurations. Blackfin, 1966 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1967 * external/discrete ones in various flavors (twl4030 family, 1968 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1969 */ 1970 musb->isr = generic_interrupt; 1971 status = musb_platform_init(musb); 1972 if (status < 0) 1973 goto fail1; 1974 1975 if (!musb->isr) { 1976 status = -ENODEV; 1977 goto fail2; 1978 } 1979 1980 #ifndef __UBOOT__ 1981 if (!musb->xceiv->io_ops) { 1982 musb->xceiv->io_dev = musb->controller; 1983 musb->xceiv->io_priv = musb->mregs; 1984 musb->xceiv->io_ops = &musb_ulpi_access; 1985 } 1986 #endif 1987 1988 pm_runtime_get_sync(musb->controller); 1989 1990 #ifndef CONFIG_USB_MUSB_PIO_ONLY 1991 if (use_dma && dev->dma_mask) { 1992 struct dma_controller *c; 1993 1994 c = dma_controller_create(musb, musb->mregs); 1995 musb->dma_controller = c; 1996 if (c) 1997 (void) c->start(c); 1998 } 1999 #endif 2000 #ifndef __UBOOT__ 2001 /* ideally this would be abstracted in platform setup */ 2002 if (!is_dma_capable() || !musb->dma_controller) 2003 dev->dma_mask = NULL; 2004 #endif 2005 2006 /* be sure interrupts are disabled before connecting ISR */ 2007 musb_platform_disable(musb); 2008 musb_generic_disable(musb); 2009 2010 /* setup musb parts of the core (especially endpoints) */ 2011 status = musb_core_init(plat->config->multipoint 2012 ? MUSB_CONTROLLER_MHDRC 2013 : MUSB_CONTROLLER_HDRC, musb); 2014 if (status < 0) 2015 goto fail3; 2016 2017 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2018 2019 /* Init IRQ workqueue before request_irq */ 2020 INIT_WORK(&musb->irq_work, musb_irq_work); 2021 2022 /* attach to the IRQ */ 2023 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2024 dev_err(dev, "request_irq %d failed!\n", nIrq); 2025 status = -ENODEV; 2026 goto fail3; 2027 } 2028 musb->nIrq = nIrq; 2029 /* FIXME this handles wakeup irqs wrong */ 2030 if (enable_irq_wake(nIrq) == 0) { 2031 musb->irq_wake = 1; 2032 device_init_wakeup(dev, 1); 2033 } else { 2034 musb->irq_wake = 0; 2035 } 2036 2037 #ifndef __UBOOT__ 2038 /* host side needs more setup */ 2039 if (is_host_enabled(musb)) { 2040 struct usb_hcd *hcd = musb_to_hcd(musb); 2041 2042 otg_set_host(musb->xceiv->otg, &hcd->self); 2043 2044 if (is_otg_enabled(musb)) 2045 hcd->self.otg_port = 1; 2046 musb->xceiv->otg->host = &hcd->self; 2047 hcd->power_budget = 2 * (plat->power ? : 250); 2048 2049 /* program PHY to use external vBus if required */ 2050 if (plat->extvbus) { 2051 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2052 busctl |= MUSB_ULPI_USE_EXTVBUS; 2053 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2054 } 2055 } 2056 #endif 2057 2058 /* For the host-only role, we can activate right away. 2059 * (We expect the ID pin to be forcibly grounded!!) 2060 * Otherwise, wait till the gadget driver hooks up. 2061 */ 2062 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2063 struct usb_hcd *hcd = musb_to_hcd(musb); 2064 2065 MUSB_HST_MODE(musb); 2066 #ifndef __UBOOT__ 2067 musb->xceiv->otg->default_a = 1; 2068 musb->xceiv->state = OTG_STATE_A_IDLE; 2069 2070 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2071 2072 hcd->self.uses_pio_for_control = 1; 2073 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2074 "HOST", status, 2075 musb_readb(musb->mregs, MUSB_DEVCTL), 2076 (musb_readb(musb->mregs, MUSB_DEVCTL) 2077 & MUSB_DEVCTL_BDEVICE 2078 ? 'B' : 'A')); 2079 #endif 2080 2081 } else /* peripheral is enabled */ { 2082 MUSB_DEV_MODE(musb); 2083 #ifndef __UBOOT__ 2084 musb->xceiv->otg->default_a = 0; 2085 musb->xceiv->state = OTG_STATE_B_IDLE; 2086 #endif 2087 2088 if (is_peripheral_capable()) 2089 status = musb_gadget_setup(musb); 2090 2091 #ifndef __UBOOT__ 2092 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2093 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2094 status, 2095 musb_readb(musb->mregs, MUSB_DEVCTL)); 2096 #endif 2097 2098 } 2099 if (status < 0) 2100 goto fail3; 2101 2102 status = musb_init_debugfs(musb); 2103 if (status < 0) 2104 goto fail4; 2105 2106 #ifdef CONFIG_SYSFS 2107 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2108 if (status) 2109 goto fail5; 2110 #endif 2111 2112 pm_runtime_put(musb->controller); 2113 2114 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n", 2115 ({char *s; 2116 switch (musb->board_mode) { 2117 case MUSB_HOST: s = "Host"; break; 2118 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2119 default: s = "OTG"; break; 2120 }; s; }), 2121 ctrl, 2122 (is_dma_capable() && musb->dma_controller) 2123 ? "DMA" : "PIO", 2124 musb->nIrq); 2125 2126 #ifndef __UBOOT__ 2127 return 0; 2128 #else 2129 return status == 0 ? musb : NULL; 2130 #endif 2131 2132 fail5: 2133 musb_exit_debugfs(musb); 2134 2135 fail4: 2136 #ifndef __UBOOT__ 2137 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2138 usb_remove_hcd(musb_to_hcd(musb)); 2139 else 2140 #endif 2141 musb_gadget_cleanup(musb); 2142 2143 fail3: 2144 pm_runtime_put_sync(musb->controller); 2145 2146 fail2: 2147 if (musb->irq_wake) 2148 device_init_wakeup(dev, 0); 2149 musb_platform_exit(musb); 2150 2151 fail1: 2152 dev_err(musb->controller, 2153 "musb_init_controller failed with status %d\n", status); 2154 2155 musb_free(musb); 2156 2157 fail0: 2158 2159 #ifndef __UBOOT__ 2160 return status; 2161 #else 2162 return status == 0 ? musb : NULL; 2163 #endif 2164 2165 } 2166 2167 /*-------------------------------------------------------------------------*/ 2168 2169 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2170 * bridge to a platform device; this driver then suffices. 2171 */ 2172 2173 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2174 static u64 *orig_dma_mask; 2175 #endif 2176 2177 #ifndef __UBOOT__ 2178 static int __devinit musb_probe(struct platform_device *pdev) 2179 { 2180 struct device *dev = &pdev->dev; 2181 int irq = platform_get_irq_byname(pdev, "mc"); 2182 int status; 2183 struct resource *iomem; 2184 void __iomem *base; 2185 2186 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2187 if (!iomem || irq <= 0) 2188 return -ENODEV; 2189 2190 base = ioremap(iomem->start, resource_size(iomem)); 2191 if (!base) { 2192 dev_err(dev, "ioremap failed\n"); 2193 return -ENOMEM; 2194 } 2195 2196 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2197 /* clobbered by use_dma=n */ 2198 orig_dma_mask = dev->dma_mask; 2199 #endif 2200 status = musb_init_controller(dev, irq, base); 2201 if (status < 0) 2202 iounmap(base); 2203 2204 return status; 2205 } 2206 2207 static int __devexit musb_remove(struct platform_device *pdev) 2208 { 2209 struct musb *musb = dev_to_musb(&pdev->dev); 2210 void __iomem *ctrl_base = musb->ctrl_base; 2211 2212 /* this gets called on rmmod. 2213 * - Host mode: host may still be active 2214 * - Peripheral mode: peripheral is deactivated (or never-activated) 2215 * - OTG mode: both roles are deactivated (or never-activated) 2216 */ 2217 musb_exit_debugfs(musb); 2218 musb_shutdown(pdev); 2219 2220 musb_free(musb); 2221 iounmap(ctrl_base); 2222 device_init_wakeup(&pdev->dev, 0); 2223 #ifndef CONFIG_USB_MUSB_PIO_ONLY 2224 pdev->dev.dma_mask = orig_dma_mask; 2225 #endif 2226 return 0; 2227 } 2228 2229 #ifdef CONFIG_PM 2230 2231 static void musb_save_context(struct musb *musb) 2232 { 2233 int i; 2234 void __iomem *musb_base = musb->mregs; 2235 void __iomem *epio; 2236 2237 if (is_host_enabled(musb)) { 2238 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2239 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2240 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2241 } 2242 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2243 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2244 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2245 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2246 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2247 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2248 2249 for (i = 0; i < musb->config->num_eps; ++i) { 2250 struct musb_hw_ep *hw_ep; 2251 2252 hw_ep = &musb->endpoints[i]; 2253 if (!hw_ep) 2254 continue; 2255 2256 epio = hw_ep->regs; 2257 if (!epio) 2258 continue; 2259 2260 musb_writeb(musb_base, MUSB_INDEX, i); 2261 musb->context.index_regs[i].txmaxp = 2262 musb_readw(epio, MUSB_TXMAXP); 2263 musb->context.index_regs[i].txcsr = 2264 musb_readw(epio, MUSB_TXCSR); 2265 musb->context.index_regs[i].rxmaxp = 2266 musb_readw(epio, MUSB_RXMAXP); 2267 musb->context.index_regs[i].rxcsr = 2268 musb_readw(epio, MUSB_RXCSR); 2269 2270 if (musb->dyn_fifo) { 2271 musb->context.index_regs[i].txfifoadd = 2272 musb_read_txfifoadd(musb_base); 2273 musb->context.index_regs[i].rxfifoadd = 2274 musb_read_rxfifoadd(musb_base); 2275 musb->context.index_regs[i].txfifosz = 2276 musb_read_txfifosz(musb_base); 2277 musb->context.index_regs[i].rxfifosz = 2278 musb_read_rxfifosz(musb_base); 2279 } 2280 if (is_host_enabled(musb)) { 2281 musb->context.index_regs[i].txtype = 2282 musb_readb(epio, MUSB_TXTYPE); 2283 musb->context.index_regs[i].txinterval = 2284 musb_readb(epio, MUSB_TXINTERVAL); 2285 musb->context.index_regs[i].rxtype = 2286 musb_readb(epio, MUSB_RXTYPE); 2287 musb->context.index_regs[i].rxinterval = 2288 musb_readb(epio, MUSB_RXINTERVAL); 2289 2290 musb->context.index_regs[i].txfunaddr = 2291 musb_read_txfunaddr(musb_base, i); 2292 musb->context.index_regs[i].txhubaddr = 2293 musb_read_txhubaddr(musb_base, i); 2294 musb->context.index_regs[i].txhubport = 2295 musb_read_txhubport(musb_base, i); 2296 2297 musb->context.index_regs[i].rxfunaddr = 2298 musb_read_rxfunaddr(musb_base, i); 2299 musb->context.index_regs[i].rxhubaddr = 2300 musb_read_rxhubaddr(musb_base, i); 2301 musb->context.index_regs[i].rxhubport = 2302 musb_read_rxhubport(musb_base, i); 2303 } 2304 } 2305 } 2306 2307 static void musb_restore_context(struct musb *musb) 2308 { 2309 int i; 2310 void __iomem *musb_base = musb->mregs; 2311 void __iomem *ep_target_regs; 2312 void __iomem *epio; 2313 2314 if (is_host_enabled(musb)) { 2315 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2316 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2317 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2318 } 2319 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2320 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2321 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2322 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2323 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2324 2325 for (i = 0; i < musb->config->num_eps; ++i) { 2326 struct musb_hw_ep *hw_ep; 2327 2328 hw_ep = &musb->endpoints[i]; 2329 if (!hw_ep) 2330 continue; 2331 2332 epio = hw_ep->regs; 2333 if (!epio) 2334 continue; 2335 2336 musb_writeb(musb_base, MUSB_INDEX, i); 2337 musb_writew(epio, MUSB_TXMAXP, 2338 musb->context.index_regs[i].txmaxp); 2339 musb_writew(epio, MUSB_TXCSR, 2340 musb->context.index_regs[i].txcsr); 2341 musb_writew(epio, MUSB_RXMAXP, 2342 musb->context.index_regs[i].rxmaxp); 2343 musb_writew(epio, MUSB_RXCSR, 2344 musb->context.index_regs[i].rxcsr); 2345 2346 if (musb->dyn_fifo) { 2347 musb_write_txfifosz(musb_base, 2348 musb->context.index_regs[i].txfifosz); 2349 musb_write_rxfifosz(musb_base, 2350 musb->context.index_regs[i].rxfifosz); 2351 musb_write_txfifoadd(musb_base, 2352 musb->context.index_regs[i].txfifoadd); 2353 musb_write_rxfifoadd(musb_base, 2354 musb->context.index_regs[i].rxfifoadd); 2355 } 2356 2357 if (is_host_enabled(musb)) { 2358 musb_writeb(epio, MUSB_TXTYPE, 2359 musb->context.index_regs[i].txtype); 2360 musb_writeb(epio, MUSB_TXINTERVAL, 2361 musb->context.index_regs[i].txinterval); 2362 musb_writeb(epio, MUSB_RXTYPE, 2363 musb->context.index_regs[i].rxtype); 2364 musb_writeb(epio, MUSB_RXINTERVAL, 2365 2366 musb->context.index_regs[i].rxinterval); 2367 musb_write_txfunaddr(musb_base, i, 2368 musb->context.index_regs[i].txfunaddr); 2369 musb_write_txhubaddr(musb_base, i, 2370 musb->context.index_regs[i].txhubaddr); 2371 musb_write_txhubport(musb_base, i, 2372 musb->context.index_regs[i].txhubport); 2373 2374 ep_target_regs = 2375 musb_read_target_reg_base(i, musb_base); 2376 2377 musb_write_rxfunaddr(ep_target_regs, 2378 musb->context.index_regs[i].rxfunaddr); 2379 musb_write_rxhubaddr(ep_target_regs, 2380 musb->context.index_regs[i].rxhubaddr); 2381 musb_write_rxhubport(ep_target_regs, 2382 musb->context.index_regs[i].rxhubport); 2383 } 2384 } 2385 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2386 } 2387 2388 static int musb_suspend(struct device *dev) 2389 { 2390 struct musb *musb = dev_to_musb(dev); 2391 unsigned long flags; 2392 2393 spin_lock_irqsave(&musb->lock, flags); 2394 2395 if (is_peripheral_active(musb)) { 2396 /* FIXME force disconnect unless we know USB will wake 2397 * the system up quickly enough to respond ... 2398 */ 2399 } else if (is_host_active(musb)) { 2400 /* we know all the children are suspended; sometimes 2401 * they will even be wakeup-enabled. 2402 */ 2403 } 2404 2405 spin_unlock_irqrestore(&musb->lock, flags); 2406 return 0; 2407 } 2408 2409 static int musb_resume_noirq(struct device *dev) 2410 { 2411 /* for static cmos like DaVinci, register values were preserved 2412 * unless for some reason the whole soc powered down or the USB 2413 * module got reset through the PSC (vs just being disabled). 2414 */ 2415 return 0; 2416 } 2417 2418 static int musb_runtime_suspend(struct device *dev) 2419 { 2420 struct musb *musb = dev_to_musb(dev); 2421 2422 musb_save_context(musb); 2423 2424 return 0; 2425 } 2426 2427 static int musb_runtime_resume(struct device *dev) 2428 { 2429 struct musb *musb = dev_to_musb(dev); 2430 static int first = 1; 2431 2432 /* 2433 * When pm_runtime_get_sync called for the first time in driver 2434 * init, some of the structure is still not initialized which is 2435 * used in restore function. But clock needs to be 2436 * enabled before any register access, so 2437 * pm_runtime_get_sync has to be called. 2438 * Also context restore without save does not make 2439 * any sense 2440 */ 2441 if (!first) 2442 musb_restore_context(musb); 2443 first = 0; 2444 2445 return 0; 2446 } 2447 2448 static const struct dev_pm_ops musb_dev_pm_ops = { 2449 .suspend = musb_suspend, 2450 .resume_noirq = musb_resume_noirq, 2451 .runtime_suspend = musb_runtime_suspend, 2452 .runtime_resume = musb_runtime_resume, 2453 }; 2454 2455 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2456 #else 2457 #define MUSB_DEV_PM_OPS NULL 2458 #endif 2459 2460 static struct platform_driver musb_driver = { 2461 .driver = { 2462 .name = (char *)musb_driver_name, 2463 .bus = &platform_bus_type, 2464 .owner = THIS_MODULE, 2465 .pm = MUSB_DEV_PM_OPS, 2466 }, 2467 .probe = musb_probe, 2468 .remove = __devexit_p(musb_remove), 2469 .shutdown = musb_shutdown, 2470 }; 2471 2472 /*-------------------------------------------------------------------------*/ 2473 2474 static int __init musb_init(void) 2475 { 2476 if (usb_disabled()) 2477 return 0; 2478 2479 pr_info("%s: version " MUSB_VERSION ", " 2480 "?dma?" 2481 ", " 2482 "otg (peripheral+host)", 2483 musb_driver_name); 2484 return platform_driver_register(&musb_driver); 2485 } 2486 module_init(musb_init); 2487 2488 static void __exit musb_cleanup(void) 2489 { 2490 platform_driver_unregister(&musb_driver); 2491 } 2492 module_exit(musb_cleanup); 2493 #endif 2494