1 /* 2 * Texas Instruments AM35x "glue layer" 3 * 4 * Copyright (c) 2010, by Texas Instruments 5 * 6 * Based on the DA8xx "glue layer" code. 7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This file is part of the Inventra Controller Driver for Linux. 10 * 11 * The Inventra Controller Driver for Linux is free software; you 12 * can redistribute it and/or modify it under the terms of the GNU 13 * General Public License version 2 as published by the Free Software 14 * Foundation. 15 * 16 * The Inventra Controller Driver for Linux is distributed in 17 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 18 * without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 * License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with The Inventra Controller Driver for Linux ; if not, 24 * write to the Free Software Foundation, Inc., 59 Temple Place, 25 * Suite 330, Boston, MA 02111-1307 USA 26 * 27 */ 28 29 #ifndef __UBOOT__ 30 #include <linux/init.h> 31 #include <linux/module.h> 32 #include <linux/clk.h> 33 #include <linux/err.h> 34 #include <linux/io.h> 35 #include <linux/platform_device.h> 36 #include <linux/dma-mapping.h> 37 38 #include <plat/usb.h> 39 #else 40 #include <common.h> 41 #include <asm/omap_musb.h> 42 #include "linux-compat.h" 43 #endif 44 45 #include "musb_core.h" 46 47 /* 48 * AM35x specific definitions 49 */ 50 /* USB 2.0 OTG module registers */ 51 #define USB_REVISION_REG 0x00 52 #define USB_CTRL_REG 0x04 53 #define USB_STAT_REG 0x08 54 #define USB_EMULATION_REG 0x0c 55 /* 0x10 Reserved */ 56 #define USB_AUTOREQ_REG 0x14 57 #define USB_SRP_FIX_TIME_REG 0x18 58 #define USB_TEARDOWN_REG 0x1c 59 #define EP_INTR_SRC_REG 0x20 60 #define EP_INTR_SRC_SET_REG 0x24 61 #define EP_INTR_SRC_CLEAR_REG 0x28 62 #define EP_INTR_MASK_REG 0x2c 63 #define EP_INTR_MASK_SET_REG 0x30 64 #define EP_INTR_MASK_CLEAR_REG 0x34 65 #define EP_INTR_SRC_MASKED_REG 0x38 66 #define CORE_INTR_SRC_REG 0x40 67 #define CORE_INTR_SRC_SET_REG 0x44 68 #define CORE_INTR_SRC_CLEAR_REG 0x48 69 #define CORE_INTR_MASK_REG 0x4c 70 #define CORE_INTR_MASK_SET_REG 0x50 71 #define CORE_INTR_MASK_CLEAR_REG 0x54 72 #define CORE_INTR_SRC_MASKED_REG 0x58 73 /* 0x5c Reserved */ 74 #define USB_END_OF_INTR_REG 0x60 75 76 /* Control register bits */ 77 #define AM35X_SOFT_RESET_MASK 1 78 79 /* USB interrupt register bits */ 80 #define AM35X_INTR_USB_SHIFT 16 81 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) 82 #define AM35X_INTR_DRVVBUS 0x100 83 #define AM35X_INTR_RX_SHIFT 16 84 #define AM35X_INTR_TX_SHIFT 0 85 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ 86 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ 87 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) 88 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) 89 90 #define USB_MENTOR_CORE_OFFSET 0x400 91 92 struct am35x_glue { 93 struct device *dev; 94 struct platform_device *musb; 95 struct clk *phy_clk; 96 struct clk *clk; 97 }; 98 #define glue_to_musb(g) platform_get_drvdata(g->musb) 99 100 /* 101 * am35x_musb_enable - enable interrupts 102 */ 103 static void am35x_musb_enable(struct musb *musb) 104 { 105 void __iomem *reg_base = musb->ctrl_base; 106 u32 epmask; 107 108 /* Workaround: setup IRQs through both register sets. */ 109 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | 110 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); 111 112 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); 113 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); 114 115 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 116 if (is_otg_enabled(musb)) 117 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, 118 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); 119 } 120 121 /* 122 * am35x_musb_disable - disable HDRC and flush interrupts 123 */ 124 static void am35x_musb_disable(struct musb *musb) 125 { 126 void __iomem *reg_base = musb->ctrl_base; 127 128 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); 129 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, 130 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); 131 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 132 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 133 } 134 135 #ifndef __UBOOT__ 136 #define portstate(stmt) stmt 137 138 static void am35x_musb_set_vbus(struct musb *musb, int is_on) 139 { 140 WARN_ON(is_on && is_peripheral_active(musb)); 141 } 142 143 #define POLL_SECONDS 2 144 145 static struct timer_list otg_workaround; 146 147 static void otg_timer(unsigned long _musb) 148 { 149 struct musb *musb = (void *)_musb; 150 void __iomem *mregs = musb->mregs; 151 u8 devctl; 152 unsigned long flags; 153 154 /* 155 * We poll because AM35x's won't expose several OTG-critical 156 * status change events (from the transceiver) otherwise. 157 */ 158 devctl = musb_readb(mregs, MUSB_DEVCTL); 159 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 160 otg_state_string(musb->xceiv->state)); 161 162 spin_lock_irqsave(&musb->lock, flags); 163 switch (musb->xceiv->state) { 164 case OTG_STATE_A_WAIT_BCON: 165 devctl &= ~MUSB_DEVCTL_SESSION; 166 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 167 168 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 169 if (devctl & MUSB_DEVCTL_BDEVICE) { 170 musb->xceiv->state = OTG_STATE_B_IDLE; 171 MUSB_DEV_MODE(musb); 172 } else { 173 musb->xceiv->state = OTG_STATE_A_IDLE; 174 MUSB_HST_MODE(musb); 175 } 176 break; 177 case OTG_STATE_A_WAIT_VFALL: 178 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 179 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, 180 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); 181 break; 182 case OTG_STATE_B_IDLE: 183 if (!is_peripheral_enabled(musb)) 184 break; 185 186 devctl = musb_readb(mregs, MUSB_DEVCTL); 187 if (devctl & MUSB_DEVCTL_BDEVICE) 188 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 189 else 190 musb->xceiv->state = OTG_STATE_A_IDLE; 191 break; 192 default: 193 break; 194 } 195 spin_unlock_irqrestore(&musb->lock, flags); 196 } 197 198 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) 199 { 200 static unsigned long last_timer; 201 202 if (!is_otg_enabled(musb)) 203 return; 204 205 if (timeout == 0) 206 timeout = jiffies + msecs_to_jiffies(3); 207 208 /* Never idle if active, or when VBUS timeout is not set as host */ 209 if (musb->is_active || (musb->a_wait_bcon == 0 && 210 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 211 dev_dbg(musb->controller, "%s active, deleting timer\n", 212 otg_state_string(musb->xceiv->state)); 213 del_timer(&otg_workaround); 214 last_timer = jiffies; 215 return; 216 } 217 218 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 219 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 220 return; 221 } 222 last_timer = timeout; 223 224 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 225 otg_state_string(musb->xceiv->state), 226 jiffies_to_msecs(timeout - jiffies)); 227 mod_timer(&otg_workaround, timeout); 228 } 229 #endif 230 231 static irqreturn_t am35x_musb_interrupt(int irq, void *hci) 232 { 233 struct musb *musb = hci; 234 void __iomem *reg_base = musb->ctrl_base; 235 #ifndef __UBOOT__ 236 struct device *dev = musb->controller; 237 struct musb_hdrc_platform_data *plat = dev->platform_data; 238 struct omap_musb_board_data *data = plat->board_data; 239 struct usb_otg *otg = musb->xceiv->otg; 240 #else 241 struct omap_musb_board_data *data = 242 (struct omap_musb_board_data *)musb->controller; 243 #endif 244 unsigned long flags; 245 irqreturn_t ret = IRQ_NONE; 246 u32 epintr, usbintr; 247 248 #ifdef __UBOOT__ 249 /* 250 * It seems that on AM35X interrupt registers can be updated 251 * before core registers. This confuses the code. 252 * As a workaround add a small delay here. 253 */ 254 udelay(10); 255 #endif 256 spin_lock_irqsave(&musb->lock, flags); 257 258 /* Get endpoint interrupts */ 259 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); 260 261 if (epintr) { 262 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); 263 264 musb->int_rx = 265 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; 266 musb->int_tx = 267 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; 268 } 269 270 /* Get usb core interrupts */ 271 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); 272 if (!usbintr && !epintr) 273 goto eoi; 274 275 if (usbintr) { 276 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); 277 278 musb->int_usb = 279 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; 280 } 281 #ifndef __UBOOT__ 282 /* 283 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 284 * AM35x's missing ID change IRQ. We need an ID change IRQ to 285 * switch appropriately between halves of the OTG state machine. 286 * Managing DEVCTL.SESSION per Mentor docs requires that we know its 287 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. 288 * Also, DRVVBUS pulses for SRP (but not at 5V) ... 289 */ 290 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { 291 int drvvbus = musb_readl(reg_base, USB_STAT_REG); 292 void __iomem *mregs = musb->mregs; 293 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 294 int err; 295 296 err = is_host_enabled(musb) && (musb->int_usb & 297 MUSB_INTR_VBUSERROR); 298 if (err) { 299 /* 300 * The Mentor core doesn't debounce VBUS as needed 301 * to cope with device connect current spikes. This 302 * means it's not uncommon for bus-powered devices 303 * to get VBUS errors during enumeration. 304 * 305 * This is a workaround, but newer RTL from Mentor 306 * seems to allow a better one: "re"-starting sessions 307 * without waiting for VBUS to stop registering in 308 * devctl. 309 */ 310 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 312 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 313 WARNING("VBUS error workaround (delay coming)\n"); 314 } else if (is_host_enabled(musb) && drvvbus) { 315 MUSB_HST_MODE(musb); 316 otg->default_a = 1; 317 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 318 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 319 del_timer(&otg_workaround); 320 } else { 321 musb->is_active = 0; 322 MUSB_DEV_MODE(musb); 323 otg->default_a = 0; 324 musb->xceiv->state = OTG_STATE_B_IDLE; 325 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 326 } 327 328 /* NOTE: this must complete power-on within 100 ms. */ 329 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 330 drvvbus ? "on" : "off", 331 otg_state_string(musb->xceiv->state), 332 err ? " ERROR" : "", 333 devctl); 334 ret = IRQ_HANDLED; 335 } 336 #endif 337 338 if (musb->int_tx || musb->int_rx || musb->int_usb) 339 ret |= musb_interrupt(musb); 340 341 eoi: 342 /* EOI needs to be written for the IRQ to be re-asserted. */ 343 if (ret == IRQ_HANDLED || epintr || usbintr) { 344 /* clear level interrupt */ 345 if (data->clear_irq) 346 data->clear_irq(); 347 /* write EOI */ 348 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 349 } 350 351 #ifndef __UBOOT__ 352 /* Poll for ID change */ 353 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) 354 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 355 #endif 356 357 spin_unlock_irqrestore(&musb->lock, flags); 358 359 return ret; 360 } 361 362 #ifndef __UBOOT__ 363 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) 364 { 365 struct device *dev = musb->controller; 366 struct musb_hdrc_platform_data *plat = dev->platform_data; 367 struct omap_musb_board_data *data = plat->board_data; 368 int retval = 0; 369 370 if (data->set_mode) 371 data->set_mode(musb_mode); 372 else 373 retval = -EIO; 374 375 return retval; 376 } 377 #endif 378 379 static int am35x_musb_init(struct musb *musb) 380 { 381 #ifndef __UBOOT__ 382 struct device *dev = musb->controller; 383 struct musb_hdrc_platform_data *plat = dev->platform_data; 384 struct omap_musb_board_data *data = plat->board_data; 385 #else 386 struct omap_musb_board_data *data = 387 (struct omap_musb_board_data *)musb->controller; 388 #endif 389 void __iomem *reg_base = musb->ctrl_base; 390 u32 rev; 391 392 musb->mregs += USB_MENTOR_CORE_OFFSET; 393 394 /* Returns zero if e.g. not clocked */ 395 rev = musb_readl(reg_base, USB_REVISION_REG); 396 if (!rev) 397 return -ENODEV; 398 399 #ifndef __UBOOT__ 400 usb_nop_xceiv_register(); 401 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 402 if (IS_ERR_OR_NULL(musb->xceiv)) 403 return -ENODEV; 404 405 if (is_host_enabled(musb)) 406 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); 407 #endif 408 409 /* Reset the musb */ 410 if (data->reset) 411 data->reset(); 412 413 /* Reset the controller */ 414 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); 415 416 /* Start the on-chip PHY and its PLL. */ 417 if (data->set_phy_power) 418 data->set_phy_power(1); 419 420 msleep(5); 421 422 musb->isr = am35x_musb_interrupt; 423 424 /* clear level interrupt */ 425 if (data->clear_irq) 426 data->clear_irq(); 427 428 return 0; 429 } 430 431 static int am35x_musb_exit(struct musb *musb) 432 { 433 #ifndef __UBOOT__ 434 struct device *dev = musb->controller; 435 struct musb_hdrc_platform_data *plat = dev->platform_data; 436 struct omap_musb_board_data *data = plat->board_data; 437 #else 438 struct omap_musb_board_data *data = 439 (struct omap_musb_board_data *)musb->controller; 440 #endif 441 442 #ifndef __UBOOT__ 443 if (is_host_enabled(musb)) 444 del_timer_sync(&otg_workaround); 445 #endif 446 447 /* Shutdown the on-chip PHY and its PLL. */ 448 if (data->set_phy_power) 449 data->set_phy_power(0); 450 451 #ifndef __UBOOT__ 452 usb_put_phy(musb->xceiv); 453 usb_nop_xceiv_unregister(); 454 #endif 455 456 return 0; 457 } 458 459 /* AM35x supports only 32bit read operation */ 460 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 461 { 462 void __iomem *fifo = hw_ep->fifo; 463 u32 val; 464 int i; 465 466 /* Read for 32bit-aligned destination address */ 467 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { 468 readsl(fifo, dst, len >> 2); 469 dst += len & ~0x03; 470 len &= 0x03; 471 } 472 /* 473 * Now read the remaining 1 to 3 byte or complete length if 474 * unaligned address. 475 */ 476 if (len > 4) { 477 for (i = 0; i < (len >> 2); i++) { 478 *(u32 *) dst = musb_readl(fifo, 0); 479 dst += 4; 480 } 481 len &= 0x03; 482 } 483 if (len > 0) { 484 val = musb_readl(fifo, 0); 485 memcpy(dst, &val, len); 486 } 487 } 488 489 #ifndef __UBOOT__ 490 static const struct musb_platform_ops am35x_ops = { 491 #else 492 const struct musb_platform_ops am35x_ops = { 493 #endif 494 .init = am35x_musb_init, 495 .exit = am35x_musb_exit, 496 497 .enable = am35x_musb_enable, 498 .disable = am35x_musb_disable, 499 500 #ifndef __UBOOT__ 501 .set_mode = am35x_musb_set_mode, 502 .try_idle = am35x_musb_try_idle, 503 504 .set_vbus = am35x_musb_set_vbus, 505 #endif 506 }; 507 508 #ifndef __UBOOT__ 509 static u64 am35x_dmamask = DMA_BIT_MASK(32); 510 511 static int __devinit am35x_probe(struct platform_device *pdev) 512 { 513 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 514 struct platform_device *musb; 515 struct am35x_glue *glue; 516 517 struct clk *phy_clk; 518 struct clk *clk; 519 520 int ret = -ENOMEM; 521 522 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 523 if (!glue) { 524 dev_err(&pdev->dev, "failed to allocate glue context\n"); 525 goto err0; 526 } 527 528 musb = platform_device_alloc("musb-hdrc", -1); 529 if (!musb) { 530 dev_err(&pdev->dev, "failed to allocate musb device\n"); 531 goto err1; 532 } 533 534 phy_clk = clk_get(&pdev->dev, "fck"); 535 if (IS_ERR(phy_clk)) { 536 dev_err(&pdev->dev, "failed to get PHY clock\n"); 537 ret = PTR_ERR(phy_clk); 538 goto err2; 539 } 540 541 clk = clk_get(&pdev->dev, "ick"); 542 if (IS_ERR(clk)) { 543 dev_err(&pdev->dev, "failed to get clock\n"); 544 ret = PTR_ERR(clk); 545 goto err3; 546 } 547 548 ret = clk_enable(phy_clk); 549 if (ret) { 550 dev_err(&pdev->dev, "failed to enable PHY clock\n"); 551 goto err4; 552 } 553 554 ret = clk_enable(clk); 555 if (ret) { 556 dev_err(&pdev->dev, "failed to enable clock\n"); 557 goto err5; 558 } 559 560 musb->dev.parent = &pdev->dev; 561 musb->dev.dma_mask = &am35x_dmamask; 562 musb->dev.coherent_dma_mask = am35x_dmamask; 563 564 glue->dev = &pdev->dev; 565 glue->musb = musb; 566 glue->phy_clk = phy_clk; 567 glue->clk = clk; 568 569 pdata->platform_ops = &am35x_ops; 570 571 platform_set_drvdata(pdev, glue); 572 573 ret = platform_device_add_resources(musb, pdev->resource, 574 pdev->num_resources); 575 if (ret) { 576 dev_err(&pdev->dev, "failed to add resources\n"); 577 goto err6; 578 } 579 580 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 581 if (ret) { 582 dev_err(&pdev->dev, "failed to add platform_data\n"); 583 goto err6; 584 } 585 586 ret = platform_device_add(musb); 587 if (ret) { 588 dev_err(&pdev->dev, "failed to register musb device\n"); 589 goto err6; 590 } 591 592 return 0; 593 594 err6: 595 clk_disable(clk); 596 597 err5: 598 clk_disable(phy_clk); 599 600 err4: 601 clk_put(clk); 602 603 err3: 604 clk_put(phy_clk); 605 606 err2: 607 platform_device_put(musb); 608 609 err1: 610 kfree(glue); 611 612 err0: 613 return ret; 614 } 615 616 static int __devexit am35x_remove(struct platform_device *pdev) 617 { 618 struct am35x_glue *glue = platform_get_drvdata(pdev); 619 620 platform_device_del(glue->musb); 621 platform_device_put(glue->musb); 622 clk_disable(glue->clk); 623 clk_disable(glue->phy_clk); 624 clk_put(glue->clk); 625 clk_put(glue->phy_clk); 626 kfree(glue); 627 628 return 0; 629 } 630 631 #ifdef CONFIG_PM 632 static int am35x_suspend(struct device *dev) 633 { 634 struct am35x_glue *glue = dev_get_drvdata(dev); 635 struct musb_hdrc_platform_data *plat = dev->platform_data; 636 struct omap_musb_board_data *data = plat->board_data; 637 638 /* Shutdown the on-chip PHY and its PLL. */ 639 if (data->set_phy_power) 640 data->set_phy_power(0); 641 642 clk_disable(glue->phy_clk); 643 clk_disable(glue->clk); 644 645 return 0; 646 } 647 648 static int am35x_resume(struct device *dev) 649 { 650 struct am35x_glue *glue = dev_get_drvdata(dev); 651 struct musb_hdrc_platform_data *plat = dev->platform_data; 652 struct omap_musb_board_data *data = plat->board_data; 653 int ret; 654 655 /* Start the on-chip PHY and its PLL. */ 656 if (data->set_phy_power) 657 data->set_phy_power(1); 658 659 ret = clk_enable(glue->phy_clk); 660 if (ret) { 661 dev_err(dev, "failed to enable PHY clock\n"); 662 return ret; 663 } 664 665 ret = clk_enable(glue->clk); 666 if (ret) { 667 dev_err(dev, "failed to enable clock\n"); 668 return ret; 669 } 670 671 return 0; 672 } 673 674 static struct dev_pm_ops am35x_pm_ops = { 675 .suspend = am35x_suspend, 676 .resume = am35x_resume, 677 }; 678 679 #define DEV_PM_OPS &am35x_pm_ops 680 #else 681 #define DEV_PM_OPS NULL 682 #endif 683 684 static struct platform_driver am35x_driver = { 685 .probe = am35x_probe, 686 .remove = __devexit_p(am35x_remove), 687 .driver = { 688 .name = "musb-am35x", 689 .pm = DEV_PM_OPS, 690 }, 691 }; 692 693 MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); 694 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 695 MODULE_LICENSE("GPL v2"); 696 697 static int __init am35x_init(void) 698 { 699 return platform_driver_register(&am35x_driver); 700 } 701 module_init(am35x_init); 702 703 static void __exit am35x_exit(void) 704 { 705 platform_driver_unregister(&am35x_driver); 706 } 707 module_exit(am35x_exit); 708 #endif 709