1 /* 2 * Texas Instruments AM35x "glue layer" 3 * 4 * Copyright (c) 2010, by Texas Instruments 5 * 6 * Based on the DA8xx "glue layer" code. 7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This file is part of the Inventra Controller Driver for Linux. 10 * 11 * The Inventra Controller Driver for Linux is free software; you 12 * can redistribute it and/or modify it under the terms of the GNU 13 * General Public License version 2 as published by the Free Software 14 * Foundation. 15 * 16 * The Inventra Controller Driver for Linux is distributed in 17 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 18 * without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 * License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with The Inventra Controller Driver for Linux ; if not, 24 * write to the Free Software Foundation, Inc., 59 Temple Place, 25 * Suite 330, Boston, MA 02111-1307 USA 26 * 27 */ 28 29 #define __UBOOT__ 30 #ifndef __UBOOT__ 31 #include <linux/init.h> 32 #include <linux/module.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/io.h> 36 #include <linux/platform_device.h> 37 #include <linux/dma-mapping.h> 38 39 #include <plat/usb.h> 40 #else 41 #include <common.h> 42 #include <asm/omap_musb.h> 43 #include "linux-compat.h" 44 #endif 45 46 #include "musb_core.h" 47 48 /* 49 * AM35x specific definitions 50 */ 51 /* USB 2.0 OTG module registers */ 52 #define USB_REVISION_REG 0x00 53 #define USB_CTRL_REG 0x04 54 #define USB_STAT_REG 0x08 55 #define USB_EMULATION_REG 0x0c 56 /* 0x10 Reserved */ 57 #define USB_AUTOREQ_REG 0x14 58 #define USB_SRP_FIX_TIME_REG 0x18 59 #define USB_TEARDOWN_REG 0x1c 60 #define EP_INTR_SRC_REG 0x20 61 #define EP_INTR_SRC_SET_REG 0x24 62 #define EP_INTR_SRC_CLEAR_REG 0x28 63 #define EP_INTR_MASK_REG 0x2c 64 #define EP_INTR_MASK_SET_REG 0x30 65 #define EP_INTR_MASK_CLEAR_REG 0x34 66 #define EP_INTR_SRC_MASKED_REG 0x38 67 #define CORE_INTR_SRC_REG 0x40 68 #define CORE_INTR_SRC_SET_REG 0x44 69 #define CORE_INTR_SRC_CLEAR_REG 0x48 70 #define CORE_INTR_MASK_REG 0x4c 71 #define CORE_INTR_MASK_SET_REG 0x50 72 #define CORE_INTR_MASK_CLEAR_REG 0x54 73 #define CORE_INTR_SRC_MASKED_REG 0x58 74 /* 0x5c Reserved */ 75 #define USB_END_OF_INTR_REG 0x60 76 77 /* Control register bits */ 78 #define AM35X_SOFT_RESET_MASK 1 79 80 /* USB interrupt register bits */ 81 #define AM35X_INTR_USB_SHIFT 16 82 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) 83 #define AM35X_INTR_DRVVBUS 0x100 84 #define AM35X_INTR_RX_SHIFT 16 85 #define AM35X_INTR_TX_SHIFT 0 86 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ 87 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ 88 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) 89 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) 90 91 #define USB_MENTOR_CORE_OFFSET 0x400 92 93 struct am35x_glue { 94 struct device *dev; 95 struct platform_device *musb; 96 struct clk *phy_clk; 97 struct clk *clk; 98 }; 99 #define glue_to_musb(g) platform_get_drvdata(g->musb) 100 101 /* 102 * am35x_musb_enable - enable interrupts 103 */ 104 static void am35x_musb_enable(struct musb *musb) 105 { 106 void __iomem *reg_base = musb->ctrl_base; 107 u32 epmask; 108 109 /* Workaround: setup IRQs through both register sets. */ 110 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | 111 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); 112 113 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); 114 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); 115 116 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 117 if (is_otg_enabled(musb)) 118 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, 119 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); 120 } 121 122 /* 123 * am35x_musb_disable - disable HDRC and flush interrupts 124 */ 125 static void am35x_musb_disable(struct musb *musb) 126 { 127 void __iomem *reg_base = musb->ctrl_base; 128 129 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); 130 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, 131 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); 132 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 133 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 134 } 135 136 #ifndef __UBOOT__ 137 #define portstate(stmt) stmt 138 139 static void am35x_musb_set_vbus(struct musb *musb, int is_on) 140 { 141 WARN_ON(is_on && is_peripheral_active(musb)); 142 } 143 144 #define POLL_SECONDS 2 145 146 static struct timer_list otg_workaround; 147 148 static void otg_timer(unsigned long _musb) 149 { 150 struct musb *musb = (void *)_musb; 151 void __iomem *mregs = musb->mregs; 152 u8 devctl; 153 unsigned long flags; 154 155 /* 156 * We poll because AM35x's won't expose several OTG-critical 157 * status change events (from the transceiver) otherwise. 158 */ 159 devctl = musb_readb(mregs, MUSB_DEVCTL); 160 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 161 otg_state_string(musb->xceiv->state)); 162 163 spin_lock_irqsave(&musb->lock, flags); 164 switch (musb->xceiv->state) { 165 case OTG_STATE_A_WAIT_BCON: 166 devctl &= ~MUSB_DEVCTL_SESSION; 167 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 168 169 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 170 if (devctl & MUSB_DEVCTL_BDEVICE) { 171 musb->xceiv->state = OTG_STATE_B_IDLE; 172 MUSB_DEV_MODE(musb); 173 } else { 174 musb->xceiv->state = OTG_STATE_A_IDLE; 175 MUSB_HST_MODE(musb); 176 } 177 break; 178 case OTG_STATE_A_WAIT_VFALL: 179 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 180 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, 181 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); 182 break; 183 case OTG_STATE_B_IDLE: 184 if (!is_peripheral_enabled(musb)) 185 break; 186 187 devctl = musb_readb(mregs, MUSB_DEVCTL); 188 if (devctl & MUSB_DEVCTL_BDEVICE) 189 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 190 else 191 musb->xceiv->state = OTG_STATE_A_IDLE; 192 break; 193 default: 194 break; 195 } 196 spin_unlock_irqrestore(&musb->lock, flags); 197 } 198 199 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) 200 { 201 static unsigned long last_timer; 202 203 if (!is_otg_enabled(musb)) 204 return; 205 206 if (timeout == 0) 207 timeout = jiffies + msecs_to_jiffies(3); 208 209 /* Never idle if active, or when VBUS timeout is not set as host */ 210 if (musb->is_active || (musb->a_wait_bcon == 0 && 211 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 212 dev_dbg(musb->controller, "%s active, deleting timer\n", 213 otg_state_string(musb->xceiv->state)); 214 del_timer(&otg_workaround); 215 last_timer = jiffies; 216 return; 217 } 218 219 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 220 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 221 return; 222 } 223 last_timer = timeout; 224 225 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 226 otg_state_string(musb->xceiv->state), 227 jiffies_to_msecs(timeout - jiffies)); 228 mod_timer(&otg_workaround, timeout); 229 } 230 #endif 231 232 static irqreturn_t am35x_musb_interrupt(int irq, void *hci) 233 { 234 struct musb *musb = hci; 235 void __iomem *reg_base = musb->ctrl_base; 236 #ifndef __UBOOT__ 237 struct device *dev = musb->controller; 238 struct musb_hdrc_platform_data *plat = dev->platform_data; 239 struct omap_musb_board_data *data = plat->board_data; 240 struct usb_otg *otg = musb->xceiv->otg; 241 #else 242 struct omap_musb_board_data *data = 243 (struct omap_musb_board_data *)musb->controller; 244 #endif 245 unsigned long flags; 246 irqreturn_t ret = IRQ_NONE; 247 u32 epintr, usbintr; 248 249 #ifdef __UBOOT__ 250 /* 251 * It seems that on AM35X interrupt registers can be updated 252 * before core registers. This confuses the code. 253 * As a workaround add a small delay here. 254 */ 255 udelay(10); 256 #endif 257 spin_lock_irqsave(&musb->lock, flags); 258 259 /* Get endpoint interrupts */ 260 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); 261 262 if (epintr) { 263 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); 264 265 musb->int_rx = 266 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; 267 musb->int_tx = 268 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; 269 } 270 271 /* Get usb core interrupts */ 272 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); 273 if (!usbintr && !epintr) 274 goto eoi; 275 276 if (usbintr) { 277 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); 278 279 musb->int_usb = 280 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; 281 } 282 #ifndef __UBOOT__ 283 /* 284 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 285 * AM35x's missing ID change IRQ. We need an ID change IRQ to 286 * switch appropriately between halves of the OTG state machine. 287 * Managing DEVCTL.SESSION per Mentor docs requires that we know its 288 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. 289 * Also, DRVVBUS pulses for SRP (but not at 5V) ... 290 */ 291 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { 292 int drvvbus = musb_readl(reg_base, USB_STAT_REG); 293 void __iomem *mregs = musb->mregs; 294 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 295 int err; 296 297 err = is_host_enabled(musb) && (musb->int_usb & 298 MUSB_INTR_VBUSERROR); 299 if (err) { 300 /* 301 * The Mentor core doesn't debounce VBUS as needed 302 * to cope with device connect current spikes. This 303 * means it's not uncommon for bus-powered devices 304 * to get VBUS errors during enumeration. 305 * 306 * This is a workaround, but newer RTL from Mentor 307 * seems to allow a better one: "re"-starting sessions 308 * without waiting for VBUS to stop registering in 309 * devctl. 310 */ 311 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 312 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 313 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 314 WARNING("VBUS error workaround (delay coming)\n"); 315 } else if (is_host_enabled(musb) && drvvbus) { 316 MUSB_HST_MODE(musb); 317 otg->default_a = 1; 318 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 319 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 320 del_timer(&otg_workaround); 321 } else { 322 musb->is_active = 0; 323 MUSB_DEV_MODE(musb); 324 otg->default_a = 0; 325 musb->xceiv->state = OTG_STATE_B_IDLE; 326 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 327 } 328 329 /* NOTE: this must complete power-on within 100 ms. */ 330 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 331 drvvbus ? "on" : "off", 332 otg_state_string(musb->xceiv->state), 333 err ? " ERROR" : "", 334 devctl); 335 ret = IRQ_HANDLED; 336 } 337 #endif 338 339 if (musb->int_tx || musb->int_rx || musb->int_usb) 340 ret |= musb_interrupt(musb); 341 342 eoi: 343 /* EOI needs to be written for the IRQ to be re-asserted. */ 344 if (ret == IRQ_HANDLED || epintr || usbintr) { 345 /* clear level interrupt */ 346 if (data->clear_irq) 347 data->clear_irq(); 348 /* write EOI */ 349 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 350 } 351 352 #ifndef __UBOOT__ 353 /* Poll for ID change */ 354 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) 355 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 356 #endif 357 358 spin_unlock_irqrestore(&musb->lock, flags); 359 360 return ret; 361 } 362 363 #ifndef __UBOOT__ 364 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) 365 { 366 struct device *dev = musb->controller; 367 struct musb_hdrc_platform_data *plat = dev->platform_data; 368 struct omap_musb_board_data *data = plat->board_data; 369 int retval = 0; 370 371 if (data->set_mode) 372 data->set_mode(musb_mode); 373 else 374 retval = -EIO; 375 376 return retval; 377 } 378 #endif 379 380 static int am35x_musb_init(struct musb *musb) 381 { 382 #ifndef __UBOOT__ 383 struct device *dev = musb->controller; 384 struct musb_hdrc_platform_data *plat = dev->platform_data; 385 struct omap_musb_board_data *data = plat->board_data; 386 #else 387 struct omap_musb_board_data *data = 388 (struct omap_musb_board_data *)musb->controller; 389 #endif 390 void __iomem *reg_base = musb->ctrl_base; 391 u32 rev; 392 393 musb->mregs += USB_MENTOR_CORE_OFFSET; 394 395 /* Returns zero if e.g. not clocked */ 396 rev = musb_readl(reg_base, USB_REVISION_REG); 397 if (!rev) 398 return -ENODEV; 399 400 #ifndef __UBOOT__ 401 usb_nop_xceiv_register(); 402 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 403 if (IS_ERR_OR_NULL(musb->xceiv)) 404 return -ENODEV; 405 406 if (is_host_enabled(musb)) 407 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); 408 #endif 409 410 /* Reset the musb */ 411 if (data->reset) 412 data->reset(); 413 414 /* Reset the controller */ 415 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); 416 417 /* Start the on-chip PHY and its PLL. */ 418 if (data->set_phy_power) 419 data->set_phy_power(1); 420 421 msleep(5); 422 423 musb->isr = am35x_musb_interrupt; 424 425 /* clear level interrupt */ 426 if (data->clear_irq) 427 data->clear_irq(); 428 429 return 0; 430 } 431 432 static int am35x_musb_exit(struct musb *musb) 433 { 434 #ifndef __UBOOT__ 435 struct device *dev = musb->controller; 436 struct musb_hdrc_platform_data *plat = dev->platform_data; 437 struct omap_musb_board_data *data = plat->board_data; 438 #else 439 struct omap_musb_board_data *data = 440 (struct omap_musb_board_data *)musb->controller; 441 #endif 442 443 #ifndef __UBOOT__ 444 if (is_host_enabled(musb)) 445 del_timer_sync(&otg_workaround); 446 #endif 447 448 /* Shutdown the on-chip PHY and its PLL. */ 449 if (data->set_phy_power) 450 data->set_phy_power(0); 451 452 #ifndef __UBOOT__ 453 usb_put_phy(musb->xceiv); 454 usb_nop_xceiv_unregister(); 455 #endif 456 457 return 0; 458 } 459 460 /* AM35x supports only 32bit read operation */ 461 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 462 { 463 void __iomem *fifo = hw_ep->fifo; 464 u32 val; 465 int i; 466 467 /* Read for 32bit-aligned destination address */ 468 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { 469 readsl(fifo, dst, len >> 2); 470 dst += len & ~0x03; 471 len &= 0x03; 472 } 473 /* 474 * Now read the remaining 1 to 3 byte or complete length if 475 * unaligned address. 476 */ 477 if (len > 4) { 478 for (i = 0; i < (len >> 2); i++) { 479 *(u32 *) dst = musb_readl(fifo, 0); 480 dst += 4; 481 } 482 len &= 0x03; 483 } 484 if (len > 0) { 485 val = musb_readl(fifo, 0); 486 memcpy(dst, &val, len); 487 } 488 } 489 490 #ifndef __UBOOT__ 491 static const struct musb_platform_ops am35x_ops = { 492 #else 493 const struct musb_platform_ops am35x_ops = { 494 #endif 495 .init = am35x_musb_init, 496 .exit = am35x_musb_exit, 497 498 .enable = am35x_musb_enable, 499 .disable = am35x_musb_disable, 500 501 #ifndef __UBOOT__ 502 .set_mode = am35x_musb_set_mode, 503 .try_idle = am35x_musb_try_idle, 504 505 .set_vbus = am35x_musb_set_vbus, 506 #endif 507 }; 508 509 #ifndef __UBOOT__ 510 static u64 am35x_dmamask = DMA_BIT_MASK(32); 511 512 static int __devinit am35x_probe(struct platform_device *pdev) 513 { 514 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 515 struct platform_device *musb; 516 struct am35x_glue *glue; 517 518 struct clk *phy_clk; 519 struct clk *clk; 520 521 int ret = -ENOMEM; 522 523 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 524 if (!glue) { 525 dev_err(&pdev->dev, "failed to allocate glue context\n"); 526 goto err0; 527 } 528 529 musb = platform_device_alloc("musb-hdrc", -1); 530 if (!musb) { 531 dev_err(&pdev->dev, "failed to allocate musb device\n"); 532 goto err1; 533 } 534 535 phy_clk = clk_get(&pdev->dev, "fck"); 536 if (IS_ERR(phy_clk)) { 537 dev_err(&pdev->dev, "failed to get PHY clock\n"); 538 ret = PTR_ERR(phy_clk); 539 goto err2; 540 } 541 542 clk = clk_get(&pdev->dev, "ick"); 543 if (IS_ERR(clk)) { 544 dev_err(&pdev->dev, "failed to get clock\n"); 545 ret = PTR_ERR(clk); 546 goto err3; 547 } 548 549 ret = clk_enable(phy_clk); 550 if (ret) { 551 dev_err(&pdev->dev, "failed to enable PHY clock\n"); 552 goto err4; 553 } 554 555 ret = clk_enable(clk); 556 if (ret) { 557 dev_err(&pdev->dev, "failed to enable clock\n"); 558 goto err5; 559 } 560 561 musb->dev.parent = &pdev->dev; 562 musb->dev.dma_mask = &am35x_dmamask; 563 musb->dev.coherent_dma_mask = am35x_dmamask; 564 565 glue->dev = &pdev->dev; 566 glue->musb = musb; 567 glue->phy_clk = phy_clk; 568 glue->clk = clk; 569 570 pdata->platform_ops = &am35x_ops; 571 572 platform_set_drvdata(pdev, glue); 573 574 ret = platform_device_add_resources(musb, pdev->resource, 575 pdev->num_resources); 576 if (ret) { 577 dev_err(&pdev->dev, "failed to add resources\n"); 578 goto err6; 579 } 580 581 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 582 if (ret) { 583 dev_err(&pdev->dev, "failed to add platform_data\n"); 584 goto err6; 585 } 586 587 ret = platform_device_add(musb); 588 if (ret) { 589 dev_err(&pdev->dev, "failed to register musb device\n"); 590 goto err6; 591 } 592 593 return 0; 594 595 err6: 596 clk_disable(clk); 597 598 err5: 599 clk_disable(phy_clk); 600 601 err4: 602 clk_put(clk); 603 604 err3: 605 clk_put(phy_clk); 606 607 err2: 608 platform_device_put(musb); 609 610 err1: 611 kfree(glue); 612 613 err0: 614 return ret; 615 } 616 617 static int __devexit am35x_remove(struct platform_device *pdev) 618 { 619 struct am35x_glue *glue = platform_get_drvdata(pdev); 620 621 platform_device_del(glue->musb); 622 platform_device_put(glue->musb); 623 clk_disable(glue->clk); 624 clk_disable(glue->phy_clk); 625 clk_put(glue->clk); 626 clk_put(glue->phy_clk); 627 kfree(glue); 628 629 return 0; 630 } 631 632 #ifdef CONFIG_PM 633 static int am35x_suspend(struct device *dev) 634 { 635 struct am35x_glue *glue = dev_get_drvdata(dev); 636 struct musb_hdrc_platform_data *plat = dev->platform_data; 637 struct omap_musb_board_data *data = plat->board_data; 638 639 /* Shutdown the on-chip PHY and its PLL. */ 640 if (data->set_phy_power) 641 data->set_phy_power(0); 642 643 clk_disable(glue->phy_clk); 644 clk_disable(glue->clk); 645 646 return 0; 647 } 648 649 static int am35x_resume(struct device *dev) 650 { 651 struct am35x_glue *glue = dev_get_drvdata(dev); 652 struct musb_hdrc_platform_data *plat = dev->platform_data; 653 struct omap_musb_board_data *data = plat->board_data; 654 int ret; 655 656 /* Start the on-chip PHY and its PLL. */ 657 if (data->set_phy_power) 658 data->set_phy_power(1); 659 660 ret = clk_enable(glue->phy_clk); 661 if (ret) { 662 dev_err(dev, "failed to enable PHY clock\n"); 663 return ret; 664 } 665 666 ret = clk_enable(glue->clk); 667 if (ret) { 668 dev_err(dev, "failed to enable clock\n"); 669 return ret; 670 } 671 672 return 0; 673 } 674 675 static struct dev_pm_ops am35x_pm_ops = { 676 .suspend = am35x_suspend, 677 .resume = am35x_resume, 678 }; 679 680 #define DEV_PM_OPS &am35x_pm_ops 681 #else 682 #define DEV_PM_OPS NULL 683 #endif 684 685 static struct platform_driver am35x_driver = { 686 .probe = am35x_probe, 687 .remove = __devexit_p(am35x_remove), 688 .driver = { 689 .name = "musb-am35x", 690 .pm = DEV_PM_OPS, 691 }, 692 }; 693 694 MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); 695 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 696 MODULE_LICENSE("GPL v2"); 697 698 static int __init am35x_init(void) 699 { 700 return platform_driver_register(&am35x_driver); 701 } 702 module_init(am35x_init); 703 704 static void __exit am35x_exit(void) 705 { 706 platform_driver_unregister(&am35x_driver); 707 } 708 module_exit(am35x_exit); 709 #endif 710