1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * USB HOST XHCI Controller 4 * 5 * Based on xHCI host controller driver in linux-kernel 6 * by Sarah Sharp. 7 * 8 * Copyright (C) 2008 Intel Corp. 9 * Author: Sarah Sharp 10 * 11 * Copyright (C) 2013 Samsung Electronics Co.Ltd 12 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 13 * Vikas Sajjan <vikas.sajjan@samsung.com> 14 */ 15 16 #ifndef HOST_XHCI_H_ 17 #define HOST_XHCI_H_ 18 19 #include <asm/types.h> 20 #include <asm/cache.h> 21 #include <asm/io.h> 22 #include <linux/list.h> 23 #include <linux/compat.h> 24 25 #define MAX_EP_CTX_NUM 31 26 #define XHCI_ALIGNMENT 64 27 /* Generic timeout for XHCI events */ 28 #define XHCI_TIMEOUT 5000 29 /* Max number of USB devices for any host controller - limit in section 6.1 */ 30 #define MAX_HC_SLOTS 256 31 /* Section 5.3.3 - MaxPorts */ 32 #define MAX_HC_PORTS 255 33 34 /* Up to 16 ms to halt an HC */ 35 #define XHCI_MAX_HALT_USEC (16*1000) 36 37 #define XHCI_MAX_RESET_USEC (250*1000) 38 39 /* 40 * These bits are Read Only (RO) and should be saved and written to the 41 * registers: 0, 3, 10:13, 30 42 * connect status, over-current status, port speed, and device removable. 43 * connect status and port speed are also sticky - meaning they're in 44 * the AUX well and they aren't changed by a hot, warm, or cold reset. 45 */ 46 #define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) 47 /* 48 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 49 * bits 5:8, 9, 14:15, 25:27 50 * link state, port power, port indicator state, "wake on" enable state 51 */ 52 #define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) 53 /* 54 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 55 * bit 4 (port reset) 56 */ 57 #define XHCI_PORT_RW1S ((1 << 4)) 58 /* 59 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 60 * bits 1, 17, 18, 19, 20, 21, 22, 23 61 * port enable/disable, and 62 * change bits: connect, PED, 63 * warm port reset changed (reserved zero for USB 2.0 ports), 64 * over-current, reset, link state, and L1 change 65 */ 66 #define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) 67 /* 68 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 69 * latched in 70 */ 71 #define XHCI_PORT_RW ((1 << 16)) 72 /* 73 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 74 * bits 2, 24, 28:31 75 */ 76 #define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) 77 78 /* 79 * XHCI Register Space. 80 */ 81 struct xhci_hccr { 82 uint32_t cr_capbase; 83 uint32_t cr_hcsparams1; 84 uint32_t cr_hcsparams2; 85 uint32_t cr_hcsparams3; 86 uint32_t cr_hccparams; 87 uint32_t cr_dboff; 88 uint32_t cr_rtsoff; 89 90 /* hc_capbase bitmasks */ 91 /* bits 7:0 - how long is the Capabilities register */ 92 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 93 /* bits 31:16 */ 94 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 95 96 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 97 /* bits 0:7, Max Device Slots */ 98 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 99 #define HCS_SLOTS_MASK 0xff 100 /* bits 8:18, Max Interrupters */ 101 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 102 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 103 #define HCS_MAX_PORTS_SHIFT 24 104 #define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT) 105 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 106 107 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 108 /* bits 0:3, frames or uframes that SW needs to queue transactions 109 * ahead of the HW to meet periodic deadlines */ 110 #define HCS_IST(p) (((p) >> 0) & 0xf) 111 /* bits 4:7, max number of Event Ring segments */ 112 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 113 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 114 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 115 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 116 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 117 118 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 119 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 120 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 121 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 122 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 123 124 /* HCCPARAMS - hcc_params - bitmasks */ 125 /* true: HC can use 64-bit address pointers */ 126 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 127 /* true: HC can do bandwidth negotiation */ 128 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 129 /* true: HC uses 64-byte Device Context structures 130 * FIXME 64-byte context structures aren't supported yet. 131 */ 132 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 133 /* true: HC has port power switches */ 134 #define HCC_PPC(p) ((p) & (1 << 3)) 135 /* true: HC has port indicators */ 136 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 137 /* true: HC has Light HC Reset Capability */ 138 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 139 /* true: HC supports latency tolerance messaging */ 140 #define HCC_LTC(p) ((p) & (1 << 6)) 141 /* true: no secondary Stream ID Support */ 142 #define HCC_NSS(p) ((p) & (1 << 7)) 143 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 144 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 145 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 146 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 147 148 /* db_off bitmask - bits 0:1 reserved */ 149 #define DBOFF_MASK (~0x3) 150 151 /* run_regs_off bitmask - bits 0:4 reserved */ 152 #define RTSOFF_MASK (~0x1f) 153 154 }; 155 156 struct xhci_hcor_port_regs { 157 volatile uint32_t or_portsc; 158 volatile uint32_t or_portpmsc; 159 volatile uint32_t or_portli; 160 volatile uint32_t reserved_3; 161 }; 162 163 struct xhci_hcor { 164 volatile uint32_t or_usbcmd; 165 volatile uint32_t or_usbsts; 166 volatile uint32_t or_pagesize; 167 volatile uint32_t reserved_0[2]; 168 volatile uint32_t or_dnctrl; 169 volatile uint64_t or_crcr; 170 volatile uint32_t reserved_1[4]; 171 volatile uint64_t or_dcbaap; 172 volatile uint32_t or_config; 173 volatile uint32_t reserved_2[241]; 174 struct xhci_hcor_port_regs portregs[MAX_HC_PORTS]; 175 }; 176 177 /* USBCMD - USB command - command bitmasks */ 178 /* start/stop HC execution - do not write unless HC is halted*/ 179 #define CMD_RUN XHCI_CMD_RUN 180 /* Reset HC - resets internal HC state machine and all registers (except 181 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 182 * The xHCI driver must reinitialize the xHC after setting this bit. 183 */ 184 #define CMD_RESET (1 << 1) 185 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 186 #define CMD_EIE XHCI_CMD_EIE 187 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 188 #define CMD_HSEIE XHCI_CMD_HSEIE 189 /* bits 4:6 are reserved (and should be preserved on writes). */ 190 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 191 #define CMD_LRESET (1 << 7) 192 /* host controller save/restore state. */ 193 #define CMD_CSS (1 << 8) 194 #define CMD_CRS (1 << 9) 195 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 196 #define CMD_EWE XHCI_CMD_EWE 197 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 198 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 199 * '0' means the xHC can power it off if all ports are in the disconnect, 200 * disabled, or powered-off state. 201 */ 202 #define CMD_PM_INDEX (1 << 11) 203 /* bits 12:31 are reserved (and should be preserved on writes). */ 204 205 /* USBSTS - USB status - status bitmasks */ 206 /* HC not running - set to 1 when run/stop bit is cleared. */ 207 #define STS_HALT XHCI_STS_HALT 208 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 209 #define STS_FATAL (1 << 2) 210 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 211 #define STS_EINT (1 << 3) 212 /* port change detect */ 213 #define STS_PORT (1 << 4) 214 /* bits 5:7 reserved and zeroed */ 215 /* save state status - '1' means xHC is saving state */ 216 #define STS_SAVE (1 << 8) 217 /* restore state status - '1' means xHC is restoring state */ 218 #define STS_RESTORE (1 << 9) 219 /* true: save or restore error */ 220 #define STS_SRE (1 << 10) 221 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 222 #define STS_CNR XHCI_STS_CNR 223 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 224 #define STS_HCE (1 << 12) 225 /* bits 13:31 reserved and should be preserved */ 226 227 /* 228 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 229 * Generate a device notification event when the HC sees a transaction with a 230 * notification type that matches a bit set in this bit field. 231 */ 232 #define DEV_NOTE_MASK (0xffff) 233 #define ENABLE_DEV_NOTE(x) (1 << (x)) 234 /* Most of the device notification types should only be used for debug. 235 * SW does need to pay attention to function wake notifications. 236 */ 237 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 238 239 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 240 /* bit 0 is the command ring cycle state */ 241 /* stop ring operation after completion of the currently executing command */ 242 #define CMD_RING_PAUSE (1 << 1) 243 /* stop ring immediately - abort the currently executing command */ 244 #define CMD_RING_ABORT (1 << 2) 245 /* true: command ring is running */ 246 #define CMD_RING_RUNNING (1 << 3) 247 /* bits 4:5 reserved and should be preserved */ 248 /* Command Ring pointer - bit mask for the lower 32 bits. */ 249 #define CMD_RING_RSVD_BITS (0x3f) 250 251 /* CONFIG - Configure Register - config_reg bitmasks */ 252 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 253 #define MAX_DEVS(p) ((p) & 0xff) 254 /* bits 8:31 - reserved and should be preserved */ 255 256 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 257 /* true: device connected */ 258 #define PORT_CONNECT (1 << 0) 259 /* true: port enabled */ 260 #define PORT_PE (1 << 1) 261 /* bit 2 reserved and zeroed */ 262 /* true: port has an over-current condition */ 263 #define PORT_OC (1 << 3) 264 /* true: port reset signaling asserted */ 265 #define PORT_RESET (1 << 4) 266 /* Port Link State - bits 5:8 267 * A read gives the current link PM state of the port, 268 * a write with Link State Write Strobe set sets the link state. 269 */ 270 #define PORT_PLS_MASK (0xf << 5) 271 #define XDEV_U0 (0x0 << 5) 272 #define XDEV_U2 (0x2 << 5) 273 #define XDEV_U3 (0x3 << 5) 274 #define XDEV_RESUME (0xf << 5) 275 /* true: port has power (see HCC_PPC) */ 276 #define PORT_POWER (1 << 9) 277 /* bits 10:13 indicate device speed: 278 * 0 - undefined speed - port hasn't be initialized by a reset yet 279 * 1 - full speed 280 * 2 - low speed 281 * 3 - high speed 282 * 4 - super speed 283 * 5-15 reserved 284 */ 285 #define DEV_SPEED_MASK (0xf << 10) 286 #define XDEV_FS (0x1 << 10) 287 #define XDEV_LS (0x2 << 10) 288 #define XDEV_HS (0x3 << 10) 289 #define XDEV_SS (0x4 << 10) 290 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 291 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 292 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 293 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 294 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 295 /* Bits 20:23 in the Slot Context are the speed for the device */ 296 #define SLOT_SPEED_FS (XDEV_FS << 10) 297 #define SLOT_SPEED_LS (XDEV_LS << 10) 298 #define SLOT_SPEED_HS (XDEV_HS << 10) 299 #define SLOT_SPEED_SS (XDEV_SS << 10) 300 /* Port Indicator Control */ 301 #define PORT_LED_OFF (0 << 14) 302 #define PORT_LED_AMBER (1 << 14) 303 #define PORT_LED_GREEN (2 << 14) 304 #define PORT_LED_MASK (3 << 14) 305 /* Port Link State Write Strobe - set this when changing link state */ 306 #define PORT_LINK_STROBE (1 << 16) 307 /* true: connect status change */ 308 #define PORT_CSC (1 << 17) 309 /* true: port enable change */ 310 #define PORT_PEC (1 << 18) 311 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 312 * into an enabled state, and the device into the default state. A "warm" reset 313 * also resets the link, forcing the device through the link training sequence. 314 * SW can also look at the Port Reset register to see when warm reset is done. 315 */ 316 #define PORT_WRC (1 << 19) 317 /* true: over-current change */ 318 #define PORT_OCC (1 << 20) 319 /* true: reset change - 1 to 0 transition of PORT_RESET */ 320 #define PORT_RC (1 << 21) 321 /* port link status change - set on some port link state transitions: 322 * Transition Reason 323 * -------------------------------------------------------------------------- 324 * - U3 to Resume Wakeup signaling from a device 325 * - Resume to Recovery to U0 USB 3.0 device resume 326 * - Resume to U0 USB 2.0 device resume 327 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 328 * - U3 to U0 Software resume of USB 2.0 device complete 329 * - U2 to U0 L1 resume of USB 2.1 device complete 330 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 331 * - U0 to disabled L1 entry error with USB 2.1 device 332 * - Any state to inactive Error on USB 3.0 port 333 */ 334 #define PORT_PLC (1 << 22) 335 /* port configure error change - port failed to configure its link partner */ 336 #define PORT_CEC (1 << 23) 337 /* bit 24 reserved */ 338 /* wake on connect (enable) */ 339 #define PORT_WKCONN_E (1 << 25) 340 /* wake on disconnect (enable) */ 341 #define PORT_WKDISC_E (1 << 26) 342 /* wake on over-current (enable) */ 343 #define PORT_WKOC_E (1 << 27) 344 /* bits 28:29 reserved */ 345 /* true: device is removable - for USB 3.0 roothub emulation */ 346 #define PORT_DEV_REMOVE (1 << 30) 347 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 348 #define PORT_WR (1 << 31) 349 350 /* We mark duplicate entries with -1 */ 351 #define DUPLICATE_ENTRY ((u8)(-1)) 352 353 /* Port Power Management Status and Control - port_power_base bitmasks */ 354 /* Inactivity timer value for transitions into U1, in microseconds. 355 * Timeout can be up to 127us. 0xFF means an infinite timeout. 356 */ 357 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 358 /* Inactivity timer value for transitions into U2 */ 359 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 360 /* Bits 24:31 for port testing */ 361 362 /* USB2 Protocol PORTSPMSC */ 363 #define PORT_L1S_MASK 7 364 #define PORT_L1S_SUCCESS 1 365 #define PORT_RWE (1 << 3) 366 #define PORT_HIRD(p) (((p) & 0xf) << 4) 367 #define PORT_HIRD_MASK (0xf << 4) 368 #define PORT_L1DS(p) (((p) & 0xff) << 8) 369 #define PORT_HLE (1 << 16) 370 371 /** 372 * struct xhci_intr_reg - Interrupt Register Set 373 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 374 * interrupts and check for pending interrupts. 375 * @irq_control: IMOD - Interrupt Moderation Register. 376 * Used to throttle interrupts. 377 * @erst_size: Number of segments in the 378 Event Ring Segment Table (ERST). 379 * @erst_base: ERST base address. 380 * @erst_dequeue: Event ring dequeue pointer. 381 * 382 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 383 * Ring Segment Table (ERST) associated with it. 384 * The event ring is comprised of multiple segments of the same size. 385 * The HC places events on the ring and "updates the Cycle bit in the TRBs to 386 * indicate to software the current position of the Enqueue Pointer." 387 * The HCD (Linux) processes those events and updates the dequeue pointer. 388 */ 389 struct xhci_intr_reg { 390 volatile __le32 irq_pending; 391 volatile __le32 irq_control; 392 volatile __le32 erst_size; 393 volatile __le32 rsvd; 394 volatile __le64 erst_base; 395 volatile __le64 erst_dequeue; 396 }; 397 398 /* irq_pending bitmasks */ 399 #define ER_IRQ_PENDING(p) ((p) & 0x1) 400 /* bits 2:31 need to be preserved */ 401 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 402 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 403 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 404 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 405 406 /* irq_control bitmasks */ 407 /* Minimum interval between interrupts (in 250ns intervals). The interval 408 * between interrupts will be longer if there are no events on the event ring. 409 * Default is 4000 (1 ms). 410 */ 411 #define ER_IRQ_INTERVAL_MASK (0xffff) 412 /* Counter used to count down the time to the next interrupt - HW use only */ 413 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 414 415 /* erst_size bitmasks */ 416 /* Preserve bits 16:31 of erst_size */ 417 #define ERST_SIZE_MASK (0xffff << 16) 418 419 /* erst_dequeue bitmasks */ 420 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 421 * where the current dequeue pointer lies. This is an optional HW hint. 422 */ 423 #define ERST_DESI_MASK (0x7) 424 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 425 * a work queue (or delayed service routine)? 426 */ 427 #define ERST_EHB (1 << 3) 428 #define ERST_PTR_MASK (0xf) 429 430 /** 431 * struct xhci_run_regs 432 * @microframe_index: MFINDEX - current microframe number 433 * 434 * Section 5.5 Host Controller Runtime Registers: 435 * "Software should read and write these registers using only Dword (32 bit) 436 * or larger accesses" 437 */ 438 struct xhci_run_regs { 439 __le32 microframe_index; 440 __le32 rsvd[7]; 441 struct xhci_intr_reg ir_set[128]; 442 }; 443 444 /** 445 * struct doorbell_array 446 * 447 * Bits 0 - 7: Endpoint target 448 * Bits 8 - 15: RsvdZ 449 * Bits 16 - 31: Stream ID 450 * 451 * Section 5.6 452 */ 453 struct xhci_doorbell_array { 454 volatile __le32 doorbell[256]; 455 }; 456 457 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 458 #define DB_VALUE_HOST 0x00000000 459 460 /** 461 * struct xhci_protocol_caps 462 * @revision: major revision, minor revision, capability ID, 463 * and next capability pointer. 464 * @name_string: Four ASCII characters to say which spec this xHC 465 * follows, typically "USB ". 466 * @port_info: Port offset, count, and protocol-defined information. 467 */ 468 struct xhci_protocol_caps { 469 u32 revision; 470 u32 name_string; 471 u32 port_info; 472 }; 473 474 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 475 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 476 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 477 478 /** 479 * struct xhci_container_ctx 480 * @type: Type of context. Used to calculated offsets to contained contexts. 481 * @size: Size of the context data 482 * @bytes: The raw context data given to HW 483 * 484 * Represents either a Device or Input context. Holds a pointer to the raw 485 * memory used for the context (bytes). 486 */ 487 struct xhci_container_ctx { 488 unsigned type; 489 #define XHCI_CTX_TYPE_DEVICE 0x1 490 #define XHCI_CTX_TYPE_INPUT 0x2 491 492 int size; 493 u8 *bytes; 494 }; 495 496 /** 497 * struct xhci_slot_ctx 498 * @dev_info: Route string, device speed, hub info, and last valid endpoint 499 * @dev_info2: Max exit latency for device number, root hub port number 500 * @tt_info: tt_info is used to construct split transaction tokens 501 * @dev_state: slot state and device address 502 * 503 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 504 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 505 * reserved at the end of the slot context for HC internal use. 506 */ 507 struct xhci_slot_ctx { 508 __le32 dev_info; 509 __le32 dev_info2; 510 __le32 tt_info; 511 __le32 dev_state; 512 /* offset 0x10 to 0x1f reserved for HC internal use */ 513 __le32 reserved[4]; 514 }; 515 516 /* dev_info bitmasks */ 517 /* Route String - 0:19 */ 518 #define ROUTE_STRING_MASK (0xfffff) 519 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 520 #define DEV_SPEED (0xf << 20) 521 /* bit 24 reserved */ 522 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 523 #define DEV_MTT (0x1 << 25) 524 /* Set if the device is a hub - bit 26 */ 525 #define DEV_HUB (0x1 << 26) 526 /* Index of the last valid endpoint context in this device context - 27:31 */ 527 #define LAST_CTX_MASK (0x1f << 27) 528 #define LAST_CTX(p) ((p) << 27) 529 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 530 #define SLOT_FLAG (1 << 0) 531 #define EP0_FLAG (1 << 1) 532 533 /* dev_info2 bitmasks */ 534 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 535 #define MAX_EXIT (0xffff) 536 /* Root hub port number that is needed to access the USB device */ 537 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 538 #define ROOT_HUB_PORT_MASK (0xff) 539 #define ROOT_HUB_PORT_SHIFT (16) 540 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 541 /* Maximum number of ports under a hub device */ 542 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 543 544 /* tt_info bitmasks */ 545 /* 546 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 547 * The Slot ID of the hub that isolates the high speed signaling from 548 * this low or full-speed device. '0' if attached to root hub port. 549 */ 550 #define TT_SLOT(p) (((p) & 0xff) << 0) 551 /* 552 * The number of the downstream facing port of the high-speed hub 553 * '0' if the device is not low or full speed. 554 */ 555 #define TT_PORT(p) (((p) & 0xff) << 8) 556 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 557 558 /* dev_state bitmasks */ 559 /* USB device address - assigned by the HC */ 560 #define DEV_ADDR_MASK (0xff) 561 /* bits 8:26 reserved */ 562 /* Slot state */ 563 #define SLOT_STATE (0x1f << 27) 564 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 565 566 #define SLOT_STATE_DISABLED 0 567 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 568 #define SLOT_STATE_DEFAULT 1 569 #define SLOT_STATE_ADDRESSED 2 570 #define SLOT_STATE_CONFIGURED 3 571 572 /** 573 * struct xhci_ep_ctx 574 * @ep_info: endpoint state, streams, mult, and interval information. 575 * @ep_info2: information on endpoint type, max packet size, max burst size, 576 * error count, and whether the HC will force an event for all 577 * transactions. 578 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 579 * defines one stream, this points to the endpoint transfer ring. 580 * Otherwise, it points to a stream context array, which has a 581 * ring pointer for each flow. 582 * @tx_info: 583 * Average TRB lengths for the endpoint ring and 584 * max payload within an Endpoint Service Interval Time (ESIT). 585 * 586 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context 587 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes 588 * reserved at the end of the endpoint context for HC internal use. 589 */ 590 struct xhci_ep_ctx { 591 __le32 ep_info; 592 __le32 ep_info2; 593 __le64 deq; 594 __le32 tx_info; 595 /* offset 0x14 - 0x1f reserved for HC internal use */ 596 __le32 reserved[3]; 597 }; 598 599 /* ep_info bitmasks */ 600 /* 601 * Endpoint State - bits 0:2 602 * 0 - disabled 603 * 1 - running 604 * 2 - halted due to halt condition - ok to manipulate endpoint ring 605 * 3 - stopped 606 * 4 - TRB error 607 * 5-7 - reserved 608 */ 609 #define EP_STATE_MASK (0xf) 610 #define EP_STATE_DISABLED 0 611 #define EP_STATE_RUNNING 1 612 #define EP_STATE_HALTED 2 613 #define EP_STATE_STOPPED 3 614 #define EP_STATE_ERROR 4 615 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 616 #define EP_MULT(p) (((p) & 0x3) << 8) 617 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 618 /* bits 10:14 are Max Primary Streams */ 619 /* bit 15 is Linear Stream Array */ 620 /* Interval - period between requests to an endpoint - 125u increments. */ 621 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 622 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 623 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 624 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 625 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 626 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 627 #define EP_HAS_LSA (1 << 15) 628 629 /* ep_info2 bitmasks */ 630 /* 631 * Force Event - generate transfer events for all TRBs for this endpoint 632 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 633 */ 634 #define FORCE_EVENT (0x1) 635 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 636 #define ERROR_COUNT_SHIFT (1) 637 #define ERROR_COUNT_MASK (0x3) 638 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 639 #define EP_TYPE(p) ((p) << 3) 640 #define EP_TYPE_SHIFT (3) 641 #define ISOC_OUT_EP 1 642 #define BULK_OUT_EP 2 643 #define INT_OUT_EP 3 644 #define CTRL_EP 4 645 #define ISOC_IN_EP 5 646 #define BULK_IN_EP 6 647 #define INT_IN_EP 7 648 /* bit 6 reserved */ 649 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 650 #define MAX_BURST(p) (((p)&0xff) << 8) 651 #define MAX_BURST_MASK (0xff) 652 #define MAX_BURST_SHIFT (8) 653 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 654 #define MAX_PACKET(p) (((p)&0xffff) << 16) 655 #define MAX_PACKET_MASK (0xffff) 656 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 657 #define MAX_PACKET_SHIFT (16) 658 659 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 660 * USB2.0 spec 9.6.6. 661 */ 662 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 663 664 /* tx_info bitmasks */ 665 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 666 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 667 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 668 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 669 670 /* deq bitmasks */ 671 #define EP_CTX_CYCLE_MASK (1 << 0) 672 673 674 /** 675 * struct xhci_input_control_context 676 * Input control context; see section 6.2.5. 677 * 678 * @drop_context: set the bit of the endpoint context you want to disable 679 * @add_context: set the bit of the endpoint context you want to enable 680 */ 681 struct xhci_input_control_ctx { 682 volatile __le32 drop_flags; 683 volatile __le32 add_flags; 684 __le32 rsvd2[6]; 685 }; 686 687 688 /** 689 * struct xhci_device_context_array 690 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 691 */ 692 struct xhci_device_context_array { 693 /* 64-bit device addresses; we only write 32-bit addresses */ 694 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 695 }; 696 /* TODO: write function to set the 64-bit device DMA address */ 697 /* 698 * TODO: change this to be dynamically sized at HC mem init time since the HC 699 * might not be able to handle the maximum number of devices possible. 700 */ 701 702 703 struct xhci_transfer_event { 704 /* 64-bit buffer address, or immediate data */ 705 __le64 buffer; 706 __le32 transfer_len; 707 /* This field is interpreted differently based on the type of TRB */ 708 volatile __le32 flags; 709 }; 710 711 /* Transfer event TRB length bit mask */ 712 /* bits 0:23 */ 713 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 714 715 /** Transfer Event bit fields **/ 716 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 717 718 /* Completion Code - only applicable for some types of TRBs */ 719 #define COMP_CODE_MASK (0xff << 24) 720 #define COMP_CODE_SHIFT (24) 721 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 722 723 typedef enum { 724 COMP_SUCCESS = 1, 725 /* Data Buffer Error */ 726 COMP_DB_ERR, /* 2 */ 727 /* Babble Detected Error */ 728 COMP_BABBLE, /* 3 */ 729 /* USB Transaction Error */ 730 COMP_TX_ERR, /* 4 */ 731 /* TRB Error - some TRB field is invalid */ 732 COMP_TRB_ERR, /* 5 */ 733 /* Stall Error - USB device is stalled */ 734 COMP_STALL, /* 6 */ 735 /* Resource Error - HC doesn't have memory for that device configuration */ 736 COMP_ENOMEM, /* 7 */ 737 /* Bandwidth Error - not enough room in schedule for this dev config */ 738 COMP_BW_ERR, /* 8 */ 739 /* No Slots Available Error - HC ran out of device slots */ 740 COMP_ENOSLOTS, /* 9 */ 741 /* Invalid Stream Type Error */ 742 COMP_STREAM_ERR, /* 10 */ 743 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 744 COMP_EBADSLT, /* 11 */ 745 /* Endpoint Not Enabled Error */ 746 COMP_EBADEP,/* 12 */ 747 /* Short Packet */ 748 COMP_SHORT_TX, /* 13 */ 749 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 750 COMP_UNDERRUN, /* 14 */ 751 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 752 COMP_OVERRUN, /* 15 */ 753 /* Virtual Function Event Ring Full Error */ 754 COMP_VF_FULL, /* 16 */ 755 /* Parameter Error - Context parameter is invalid */ 756 COMP_EINVAL, /* 17 */ 757 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 758 COMP_BW_OVER,/* 18 */ 759 /* Context State Error - illegal context state transition requested */ 760 COMP_CTX_STATE,/* 19 */ 761 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 762 COMP_PING_ERR,/* 20 */ 763 /* Event Ring is full */ 764 COMP_ER_FULL,/* 21 */ 765 /* Incompatible Device Error */ 766 COMP_DEV_ERR,/* 22 */ 767 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 768 COMP_MISSED_INT,/* 23 */ 769 /* Successfully stopped command ring */ 770 COMP_CMD_STOP, /* 24 */ 771 /* Successfully aborted current command and stopped command ring */ 772 COMP_CMD_ABORT, /* 25 */ 773 /* Stopped - transfer was terminated by a stop endpoint command */ 774 COMP_STOP,/* 26 */ 775 /* Same as COMP_EP_STOPPED, but the transferred length in the event 776 * is invalid */ 777 COMP_STOP_INVAL, /* 27*/ 778 /* Control Abort Error - Debug Capability - control pipe aborted */ 779 COMP_DBG_ABORT, /* 28 */ 780 /* Max Exit Latency Too Large Error */ 781 COMP_MEL_ERR,/* 29 */ 782 /* TRB type 30 reserved */ 783 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 784 COMP_BUFF_OVER = 31, 785 /* Event Lost Error - xHC has an "internal event overrun condition" */ 786 COMP_ISSUES, /* 32 */ 787 /* Undefined Error - reported when other error codes don't apply */ 788 COMP_UNKNOWN, /* 33 */ 789 /* Invalid Stream ID Error */ 790 COMP_STRID_ERR, /* 34 */ 791 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 792 COMP_2ND_BW_ERR, /* 35 */ 793 /* Split Transaction Error */ 794 COMP_SPLIT_ERR /* 36 */ 795 796 } xhci_comp_code; 797 798 struct xhci_link_trb { 799 /* 64-bit segment pointer*/ 800 volatile __le64 segment_ptr; 801 volatile __le32 intr_target; 802 volatile __le32 control; 803 }; 804 805 /* control bitfields */ 806 #define LINK_TOGGLE (0x1 << 1) 807 808 /* Command completion event TRB */ 809 struct xhci_event_cmd { 810 /* Pointer to command TRB, or the value passed by the event data trb */ 811 volatile __le64 cmd_trb; 812 volatile __le32 status; 813 volatile __le32 flags; 814 }; 815 816 /* flags bitmasks */ 817 /* bits 16:23 are the virtual function ID */ 818 /* bits 24:31 are the slot ID */ 819 #define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) 820 #define TRB_TO_SLOT_ID_SHIFT (24) 821 #define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) 822 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 823 #define SLOT_ID_FOR_TRB_MASK (0xff) 824 #define SLOT_ID_FOR_TRB_SHIFT (24) 825 826 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 827 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 828 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 829 830 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 831 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 832 #define LAST_EP_INDEX 30 833 834 /* Set TR Dequeue Pointer command TRB fields */ 835 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 836 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 837 838 839 /* Port Status Change Event TRB fields */ 840 /* Port ID - bits 31:24 */ 841 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 842 #define PORT_ID_SHIFT (24) 843 #define PORT_ID_MASK (0xff << PORT_ID_SHIFT) 844 845 /* Normal TRB fields */ 846 /* transfer_len bitmasks - bits 0:16 */ 847 #define TRB_LEN(p) ((p) & 0x1ffff) 848 #define TRB_LEN_MASK (0x1ffff) 849 /* Interrupter Target - which MSI-X vector to target the completion event at */ 850 #define TRB_INTR_TARGET_SHIFT (22) 851 #define TRB_INTR_TARGET_MASK (0x3ff) 852 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 853 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 854 #define TRB_TBC(p) (((p) & 0x3) << 7) 855 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 856 857 /* Cycle bit - indicates TRB ownership by HC or HCD */ 858 #define TRB_CYCLE (1<<0) 859 /* 860 * Force next event data TRB to be evaluated before task switch. 861 * Used to pass OS data back after a TD completes. 862 */ 863 #define TRB_ENT (1<<1) 864 /* Interrupt on short packet */ 865 #define TRB_ISP (1<<2) 866 /* Set PCIe no snoop attribute */ 867 #define TRB_NO_SNOOP (1<<3) 868 /* Chain multiple TRBs into a TD */ 869 #define TRB_CHAIN (1<<4) 870 /* Interrupt on completion */ 871 #define TRB_IOC (1<<5) 872 /* The buffer pointer contains immediate data */ 873 #define TRB_IDT (1<<6) 874 875 /* Block Event Interrupt */ 876 #define TRB_BEI (1<<9) 877 878 /* Control transfer TRB specific fields */ 879 #define TRB_DIR_IN (1<<16) 880 #define TRB_TX_TYPE(p) ((p) << 16) 881 #define TRB_TX_TYPE_SHIFT (16) 882 #define TRB_DATA_OUT 2 883 #define TRB_DATA_IN 3 884 885 /* Isochronous TRB specific fields */ 886 #define TRB_SIA (1 << 31) 887 888 struct xhci_generic_trb { 889 volatile __le32 field[4]; 890 }; 891 892 union xhci_trb { 893 struct xhci_link_trb link; 894 struct xhci_transfer_event trans_event; 895 struct xhci_event_cmd event_cmd; 896 struct xhci_generic_trb generic; 897 }; 898 899 /* TRB bit mask */ 900 #define TRB_TYPE_BITMASK (0xfc00) 901 #define TRB_TYPE(p) ((p) << 10) 902 #define TRB_TYPE_SHIFT (10) 903 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 904 905 /* TRB type IDs */ 906 typedef enum { 907 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 908 TRB_NORMAL = 1, 909 /* setup stage for control transfers */ 910 TRB_SETUP, /* 2 */ 911 /* data stage for control transfers */ 912 TRB_DATA, /* 3 */ 913 /* status stage for control transfers */ 914 TRB_STATUS, /* 4 */ 915 /* isoc transfers */ 916 TRB_ISOC, /* 5 */ 917 /* TRB for linking ring segments */ 918 TRB_LINK, /* 6 */ 919 /* TRB for EVENT DATA */ 920 TRB_EVENT_DATA, /* 7 */ 921 /* Transfer Ring No-op (not for the command ring) */ 922 TRB_TR_NOOP, /* 8 */ 923 /* Command TRBs */ 924 /* Enable Slot Command */ 925 TRB_ENABLE_SLOT, /* 9 */ 926 /* Disable Slot Command */ 927 TRB_DISABLE_SLOT, /* 10 */ 928 /* Address Device Command */ 929 TRB_ADDR_DEV, /* 11 */ 930 /* Configure Endpoint Command */ 931 TRB_CONFIG_EP, /* 12 */ 932 /* Evaluate Context Command */ 933 TRB_EVAL_CONTEXT, /* 13 */ 934 /* Reset Endpoint Command */ 935 TRB_RESET_EP, /* 14 */ 936 /* Stop Transfer Ring Command */ 937 TRB_STOP_RING, /* 15 */ 938 /* Set Transfer Ring Dequeue Pointer Command */ 939 TRB_SET_DEQ, /* 16 */ 940 /* Reset Device Command */ 941 TRB_RESET_DEV, /* 17 */ 942 /* Force Event Command (opt) */ 943 TRB_FORCE_EVENT, /* 18 */ 944 /* Negotiate Bandwidth Command (opt) */ 945 TRB_NEG_BANDWIDTH, /* 19 */ 946 /* Set Latency Tolerance Value Command (opt) */ 947 TRB_SET_LT, /* 20 */ 948 /* Get port bandwidth Command */ 949 TRB_GET_BW, /* 21 */ 950 /* Force Header Command - generate a transaction or link management packet */ 951 TRB_FORCE_HEADER, /* 22 */ 952 /* No-op Command - not for transfer rings */ 953 TRB_CMD_NOOP, /* 23 */ 954 /* TRB IDs 24-31 reserved */ 955 /* Event TRBS */ 956 /* Transfer Event */ 957 TRB_TRANSFER = 32, 958 /* Command Completion Event */ 959 TRB_COMPLETION, /* 33 */ 960 /* Port Status Change Event */ 961 TRB_PORT_STATUS, /* 34 */ 962 /* Bandwidth Request Event (opt) */ 963 TRB_BANDWIDTH_EVENT, /* 35 */ 964 /* Doorbell Event (opt) */ 965 TRB_DOORBELL, /* 36 */ 966 /* Host Controller Event */ 967 TRB_HC_EVENT, /* 37 */ 968 /* Device Notification Event - device sent function wake notification */ 969 TRB_DEV_NOTE, /* 38 */ 970 /* MFINDEX Wrap Event - microframe counter wrapped */ 971 TRB_MFINDEX_WRAP, /* 39 */ 972 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 973 /* Nec vendor-specific command completion event. */ 974 TRB_NEC_CMD_COMP = 48, /* 48 */ 975 /* Get NEC firmware revision. */ 976 TRB_NEC_GET_FW, /* 49 */ 977 } trb_type; 978 979 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 980 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 981 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 982 cpu_to_le32(TRB_TYPE(TRB_LINK))) 983 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 984 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 985 986 /* 987 * TRBS_PER_SEGMENT must be a multiple of 4, 988 * since the command ring is 64-byte aligned. 989 * It must also be greater than 16. 990 */ 991 #define TRBS_PER_SEGMENT 64 992 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 993 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 994 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 995 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 996 * Change this if you change TRBS_PER_SEGMENT! 997 */ 998 #define SEGMENT_SHIFT 10 999 /* TRB buffer pointers can't cross 64KB boundaries */ 1000 #define TRB_MAX_BUFF_SHIFT 16 1001 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1002 1003 struct xhci_segment { 1004 union xhci_trb *trbs; 1005 /* private to HCD */ 1006 struct xhci_segment *next; 1007 }; 1008 1009 struct xhci_ring { 1010 struct xhci_segment *first_seg; 1011 union xhci_trb *enqueue; 1012 struct xhci_segment *enq_seg; 1013 union xhci_trb *dequeue; 1014 struct xhci_segment *deq_seg; 1015 /* 1016 * Write the cycle state into the TRB cycle field to give ownership of 1017 * the TRB to the host controller (if we are the producer), or to check 1018 * if we own the TRB (if we are the consumer). See section 4.9.1. 1019 */ 1020 volatile u32 cycle_state; 1021 unsigned int num_segs; 1022 }; 1023 1024 struct xhci_erst_entry { 1025 /* 64-bit event ring segment address */ 1026 __le64 seg_addr; 1027 __le32 seg_size; 1028 /* Set to zero */ 1029 __le32 rsvd; 1030 }; 1031 1032 struct xhci_erst { 1033 struct xhci_erst_entry *entries; 1034 unsigned int num_entries; 1035 /* Num entries the ERST can contain */ 1036 unsigned int erst_size; 1037 }; 1038 1039 struct xhci_scratchpad { 1040 u64 *sp_array; 1041 }; 1042 1043 /* 1044 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1045 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1046 * meaning 64 ring segments. 1047 * Initial allocated size of the ERST, in number of entries */ 1048 #define ERST_NUM_SEGS 1 1049 /* Initial number of event segment rings allocated */ 1050 #define ERST_ENTRIES 1 1051 /* Initial allocated size of the ERST, in number of entries */ 1052 #define ERST_SIZE 64 1053 /* Poll every 60 seconds */ 1054 #define POLL_TIMEOUT 60 1055 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1056 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1057 /* XXX: Make these module parameters */ 1058 1059 struct xhci_virt_ep { 1060 struct xhci_ring *ring; 1061 unsigned int ep_state; 1062 #define SET_DEQ_PENDING (1 << 0) 1063 #define EP_HALTED (1 << 1) /* For stall handling */ 1064 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 1065 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 1066 #define EP_GETTING_STREAMS (1 << 3) 1067 #define EP_HAS_STREAMS (1 << 4) 1068 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 1069 #define EP_GETTING_NO_STREAMS (1 << 5) 1070 }; 1071 1072 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 1073 1074 struct xhci_virt_device { 1075 struct usb_device *udev; 1076 /* 1077 * Commands to the hardware are passed an "input context" that 1078 * tells the hardware what to change in its data structures. 1079 * The hardware will return changes in an "output context" that 1080 * software must allocate for the hardware. We need to keep 1081 * track of input and output contexts separately because 1082 * these commands might fail and we don't trust the hardware. 1083 */ 1084 struct xhci_container_ctx *out_ctx; 1085 /* Used for addressing devices and configuration changes */ 1086 struct xhci_container_ctx *in_ctx; 1087 /* Rings saved to ensure old alt settings can be re-instated */ 1088 #define XHCI_MAX_RINGS_CACHED 31 1089 struct xhci_virt_ep eps[31]; 1090 }; 1091 1092 /* TODO: copied from ehci.h - can be refactored? */ 1093 /* xHCI spec says all registers are little endian */ 1094 static inline unsigned int xhci_readl(uint32_t volatile *regs) 1095 { 1096 return readl(regs); 1097 } 1098 1099 static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) 1100 { 1101 writel(val, regs); 1102 } 1103 1104 /* 1105 * Registers should always be accessed with double word or quad word accesses. 1106 * Some xHCI implementations may support 64-bit address pointers. Registers 1107 * with 64-bit address pointers should be written to with dword accesses by 1108 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1109 * xHCI implementations that do not support 64-bit address pointers will ignore 1110 * the high dword, and write order is irrelevant. 1111 */ 1112 static inline u64 xhci_readq(__le64 volatile *regs) 1113 { 1114 #if BITS_PER_LONG == 64 1115 return readq(regs); 1116 #else 1117 __u32 *ptr = (__u32 *)regs; 1118 u64 val_lo = readl(ptr); 1119 u64 val_hi = readl(ptr + 1); 1120 return val_lo + (val_hi << 32); 1121 #endif 1122 } 1123 1124 static inline void xhci_writeq(__le64 volatile *regs, const u64 val) 1125 { 1126 #if BITS_PER_LONG == 64 1127 writeq(val, regs); 1128 #else 1129 __u32 *ptr = (__u32 *)regs; 1130 u32 val_lo = lower_32_bits(val); 1131 /* FIXME */ 1132 u32 val_hi = upper_32_bits(val); 1133 writel(val_lo, ptr); 1134 writel(val_hi, ptr + 1); 1135 #endif 1136 } 1137 1138 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, 1139 struct xhci_hcor **ret_hcor); 1140 void xhci_hcd_stop(int index); 1141 1142 1143 /************************************************************* 1144 EXTENDED CAPABILITY DEFINITIONS 1145 *************************************************************/ 1146 /* Up to 16 ms to halt an HC */ 1147 #define XHCI_MAX_HALT_USEC (16*1000) 1148 /* HC not running - set to 1 when run/stop bit is cleared. */ 1149 #define XHCI_STS_HALT (1 << 0) 1150 1151 /* HCCPARAMS offset from PCI base address */ 1152 #define XHCI_HCC_PARAMS_OFFSET 0x10 1153 /* HCCPARAMS contains the first extended capability pointer */ 1154 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 1155 1156 /* Command and Status registers offset from the Operational Registers address */ 1157 #define XHCI_CMD_OFFSET 0x00 1158 #define XHCI_STS_OFFSET 0x04 1159 1160 #define XHCI_MAX_EXT_CAPS 50 1161 1162 /* Capability Register */ 1163 /* bits 7:0 - how long is the Capabilities register */ 1164 #define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) 1165 1166 /* Extended capability register fields */ 1167 #define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) 1168 #define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) 1169 #define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) 1170 /* Extended capability IDs - ID 0 reserved */ 1171 #define XHCI_EXT_CAPS_LEGACY 1 1172 #define XHCI_EXT_CAPS_PROTOCOL 2 1173 #define XHCI_EXT_CAPS_PM 3 1174 #define XHCI_EXT_CAPS_VIRT 4 1175 #define XHCI_EXT_CAPS_ROUTE 5 1176 /* IDs 6-9 reserved */ 1177 #define XHCI_EXT_CAPS_DEBUG 10 1178 /* USB Legacy Support Capability - section 7.1.1 */ 1179 #define XHCI_HC_BIOS_OWNED (1 << 16) 1180 #define XHCI_HC_OS_OWNED (1 << 24) 1181 1182 /* USB Legacy Support Capability - section 7.1.1 */ 1183 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1184 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 1185 1186 /* USB Legacy Support Control and Status Register - section 7.1.2 */ 1187 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1188 #define XHCI_LEGACY_CONTROL_OFFSET (0x04) 1189 /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 1190 #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 1191 1192 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 1193 #define XHCI_L1C (1 << 16) 1194 1195 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 1196 #define XHCI_HLC (1 << 19) 1197 1198 /* command register values to disable interrupts and halt the HC */ 1199 /* start/stop HC execution - do not write unless HC is halted*/ 1200 #define XHCI_CMD_RUN (1 << 0) 1201 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 1202 #define XHCI_CMD_EIE (1 << 2) 1203 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 1204 #define XHCI_CMD_HSEIE (1 << 3) 1205 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 1206 #define XHCI_CMD_EWE (1 << 10) 1207 1208 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 1209 1210 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 1211 #define XHCI_STS_CNR (1 << 11) 1212 1213 struct xhci_ctrl { 1214 #ifdef CONFIG_DM_USB 1215 struct udevice *dev; 1216 #endif 1217 struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ 1218 struct xhci_hcor *hcor; 1219 struct xhci_doorbell_array *dba; 1220 struct xhci_run_regs *run_regs; 1221 struct xhci_device_context_array *dcbaa \ 1222 __attribute__ ((aligned(ARCH_DMA_MINALIGN))); 1223 struct xhci_ring *event_ring; 1224 struct xhci_ring *cmd_ring; 1225 struct xhci_ring *transfer_ring; 1226 struct xhci_segment *seg; 1227 struct xhci_intr_reg *ir_set; 1228 struct xhci_erst erst; 1229 struct xhci_erst_entry entry[ERST_NUM_SEGS]; 1230 struct xhci_scratchpad *scratchpad; 1231 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1232 int rootdev; 1233 }; 1234 1235 unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); 1236 struct xhci_input_control_ctx 1237 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1238 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, 1239 struct xhci_container_ctx *ctx); 1240 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, 1241 struct xhci_container_ctx *ctx, 1242 unsigned int ep_index); 1243 void xhci_endpoint_copy(struct xhci_ctrl *ctrl, 1244 struct xhci_container_ctx *in_ctx, 1245 struct xhci_container_ctx *out_ctx, 1246 unsigned int ep_index); 1247 void xhci_slot_copy(struct xhci_ctrl *ctrl, 1248 struct xhci_container_ctx *in_ctx, 1249 struct xhci_container_ctx *out_ctx); 1250 void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, 1251 struct usb_device *udev, int hop_portnr); 1252 void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, 1253 u32 slot_id, u32 ep_index, trb_type cmd); 1254 void xhci_acknowledge_event(struct xhci_ctrl *ctrl); 1255 union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); 1256 int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, 1257 int length, void *buffer); 1258 int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, 1259 struct devrequest *req, int length, void *buffer); 1260 int xhci_check_maxpacket(struct usb_device *udev); 1261 void xhci_flush_cache(uintptr_t addr, u32 type_len); 1262 void xhci_inval_cache(uintptr_t addr, u32 type_len); 1263 void xhci_cleanup(struct xhci_ctrl *ctrl); 1264 struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs); 1265 int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id); 1266 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, 1267 struct xhci_hcor *hcor); 1268 1269 /** 1270 * xhci_deregister() - Unregister an XHCI controller 1271 * 1272 * @dev: Controller device 1273 * @return 0 if registered, -ve on error 1274 */ 1275 int xhci_deregister(struct udevice *dev); 1276 1277 /** 1278 * xhci_register() - Register a new XHCI controller 1279 * 1280 * @dev: Controller device 1281 * @hccr: Host controller control registers 1282 * @hcor: Not sure what this means 1283 * @return 0 if registered, -ve on error 1284 */ 1285 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1286 struct xhci_hcor *hcor); 1287 1288 extern struct dm_usb_ops xhci_usb_ops; 1289 1290 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); 1291 1292 #endif /* HOST_XHCI_H_ */ 1293