1 /* 2 * USB HOST XHCI Controller 3 * 4 * Based on xHCI host controller driver in linux-kernel 5 * by Sarah Sharp. 6 * 7 * Copyright (C) 2008 Intel Corp. 8 * Author: Sarah Sharp 9 * 10 * Copyright (C) 2013 Samsung Electronics Co.Ltd 11 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 12 * Vikas Sajjan <vikas.sajjan@samsung.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef HOST_XHCI_H_ 18 #define HOST_XHCI_H_ 19 20 #include <asm/types.h> 21 #include <asm/cache.h> 22 #include <asm/io.h> 23 #include <linux/list.h> 24 #include <linux/compat.h> 25 26 #define MAX_EP_CTX_NUM 31 27 #define XHCI_ALIGNMENT 64 28 /* Generic timeout for XHCI events */ 29 #define XHCI_TIMEOUT 5000 30 /* Max number of USB devices for any host controller - limit in section 6.1 */ 31 #define MAX_HC_SLOTS 256 32 /* Section 5.3.3 - MaxPorts */ 33 #define MAX_HC_PORTS 127 34 35 /* Up to 16 ms to halt an HC */ 36 #define XHCI_MAX_HALT_USEC (16*1000) 37 38 #define XHCI_MAX_RESET_USEC (250*1000) 39 40 /* 41 * These bits are Read Only (RO) and should be saved and written to the 42 * registers: 0, 3, 10:13, 30 43 * connect status, over-current status, port speed, and device removable. 44 * connect status and port speed are also sticky - meaning they're in 45 * the AUX well and they aren't changed by a hot, warm, or cold reset. 46 */ 47 #define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) 48 /* 49 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 50 * bits 5:8, 9, 14:15, 25:27 51 * link state, port power, port indicator state, "wake on" enable state 52 */ 53 #define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) 54 /* 55 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 56 * bit 4 (port reset) 57 */ 58 #define XHCI_PORT_RW1S ((1 << 4)) 59 /* 60 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 61 * bits 1, 17, 18, 19, 20, 21, 22, 23 62 * port enable/disable, and 63 * change bits: connect, PED, 64 * warm port reset changed (reserved zero for USB 2.0 ports), 65 * over-current, reset, link state, and L1 change 66 */ 67 #define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) 68 /* 69 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 70 * latched in 71 */ 72 #define XHCI_PORT_RW ((1 << 16)) 73 /* 74 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 75 * bits 2, 24, 28:31 76 */ 77 #define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) 78 79 /* 80 * XHCI Register Space. 81 */ 82 struct xhci_hccr { 83 uint32_t cr_capbase; 84 uint32_t cr_hcsparams1; 85 uint32_t cr_hcsparams2; 86 uint32_t cr_hcsparams3; 87 uint32_t cr_hccparams; 88 uint32_t cr_dboff; 89 uint32_t cr_rtsoff; 90 91 /* hc_capbase bitmasks */ 92 /* bits 7:0 - how long is the Capabilities register */ 93 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 94 /* bits 31:16 */ 95 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 96 97 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 98 /* bits 0:7, Max Device Slots */ 99 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 100 #define HCS_SLOTS_MASK 0xff 101 /* bits 8:18, Max Interrupters */ 102 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 103 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 104 #define HCS_MAX_PORTS_SHIFT 24 105 #define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT) 106 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 107 108 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 109 /* bits 0:3, frames or uframes that SW needs to queue transactions 110 * ahead of the HW to meet periodic deadlines */ 111 #define HCS_IST(p) (((p) >> 0) & 0xf) 112 /* bits 4:7, max number of Event Ring segments */ 113 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 114 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 115 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 116 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 117 118 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 119 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 120 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 121 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 122 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 123 124 /* HCCPARAMS - hcc_params - bitmasks */ 125 /* true: HC can use 64-bit address pointers */ 126 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 127 /* true: HC can do bandwidth negotiation */ 128 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 129 /* true: HC uses 64-byte Device Context structures 130 * FIXME 64-byte context structures aren't supported yet. 131 */ 132 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 133 /* true: HC has port power switches */ 134 #define HCC_PPC(p) ((p) & (1 << 3)) 135 /* true: HC has port indicators */ 136 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 137 /* true: HC has Light HC Reset Capability */ 138 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 139 /* true: HC supports latency tolerance messaging */ 140 #define HCC_LTC(p) ((p) & (1 << 6)) 141 /* true: no secondary Stream ID Support */ 142 #define HCC_NSS(p) ((p) & (1 << 7)) 143 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 144 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 145 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 146 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 147 148 /* db_off bitmask - bits 0:1 reserved */ 149 #define DBOFF_MASK (~0x3) 150 151 /* run_regs_off bitmask - bits 0:4 reserved */ 152 #define RTSOFF_MASK (~0x1f) 153 154 }; 155 156 struct xhci_hcor_port_regs { 157 volatile uint32_t or_portsc; 158 volatile uint32_t or_portpmsc; 159 volatile uint32_t or_portli; 160 volatile uint32_t reserved_3; 161 }; 162 163 struct xhci_hcor { 164 volatile uint32_t or_usbcmd; 165 volatile uint32_t or_usbsts; 166 volatile uint32_t or_pagesize; 167 volatile uint32_t reserved_0[2]; 168 volatile uint32_t or_dnctrl; 169 volatile uint64_t or_crcr; 170 volatile uint32_t reserved_1[4]; 171 volatile uint64_t or_dcbaap; 172 volatile uint32_t or_config; 173 volatile uint32_t reserved_2[241]; 174 struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS]; 175 176 uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254]; 177 }; 178 179 /* USBCMD - USB command - command bitmasks */ 180 /* start/stop HC execution - do not write unless HC is halted*/ 181 #define CMD_RUN XHCI_CMD_RUN 182 /* Reset HC - resets internal HC state machine and all registers (except 183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 184 * The xHCI driver must reinitialize the xHC after setting this bit. 185 */ 186 #define CMD_RESET (1 << 1) 187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 188 #define CMD_EIE XHCI_CMD_EIE 189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 190 #define CMD_HSEIE XHCI_CMD_HSEIE 191 /* bits 4:6 are reserved (and should be preserved on writes). */ 192 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 193 #define CMD_LRESET (1 << 7) 194 /* host controller save/restore state. */ 195 #define CMD_CSS (1 << 8) 196 #define CMD_CRS (1 << 9) 197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 198 #define CMD_EWE XHCI_CMD_EWE 199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 201 * '0' means the xHC can power it off if all ports are in the disconnect, 202 * disabled, or powered-off state. 203 */ 204 #define CMD_PM_INDEX (1 << 11) 205 /* bits 12:31 are reserved (and should be preserved on writes). */ 206 207 /* USBSTS - USB status - status bitmasks */ 208 /* HC not running - set to 1 when run/stop bit is cleared. */ 209 #define STS_HALT XHCI_STS_HALT 210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 211 #define STS_FATAL (1 << 2) 212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 213 #define STS_EINT (1 << 3) 214 /* port change detect */ 215 #define STS_PORT (1 << 4) 216 /* bits 5:7 reserved and zeroed */ 217 /* save state status - '1' means xHC is saving state */ 218 #define STS_SAVE (1 << 8) 219 /* restore state status - '1' means xHC is restoring state */ 220 #define STS_RESTORE (1 << 9) 221 /* true: save or restore error */ 222 #define STS_SRE (1 << 10) 223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 224 #define STS_CNR XHCI_STS_CNR 225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 226 #define STS_HCE (1 << 12) 227 /* bits 13:31 reserved and should be preserved */ 228 229 /* 230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 231 * Generate a device notification event when the HC sees a transaction with a 232 * notification type that matches a bit set in this bit field. 233 */ 234 #define DEV_NOTE_MASK (0xffff) 235 #define ENABLE_DEV_NOTE(x) (1 << (x)) 236 /* Most of the device notification types should only be used for debug. 237 * SW does need to pay attention to function wake notifications. 238 */ 239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 240 241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 242 /* bit 0 is the command ring cycle state */ 243 /* stop ring operation after completion of the currently executing command */ 244 #define CMD_RING_PAUSE (1 << 1) 245 /* stop ring immediately - abort the currently executing command */ 246 #define CMD_RING_ABORT (1 << 2) 247 /* true: command ring is running */ 248 #define CMD_RING_RUNNING (1 << 3) 249 /* bits 4:5 reserved and should be preserved */ 250 /* Command Ring pointer - bit mask for the lower 32 bits. */ 251 #define CMD_RING_RSVD_BITS (0x3f) 252 253 /* CONFIG - Configure Register - config_reg bitmasks */ 254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 255 #define MAX_DEVS(p) ((p) & 0xff) 256 /* bits 8:31 - reserved and should be preserved */ 257 258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 259 /* true: device connected */ 260 #define PORT_CONNECT (1 << 0) 261 /* true: port enabled */ 262 #define PORT_PE (1 << 1) 263 /* bit 2 reserved and zeroed */ 264 /* true: port has an over-current condition */ 265 #define PORT_OC (1 << 3) 266 /* true: port reset signaling asserted */ 267 #define PORT_RESET (1 << 4) 268 /* Port Link State - bits 5:8 269 * A read gives the current link PM state of the port, 270 * a write with Link State Write Strobe set sets the link state. 271 */ 272 #define PORT_PLS_MASK (0xf << 5) 273 #define XDEV_U0 (0x0 << 5) 274 #define XDEV_U2 (0x2 << 5) 275 #define XDEV_U3 (0x3 << 5) 276 #define XDEV_RESUME (0xf << 5) 277 /* true: port has power (see HCC_PPC) */ 278 #define PORT_POWER (1 << 9) 279 /* bits 10:13 indicate device speed: 280 * 0 - undefined speed - port hasn't be initialized by a reset yet 281 * 1 - full speed 282 * 2 - low speed 283 * 3 - high speed 284 * 4 - super speed 285 * 5-15 reserved 286 */ 287 #define DEV_SPEED_MASK (0xf << 10) 288 #define XDEV_FS (0x1 << 10) 289 #define XDEV_LS (0x2 << 10) 290 #define XDEV_HS (0x3 << 10) 291 #define XDEV_SS (0x4 << 10) 292 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 293 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 294 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 295 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 296 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 297 /* Bits 20:23 in the Slot Context are the speed for the device */ 298 #define SLOT_SPEED_FS (XDEV_FS << 10) 299 #define SLOT_SPEED_LS (XDEV_LS << 10) 300 #define SLOT_SPEED_HS (XDEV_HS << 10) 301 #define SLOT_SPEED_SS (XDEV_SS << 10) 302 /* Port Indicator Control */ 303 #define PORT_LED_OFF (0 << 14) 304 #define PORT_LED_AMBER (1 << 14) 305 #define PORT_LED_GREEN (2 << 14) 306 #define PORT_LED_MASK (3 << 14) 307 /* Port Link State Write Strobe - set this when changing link state */ 308 #define PORT_LINK_STROBE (1 << 16) 309 /* true: connect status change */ 310 #define PORT_CSC (1 << 17) 311 /* true: port enable change */ 312 #define PORT_PEC (1 << 18) 313 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 314 * into an enabled state, and the device into the default state. A "warm" reset 315 * also resets the link, forcing the device through the link training sequence. 316 * SW can also look at the Port Reset register to see when warm reset is done. 317 */ 318 #define PORT_WRC (1 << 19) 319 /* true: over-current change */ 320 #define PORT_OCC (1 << 20) 321 /* true: reset change - 1 to 0 transition of PORT_RESET */ 322 #define PORT_RC (1 << 21) 323 /* port link status change - set on some port link state transitions: 324 * Transition Reason 325 * -------------------------------------------------------------------------- 326 * - U3 to Resume Wakeup signaling from a device 327 * - Resume to Recovery to U0 USB 3.0 device resume 328 * - Resume to U0 USB 2.0 device resume 329 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 330 * - U3 to U0 Software resume of USB 2.0 device complete 331 * - U2 to U0 L1 resume of USB 2.1 device complete 332 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 333 * - U0 to disabled L1 entry error with USB 2.1 device 334 * - Any state to inactive Error on USB 3.0 port 335 */ 336 #define PORT_PLC (1 << 22) 337 /* port configure error change - port failed to configure its link partner */ 338 #define PORT_CEC (1 << 23) 339 /* bit 24 reserved */ 340 /* wake on connect (enable) */ 341 #define PORT_WKCONN_E (1 << 25) 342 /* wake on disconnect (enable) */ 343 #define PORT_WKDISC_E (1 << 26) 344 /* wake on over-current (enable) */ 345 #define PORT_WKOC_E (1 << 27) 346 /* bits 28:29 reserved */ 347 /* true: device is removable - for USB 3.0 roothub emulation */ 348 #define PORT_DEV_REMOVE (1 << 30) 349 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 350 #define PORT_WR (1 << 31) 351 352 /* We mark duplicate entries with -1 */ 353 #define DUPLICATE_ENTRY ((u8)(-1)) 354 355 /* Port Power Management Status and Control - port_power_base bitmasks */ 356 /* Inactivity timer value for transitions into U1, in microseconds. 357 * Timeout can be up to 127us. 0xFF means an infinite timeout. 358 */ 359 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 360 /* Inactivity timer value for transitions into U2 */ 361 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 362 /* Bits 24:31 for port testing */ 363 364 /* USB2 Protocol PORTSPMSC */ 365 #define PORT_L1S_MASK 7 366 #define PORT_L1S_SUCCESS 1 367 #define PORT_RWE (1 << 3) 368 #define PORT_HIRD(p) (((p) & 0xf) << 4) 369 #define PORT_HIRD_MASK (0xf << 4) 370 #define PORT_L1DS(p) (((p) & 0xff) << 8) 371 #define PORT_HLE (1 << 16) 372 373 /** 374 * struct xhci_intr_reg - Interrupt Register Set 375 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 376 * interrupts and check for pending interrupts. 377 * @irq_control: IMOD - Interrupt Moderation Register. 378 * Used to throttle interrupts. 379 * @erst_size: Number of segments in the 380 Event Ring Segment Table (ERST). 381 * @erst_base: ERST base address. 382 * @erst_dequeue: Event ring dequeue pointer. 383 * 384 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 385 * Ring Segment Table (ERST) associated with it. 386 * The event ring is comprised of multiple segments of the same size. 387 * The HC places events on the ring and "updates the Cycle bit in the TRBs to 388 * indicate to software the current position of the Enqueue Pointer." 389 * The HCD (Linux) processes those events and updates the dequeue pointer. 390 */ 391 struct xhci_intr_reg { 392 volatile __le32 irq_pending; 393 volatile __le32 irq_control; 394 volatile __le32 erst_size; 395 volatile __le32 rsvd; 396 volatile __le64 erst_base; 397 volatile __le64 erst_dequeue; 398 }; 399 400 /* irq_pending bitmasks */ 401 #define ER_IRQ_PENDING(p) ((p) & 0x1) 402 /* bits 2:31 need to be preserved */ 403 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 404 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 405 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 406 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 407 408 /* irq_control bitmasks */ 409 /* Minimum interval between interrupts (in 250ns intervals). The interval 410 * between interrupts will be longer if there are no events on the event ring. 411 * Default is 4000 (1 ms). 412 */ 413 #define ER_IRQ_INTERVAL_MASK (0xffff) 414 /* Counter used to count down the time to the next interrupt - HW use only */ 415 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 416 417 /* erst_size bitmasks */ 418 /* Preserve bits 16:31 of erst_size */ 419 #define ERST_SIZE_MASK (0xffff << 16) 420 421 /* erst_dequeue bitmasks */ 422 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 423 * where the current dequeue pointer lies. This is an optional HW hint. 424 */ 425 #define ERST_DESI_MASK (0x7) 426 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 427 * a work queue (or delayed service routine)? 428 */ 429 #define ERST_EHB (1 << 3) 430 #define ERST_PTR_MASK (0xf) 431 432 /** 433 * struct xhci_run_regs 434 * @microframe_index: MFINDEX - current microframe number 435 * 436 * Section 5.5 Host Controller Runtime Registers: 437 * "Software should read and write these registers using only Dword (32 bit) 438 * or larger accesses" 439 */ 440 struct xhci_run_regs { 441 __le32 microframe_index; 442 __le32 rsvd[7]; 443 struct xhci_intr_reg ir_set[128]; 444 }; 445 446 /** 447 * struct doorbell_array 448 * 449 * Bits 0 - 7: Endpoint target 450 * Bits 8 - 15: RsvdZ 451 * Bits 16 - 31: Stream ID 452 * 453 * Section 5.6 454 */ 455 struct xhci_doorbell_array { 456 volatile __le32 doorbell[256]; 457 }; 458 459 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 460 #define DB_VALUE_HOST 0x00000000 461 462 /** 463 * struct xhci_protocol_caps 464 * @revision: major revision, minor revision, capability ID, 465 * and next capability pointer. 466 * @name_string: Four ASCII characters to say which spec this xHC 467 * follows, typically "USB ". 468 * @port_info: Port offset, count, and protocol-defined information. 469 */ 470 struct xhci_protocol_caps { 471 u32 revision; 472 u32 name_string; 473 u32 port_info; 474 }; 475 476 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 477 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 478 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 479 480 /** 481 * struct xhci_container_ctx 482 * @type: Type of context. Used to calculated offsets to contained contexts. 483 * @size: Size of the context data 484 * @bytes: The raw context data given to HW 485 * @dma: dma address of the bytes 486 * 487 * Represents either a Device or Input context. Holds a pointer to the raw 488 * memory used for the context (bytes) and dma address of it (dma). 489 */ 490 struct xhci_container_ctx { 491 unsigned type; 492 #define XHCI_CTX_TYPE_DEVICE 0x1 493 #define XHCI_CTX_TYPE_INPUT 0x2 494 495 int size; 496 u8 *bytes; 497 }; 498 499 /** 500 * struct xhci_slot_ctx 501 * @dev_info: Route string, device speed, hub info, and last valid endpoint 502 * @dev_info2: Max exit latency for device number, root hub port number 503 * @tt_info: tt_info is used to construct split transaction tokens 504 * @dev_state: slot state and device address 505 * 506 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 507 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 508 * reserved at the end of the slot context for HC internal use. 509 */ 510 struct xhci_slot_ctx { 511 __le32 dev_info; 512 __le32 dev_info2; 513 __le32 tt_info; 514 __le32 dev_state; 515 /* offset 0x10 to 0x1f reserved for HC internal use */ 516 __le32 reserved[4]; 517 }; 518 519 /* dev_info bitmasks */ 520 /* Route String - 0:19 */ 521 #define ROUTE_STRING_MASK (0xfffff) 522 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 523 #define DEV_SPEED (0xf << 20) 524 /* bit 24 reserved */ 525 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 526 #define DEV_MTT (0x1 << 25) 527 /* Set if the device is a hub - bit 26 */ 528 #define DEV_HUB (0x1 << 26) 529 /* Index of the last valid endpoint context in this device context - 27:31 */ 530 #define LAST_CTX_MASK (0x1f << 27) 531 #define LAST_CTX(p) ((p) << 27) 532 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 533 #define SLOT_FLAG (1 << 0) 534 #define EP0_FLAG (1 << 1) 535 536 /* dev_info2 bitmasks */ 537 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 538 #define MAX_EXIT (0xffff) 539 /* Root hub port number that is needed to access the USB device */ 540 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 541 #define ROOT_HUB_PORT_MASK (0xff) 542 #define ROOT_HUB_PORT_SHIFT (16) 543 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 544 /* Maximum number of ports under a hub device */ 545 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 546 547 /* tt_info bitmasks */ 548 /* 549 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 550 * The Slot ID of the hub that isolates the high speed signaling from 551 * this low or full-speed device. '0' if attached to root hub port. 552 */ 553 #define TT_SLOT (0xff) 554 /* 555 * The number of the downstream facing port of the high-speed hub 556 * '0' if the device is not low or full speed. 557 */ 558 #define TT_PORT (0xff << 8) 559 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 560 561 /* dev_state bitmasks */ 562 /* USB device address - assigned by the HC */ 563 #define DEV_ADDR_MASK (0xff) 564 /* bits 8:26 reserved */ 565 /* Slot state */ 566 #define SLOT_STATE (0x1f << 27) 567 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 568 569 #define SLOT_STATE_DISABLED 0 570 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 571 #define SLOT_STATE_DEFAULT 1 572 #define SLOT_STATE_ADDRESSED 2 573 #define SLOT_STATE_CONFIGURED 3 574 575 /** 576 * struct xhci_ep_ctx 577 * @ep_info: endpoint state, streams, mult, and interval information. 578 * @ep_info2: information on endpoint type, max packet size, max burst size, 579 * error count, and whether the HC will force an event for all 580 * transactions. 581 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 582 * defines one stream, this points to the endpoint transfer ring. 583 * Otherwise, it points to a stream context array, which has a 584 * ring pointer for each flow. 585 * @tx_info: 586 * Average TRB lengths for the endpoint ring and 587 * max payload within an Endpoint Service Interval Time (ESIT). 588 * 589 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context 590 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes 591 * reserved at the end of the endpoint context for HC internal use. 592 */ 593 struct xhci_ep_ctx { 594 __le32 ep_info; 595 __le32 ep_info2; 596 __le64 deq; 597 __le32 tx_info; 598 /* offset 0x14 - 0x1f reserved for HC internal use */ 599 __le32 reserved[3]; 600 }; 601 602 /* ep_info bitmasks */ 603 /* 604 * Endpoint State - bits 0:2 605 * 0 - disabled 606 * 1 - running 607 * 2 - halted due to halt condition - ok to manipulate endpoint ring 608 * 3 - stopped 609 * 4 - TRB error 610 * 5-7 - reserved 611 */ 612 #define EP_STATE_MASK (0xf) 613 #define EP_STATE_DISABLED 0 614 #define EP_STATE_RUNNING 1 615 #define EP_STATE_HALTED 2 616 #define EP_STATE_STOPPED 3 617 #define EP_STATE_ERROR 4 618 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 619 #define EP_MULT(p) (((p) & 0x3) << 8) 620 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 621 /* bits 10:14 are Max Primary Streams */ 622 /* bit 15 is Linear Stream Array */ 623 /* Interval - period between requests to an endpoint - 125u increments. */ 624 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 625 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 626 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 627 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 628 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 629 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 630 #define EP_HAS_LSA (1 << 15) 631 632 /* ep_info2 bitmasks */ 633 /* 634 * Force Event - generate transfer events for all TRBs for this endpoint 635 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 636 */ 637 #define FORCE_EVENT (0x1) 638 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 639 #define ERROR_COUNT_SHIFT (1) 640 #define ERROR_COUNT_MASK (0x3) 641 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 642 #define EP_TYPE(p) ((p) << 3) 643 #define EP_TYPE_SHIFT (3) 644 #define ISOC_OUT_EP 1 645 #define BULK_OUT_EP 2 646 #define INT_OUT_EP 3 647 #define CTRL_EP 4 648 #define ISOC_IN_EP 5 649 #define BULK_IN_EP 6 650 #define INT_IN_EP 7 651 /* bit 6 reserved */ 652 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 653 #define MAX_BURST(p) (((p)&0xff) << 8) 654 #define MAX_BURST_MASK (0xff) 655 #define MAX_BURST_SHIFT (8) 656 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 657 #define MAX_PACKET(p) (((p)&0xffff) << 16) 658 #define MAX_PACKET_MASK (0xffff) 659 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 660 #define MAX_PACKET_SHIFT (16) 661 662 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 663 * USB2.0 spec 9.6.6. 664 */ 665 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 666 667 /* tx_info bitmasks */ 668 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 669 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 670 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 671 672 /* deq bitmasks */ 673 #define EP_CTX_CYCLE_MASK (1 << 0) 674 675 676 /** 677 * struct xhci_input_control_context 678 * Input control context; see section 6.2.5. 679 * 680 * @drop_context: set the bit of the endpoint context you want to disable 681 * @add_context: set the bit of the endpoint context you want to enable 682 */ 683 struct xhci_input_control_ctx { 684 volatile __le32 drop_flags; 685 volatile __le32 add_flags; 686 __le32 rsvd2[6]; 687 }; 688 689 690 /** 691 * struct xhci_device_context_array 692 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 693 */ 694 struct xhci_device_context_array { 695 /* 64-bit device addresses; we only write 32-bit addresses */ 696 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 697 }; 698 /* TODO: write function to set the 64-bit device DMA address */ 699 /* 700 * TODO: change this to be dynamically sized at HC mem init time since the HC 701 * might not be able to handle the maximum number of devices possible. 702 */ 703 704 705 struct xhci_transfer_event { 706 /* 64-bit buffer address, or immediate data */ 707 __le64 buffer; 708 __le32 transfer_len; 709 /* This field is interpreted differently based on the type of TRB */ 710 volatile __le32 flags; 711 }; 712 713 /* Transfer event TRB length bit mask */ 714 /* bits 0:23 */ 715 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 716 717 /** Transfer Event bit fields **/ 718 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 719 720 /* Completion Code - only applicable for some types of TRBs */ 721 #define COMP_CODE_MASK (0xff << 24) 722 #define COMP_CODE_SHIFT (24) 723 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 724 725 typedef enum { 726 COMP_SUCCESS = 1, 727 /* Data Buffer Error */ 728 COMP_DB_ERR, /* 2 */ 729 /* Babble Detected Error */ 730 COMP_BABBLE, /* 3 */ 731 /* USB Transaction Error */ 732 COMP_TX_ERR, /* 4 */ 733 /* TRB Error - some TRB field is invalid */ 734 COMP_TRB_ERR, /* 5 */ 735 /* Stall Error - USB device is stalled */ 736 COMP_STALL, /* 6 */ 737 /* Resource Error - HC doesn't have memory for that device configuration */ 738 COMP_ENOMEM, /* 7 */ 739 /* Bandwidth Error - not enough room in schedule for this dev config */ 740 COMP_BW_ERR, /* 8 */ 741 /* No Slots Available Error - HC ran out of device slots */ 742 COMP_ENOSLOTS, /* 9 */ 743 /* Invalid Stream Type Error */ 744 COMP_STREAM_ERR, /* 10 */ 745 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 746 COMP_EBADSLT, /* 11 */ 747 /* Endpoint Not Enabled Error */ 748 COMP_EBADEP,/* 12 */ 749 /* Short Packet */ 750 COMP_SHORT_TX, /* 13 */ 751 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 752 COMP_UNDERRUN, /* 14 */ 753 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 754 COMP_OVERRUN, /* 15 */ 755 /* Virtual Function Event Ring Full Error */ 756 COMP_VF_FULL, /* 16 */ 757 /* Parameter Error - Context parameter is invalid */ 758 COMP_EINVAL, /* 17 */ 759 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 760 COMP_BW_OVER,/* 18 */ 761 /* Context State Error - illegal context state transition requested */ 762 COMP_CTX_STATE,/* 19 */ 763 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 764 COMP_PING_ERR,/* 20 */ 765 /* Event Ring is full */ 766 COMP_ER_FULL,/* 21 */ 767 /* Incompatible Device Error */ 768 COMP_DEV_ERR,/* 22 */ 769 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 770 COMP_MISSED_INT,/* 23 */ 771 /* Successfully stopped command ring */ 772 COMP_CMD_STOP, /* 24 */ 773 /* Successfully aborted current command and stopped command ring */ 774 COMP_CMD_ABORT, /* 25 */ 775 /* Stopped - transfer was terminated by a stop endpoint command */ 776 COMP_STOP,/* 26 */ 777 /* Same as COMP_EP_STOPPED, but the transferred length in the event 778 * is invalid */ 779 COMP_STOP_INVAL, /* 27*/ 780 /* Control Abort Error - Debug Capability - control pipe aborted */ 781 COMP_DBG_ABORT, /* 28 */ 782 /* Max Exit Latency Too Large Error */ 783 COMP_MEL_ERR,/* 29 */ 784 /* TRB type 30 reserved */ 785 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 786 COMP_BUFF_OVER = 31, 787 /* Event Lost Error - xHC has an "internal event overrun condition" */ 788 COMP_ISSUES, /* 32 */ 789 /* Undefined Error - reported when other error codes don't apply */ 790 COMP_UNKNOWN, /* 33 */ 791 /* Invalid Stream ID Error */ 792 COMP_STRID_ERR, /* 34 */ 793 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 794 COMP_2ND_BW_ERR, /* 35 */ 795 /* Split Transaction Error */ 796 COMP_SPLIT_ERR /* 36 */ 797 798 } xhci_comp_code; 799 800 struct xhci_link_trb { 801 /* 64-bit segment pointer*/ 802 volatile __le64 segment_ptr; 803 volatile __le32 intr_target; 804 volatile __le32 control; 805 }; 806 807 /* control bitfields */ 808 #define LINK_TOGGLE (0x1 << 1) 809 810 /* Command completion event TRB */ 811 struct xhci_event_cmd { 812 /* Pointer to command TRB, or the value passed by the event data trb */ 813 volatile __le64 cmd_trb; 814 volatile __le32 status; 815 volatile __le32 flags; 816 }; 817 818 /* flags bitmasks */ 819 /* bits 16:23 are the virtual function ID */ 820 /* bits 24:31 are the slot ID */ 821 #define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) 822 #define TRB_TO_SLOT_ID_SHIFT (24) 823 #define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) 824 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 825 #define SLOT_ID_FOR_TRB_MASK (0xff) 826 #define SLOT_ID_FOR_TRB_SHIFT (24) 827 828 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 829 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 830 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 831 832 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 833 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 834 #define LAST_EP_INDEX 30 835 836 /* Set TR Dequeue Pointer command TRB fields */ 837 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 838 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 839 840 841 /* Port Status Change Event TRB fields */ 842 /* Port ID - bits 31:24 */ 843 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 844 #define PORT_ID_SHIFT (24) 845 #define PORT_ID_MASK (0xff << PORT_ID_SHIFT) 846 847 /* Normal TRB fields */ 848 /* transfer_len bitmasks - bits 0:16 */ 849 #define TRB_LEN(p) ((p) & 0x1ffff) 850 #define TRB_LEN_MASK (0x1ffff) 851 /* Interrupter Target - which MSI-X vector to target the completion event at */ 852 #define TRB_INTR_TARGET_SHIFT (22) 853 #define TRB_INTR_TARGET_MASK (0x3ff) 854 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 855 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 856 #define TRB_TBC(p) (((p) & 0x3) << 7) 857 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 858 859 /* Cycle bit - indicates TRB ownership by HC or HCD */ 860 #define TRB_CYCLE (1<<0) 861 /* 862 * Force next event data TRB to be evaluated before task switch. 863 * Used to pass OS data back after a TD completes. 864 */ 865 #define TRB_ENT (1<<1) 866 /* Interrupt on short packet */ 867 #define TRB_ISP (1<<2) 868 /* Set PCIe no snoop attribute */ 869 #define TRB_NO_SNOOP (1<<3) 870 /* Chain multiple TRBs into a TD */ 871 #define TRB_CHAIN (1<<4) 872 /* Interrupt on completion */ 873 #define TRB_IOC (1<<5) 874 /* The buffer pointer contains immediate data */ 875 #define TRB_IDT (1<<6) 876 877 /* Block Event Interrupt */ 878 #define TRB_BEI (1<<9) 879 880 /* Control transfer TRB specific fields */ 881 #define TRB_DIR_IN (1<<16) 882 #define TRB_TX_TYPE(p) ((p) << 16) 883 #define TRB_TX_TYPE_SHIFT (16) 884 #define TRB_DATA_OUT 2 885 #define TRB_DATA_IN 3 886 887 /* Isochronous TRB specific fields */ 888 #define TRB_SIA (1 << 31) 889 890 struct xhci_generic_trb { 891 volatile __le32 field[4]; 892 }; 893 894 union xhci_trb { 895 struct xhci_link_trb link; 896 struct xhci_transfer_event trans_event; 897 struct xhci_event_cmd event_cmd; 898 struct xhci_generic_trb generic; 899 }; 900 901 /* TRB bit mask */ 902 #define TRB_TYPE_BITMASK (0xfc00) 903 #define TRB_TYPE(p) ((p) << 10) 904 #define TRB_TYPE_SHIFT (10) 905 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 906 907 /* TRB type IDs */ 908 typedef enum { 909 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 910 TRB_NORMAL = 1, 911 /* setup stage for control transfers */ 912 TRB_SETUP, /* 2 */ 913 /* data stage for control transfers */ 914 TRB_DATA, /* 3 */ 915 /* status stage for control transfers */ 916 TRB_STATUS, /* 4 */ 917 /* isoc transfers */ 918 TRB_ISOC, /* 5 */ 919 /* TRB for linking ring segments */ 920 TRB_LINK, /* 6 */ 921 /* TRB for EVENT DATA */ 922 TRB_EVENT_DATA, /* 7 */ 923 /* Transfer Ring No-op (not for the command ring) */ 924 TRB_TR_NOOP, /* 8 */ 925 /* Command TRBs */ 926 /* Enable Slot Command */ 927 TRB_ENABLE_SLOT, /* 9 */ 928 /* Disable Slot Command */ 929 TRB_DISABLE_SLOT, /* 10 */ 930 /* Address Device Command */ 931 TRB_ADDR_DEV, /* 11 */ 932 /* Configure Endpoint Command */ 933 TRB_CONFIG_EP, /* 12 */ 934 /* Evaluate Context Command */ 935 TRB_EVAL_CONTEXT, /* 13 */ 936 /* Reset Endpoint Command */ 937 TRB_RESET_EP, /* 14 */ 938 /* Stop Transfer Ring Command */ 939 TRB_STOP_RING, /* 15 */ 940 /* Set Transfer Ring Dequeue Pointer Command */ 941 TRB_SET_DEQ, /* 16 */ 942 /* Reset Device Command */ 943 TRB_RESET_DEV, /* 17 */ 944 /* Force Event Command (opt) */ 945 TRB_FORCE_EVENT, /* 18 */ 946 /* Negotiate Bandwidth Command (opt) */ 947 TRB_NEG_BANDWIDTH, /* 19 */ 948 /* Set Latency Tolerance Value Command (opt) */ 949 TRB_SET_LT, /* 20 */ 950 /* Get port bandwidth Command */ 951 TRB_GET_BW, /* 21 */ 952 /* Force Header Command - generate a transaction or link management packet */ 953 TRB_FORCE_HEADER, /* 22 */ 954 /* No-op Command - not for transfer rings */ 955 TRB_CMD_NOOP, /* 23 */ 956 /* TRB IDs 24-31 reserved */ 957 /* Event TRBS */ 958 /* Transfer Event */ 959 TRB_TRANSFER = 32, 960 /* Command Completion Event */ 961 TRB_COMPLETION, /* 33 */ 962 /* Port Status Change Event */ 963 TRB_PORT_STATUS, /* 34 */ 964 /* Bandwidth Request Event (opt) */ 965 TRB_BANDWIDTH_EVENT, /* 35 */ 966 /* Doorbell Event (opt) */ 967 TRB_DOORBELL, /* 36 */ 968 /* Host Controller Event */ 969 TRB_HC_EVENT, /* 37 */ 970 /* Device Notification Event - device sent function wake notification */ 971 TRB_DEV_NOTE, /* 38 */ 972 /* MFINDEX Wrap Event - microframe counter wrapped */ 973 TRB_MFINDEX_WRAP, /* 39 */ 974 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 975 /* Nec vendor-specific command completion event. */ 976 TRB_NEC_CMD_COMP = 48, /* 48 */ 977 /* Get NEC firmware revision. */ 978 TRB_NEC_GET_FW, /* 49 */ 979 } trb_type; 980 981 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 982 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 983 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 984 cpu_to_le32(TRB_TYPE(TRB_LINK))) 985 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 986 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 987 988 /* 989 * TRBS_PER_SEGMENT must be a multiple of 4, 990 * since the command ring is 64-byte aligned. 991 * It must also be greater than 16. 992 */ 993 #define TRBS_PER_SEGMENT 64 994 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 995 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 996 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 997 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 998 * Change this if you change TRBS_PER_SEGMENT! 999 */ 1000 #define SEGMENT_SHIFT 10 1001 /* TRB buffer pointers can't cross 64KB boundaries */ 1002 #define TRB_MAX_BUFF_SHIFT 16 1003 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1004 1005 struct xhci_segment { 1006 union xhci_trb *trbs; 1007 /* private to HCD */ 1008 struct xhci_segment *next; 1009 }; 1010 1011 struct xhci_ring { 1012 struct xhci_segment *first_seg; 1013 union xhci_trb *enqueue; 1014 struct xhci_segment *enq_seg; 1015 union xhci_trb *dequeue; 1016 struct xhci_segment *deq_seg; 1017 /* 1018 * Write the cycle state into the TRB cycle field to give ownership of 1019 * the TRB to the host controller (if we are the producer), or to check 1020 * if we own the TRB (if we are the consumer). See section 4.9.1. 1021 */ 1022 volatile u32 cycle_state; 1023 unsigned int num_segs; 1024 }; 1025 1026 struct xhci_erst_entry { 1027 /* 64-bit event ring segment address */ 1028 __le64 seg_addr; 1029 __le32 seg_size; 1030 /* Set to zero */ 1031 __le32 rsvd; 1032 }; 1033 1034 struct xhci_erst { 1035 struct xhci_erst_entry *entries; 1036 unsigned int num_entries; 1037 /* Num entries the ERST can contain */ 1038 unsigned int erst_size; 1039 }; 1040 1041 /* 1042 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1043 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1044 * meaning 64 ring segments. 1045 * Initial allocated size of the ERST, in number of entries */ 1046 #define ERST_NUM_SEGS 3 1047 /* Initial number of event segment rings allocated */ 1048 #define ERST_ENTRIES 3 1049 /* Initial allocated size of the ERST, in number of entries */ 1050 #define ERST_SIZE 64 1051 /* Poll every 60 seconds */ 1052 #define POLL_TIMEOUT 60 1053 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1054 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1055 /* XXX: Make these module parameters */ 1056 1057 struct xhci_virt_ep { 1058 struct xhci_ring *ring; 1059 unsigned int ep_state; 1060 #define SET_DEQ_PENDING (1 << 0) 1061 #define EP_HALTED (1 << 1) /* For stall handling */ 1062 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 1063 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 1064 #define EP_GETTING_STREAMS (1 << 3) 1065 #define EP_HAS_STREAMS (1 << 4) 1066 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 1067 #define EP_GETTING_NO_STREAMS (1 << 5) 1068 }; 1069 1070 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 1071 1072 struct xhci_virt_device { 1073 struct usb_device *udev; 1074 /* 1075 * Commands to the hardware are passed an "input context" that 1076 * tells the hardware what to change in its data structures. 1077 * The hardware will return changes in an "output context" that 1078 * software must allocate for the hardware. We need to keep 1079 * track of input and output contexts separately because 1080 * these commands might fail and we don't trust the hardware. 1081 */ 1082 struct xhci_container_ctx *out_ctx; 1083 /* Used for addressing devices and configuration changes */ 1084 struct xhci_container_ctx *in_ctx; 1085 /* Rings saved to ensure old alt settings can be re-instated */ 1086 #define XHCI_MAX_RINGS_CACHED 31 1087 struct xhci_virt_ep eps[31]; 1088 }; 1089 1090 /* TODO: copied from ehci.h - can be refactored? */ 1091 /* xHCI spec says all registers are little endian */ 1092 static inline unsigned int xhci_readl(uint32_t volatile *regs) 1093 { 1094 return readl(regs); 1095 } 1096 1097 static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) 1098 { 1099 writel(val, regs); 1100 } 1101 1102 /* 1103 * Registers should always be accessed with double word or quad word accesses. 1104 * Some xHCI implementations may support 64-bit address pointers. Registers 1105 * with 64-bit address pointers should be written to with dword accesses by 1106 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1107 * xHCI implementations that do not support 64-bit address pointers will ignore 1108 * the high dword, and write order is irrelevant. 1109 */ 1110 static inline u64 xhci_readq(__le64 volatile *regs) 1111 { 1112 #if BITS_PER_LONG == 64 1113 return readq(regs); 1114 #else 1115 __u32 *ptr = (__u32 *)regs; 1116 u64 val_lo = readl(ptr); 1117 u64 val_hi = readl(ptr + 1); 1118 return val_lo + (val_hi << 32); 1119 #endif 1120 } 1121 1122 static inline void xhci_writeq(__le64 volatile *regs, const u64 val) 1123 { 1124 #if BITS_PER_LONG == 64 1125 writeq(val, regs); 1126 #else 1127 __u32 *ptr = (__u32 *)regs; 1128 u32 val_lo = lower_32_bits(val); 1129 /* FIXME */ 1130 u32 val_hi = upper_32_bits(val); 1131 writel(val_lo, ptr); 1132 writel(val_hi, ptr + 1); 1133 #endif 1134 } 1135 1136 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, 1137 struct xhci_hcor **ret_hcor); 1138 void xhci_hcd_stop(int index); 1139 1140 1141 /************************************************************* 1142 EXTENDED CAPABILITY DEFINITIONS 1143 *************************************************************/ 1144 /* Up to 16 ms to halt an HC */ 1145 #define XHCI_MAX_HALT_USEC (16*1000) 1146 /* HC not running - set to 1 when run/stop bit is cleared. */ 1147 #define XHCI_STS_HALT (1 << 0) 1148 1149 /* HCCPARAMS offset from PCI base address */ 1150 #define XHCI_HCC_PARAMS_OFFSET 0x10 1151 /* HCCPARAMS contains the first extended capability pointer */ 1152 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 1153 1154 /* Command and Status registers offset from the Operational Registers address */ 1155 #define XHCI_CMD_OFFSET 0x00 1156 #define XHCI_STS_OFFSET 0x04 1157 1158 #define XHCI_MAX_EXT_CAPS 50 1159 1160 /* Capability Register */ 1161 /* bits 7:0 - how long is the Capabilities register */ 1162 #define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) 1163 1164 /* Extended capability register fields */ 1165 #define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) 1166 #define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) 1167 #define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) 1168 /* Extended capability IDs - ID 0 reserved */ 1169 #define XHCI_EXT_CAPS_LEGACY 1 1170 #define XHCI_EXT_CAPS_PROTOCOL 2 1171 #define XHCI_EXT_CAPS_PM 3 1172 #define XHCI_EXT_CAPS_VIRT 4 1173 #define XHCI_EXT_CAPS_ROUTE 5 1174 /* IDs 6-9 reserved */ 1175 #define XHCI_EXT_CAPS_DEBUG 10 1176 /* USB Legacy Support Capability - section 7.1.1 */ 1177 #define XHCI_HC_BIOS_OWNED (1 << 16) 1178 #define XHCI_HC_OS_OWNED (1 << 24) 1179 1180 /* USB Legacy Support Capability - section 7.1.1 */ 1181 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1182 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 1183 1184 /* USB Legacy Support Control and Status Register - section 7.1.2 */ 1185 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1186 #define XHCI_LEGACY_CONTROL_OFFSET (0x04) 1187 /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 1188 #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 1189 1190 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 1191 #define XHCI_L1C (1 << 16) 1192 1193 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 1194 #define XHCI_HLC (1 << 19) 1195 1196 /* command register values to disable interrupts and halt the HC */ 1197 /* start/stop HC execution - do not write unless HC is halted*/ 1198 #define XHCI_CMD_RUN (1 << 0) 1199 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 1200 #define XHCI_CMD_EIE (1 << 2) 1201 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 1202 #define XHCI_CMD_HSEIE (1 << 3) 1203 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 1204 #define XHCI_CMD_EWE (1 << 10) 1205 1206 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 1207 1208 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 1209 #define XHCI_STS_CNR (1 << 11) 1210 1211 struct xhci_ctrl { 1212 #ifdef CONFIG_DM_USB 1213 struct udevice *dev; 1214 #endif 1215 struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ 1216 struct xhci_hcor *hcor; 1217 struct xhci_doorbell_array *dba; 1218 struct xhci_run_regs *run_regs; 1219 struct xhci_device_context_array *dcbaa \ 1220 __attribute__ ((aligned(ARCH_DMA_MINALIGN))); 1221 struct xhci_ring *event_ring; 1222 struct xhci_ring *cmd_ring; 1223 struct xhci_ring *transfer_ring; 1224 struct xhci_segment *seg; 1225 struct xhci_intr_reg *ir_set; 1226 struct xhci_erst erst; 1227 struct xhci_erst_entry entry[ERST_NUM_SEGS]; 1228 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1229 int rootdev; 1230 }; 1231 1232 unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); 1233 struct xhci_input_control_ctx 1234 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1235 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, 1236 struct xhci_container_ctx *ctx); 1237 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, 1238 struct xhci_container_ctx *ctx, 1239 unsigned int ep_index); 1240 void xhci_endpoint_copy(struct xhci_ctrl *ctrl, 1241 struct xhci_container_ctx *in_ctx, 1242 struct xhci_container_ctx *out_ctx, 1243 unsigned int ep_index); 1244 void xhci_slot_copy(struct xhci_ctrl *ctrl, 1245 struct xhci_container_ctx *in_ctx, 1246 struct xhci_container_ctx *out_ctx); 1247 void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, int slot_id, 1248 int speed, int hop_portnr); 1249 void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, 1250 u32 slot_id, u32 ep_index, trb_type cmd); 1251 void xhci_acknowledge_event(struct xhci_ctrl *ctrl); 1252 union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); 1253 int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, 1254 int length, void *buffer); 1255 int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, 1256 struct devrequest *req, int length, void *buffer); 1257 int xhci_check_maxpacket(struct usb_device *udev); 1258 void xhci_flush_cache(uintptr_t addr, u32 type_len); 1259 void xhci_inval_cache(uintptr_t addr, u32 type_len); 1260 void xhci_cleanup(struct xhci_ctrl *ctrl); 1261 struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs); 1262 int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id); 1263 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, 1264 struct xhci_hcor *hcor); 1265 1266 /** 1267 * xhci_deregister() - Unregister an XHCI controller 1268 * 1269 * @dev: Controller device 1270 * @return 0 if registered, -ve on error 1271 */ 1272 int xhci_deregister(struct udevice *dev); 1273 1274 /** 1275 * xhci_register() - Register a new XHCI controller 1276 * 1277 * @dev: Controller device 1278 * @hccr: Host controller control registers 1279 * @hcor: Not sure what this means 1280 * @return 0 if registered, -ve on error 1281 */ 1282 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1283 struct xhci_hcor *hcor); 1284 1285 extern struct dm_usb_ops xhci_usb_ops; 1286 1287 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); 1288 1289 #endif /* HOST_XHCI_H_ */ 1290