1 /* 2 * USB HOST XHCI Controller 3 * 4 * Based on xHCI host controller driver in linux-kernel 5 * by Sarah Sharp. 6 * 7 * Copyright (C) 2008 Intel Corp. 8 * Author: Sarah Sharp 9 * 10 * Copyright (C) 2013 Samsung Electronics Co.Ltd 11 * Authors: Vivek Gautam <gautam.vivek@samsung.com> 12 * Vikas Sajjan <vikas.sajjan@samsung.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef HOST_XHCI_H_ 18 #define HOST_XHCI_H_ 19 20 #include <asm/cache.h> 21 #include <asm/io.h> 22 #include <linux/list.h> 23 24 #define upper_32_bits(n) (u32)((n) >> 32) 25 #define lower_32_bits(n) (u32)(n) 26 27 #define MAX_EP_CTX_NUM 31 28 #define XHCI_ALIGNMENT 64 29 /* Generic timeout for XHCI events */ 30 #define XHCI_TIMEOUT 5000 31 /* Max number of USB devices for any host controller - limit in section 6.1 */ 32 #define MAX_HC_SLOTS 256 33 /* Section 5.3.3 - MaxPorts */ 34 #define MAX_HC_PORTS 127 35 36 /* Up to 16 ms to halt an HC */ 37 #define XHCI_MAX_HALT_USEC (16*1000) 38 39 #define XHCI_MAX_RESET_USEC (250*1000) 40 41 /* 42 * These bits are Read Only (RO) and should be saved and written to the 43 * registers: 0, 3, 10:13, 30 44 * connect status, over-current status, port speed, and device removable. 45 * connect status and port speed are also sticky - meaning they're in 46 * the AUX well and they aren't changed by a hot, warm, or cold reset. 47 */ 48 #define XHCI_PORT_RO ((1 << 0) | (1 << 3) | (0xf << 10) | (1 << 30)) 49 /* 50 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 51 * bits 5:8, 9, 14:15, 25:27 52 * link state, port power, port indicator state, "wake on" enable state 53 */ 54 #define XHCI_PORT_RWS ((0xf << 5) | (1 << 9) | (0x3 << 14) | (0x7 << 25)) 55 /* 56 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 57 * bit 4 (port reset) 58 */ 59 #define XHCI_PORT_RW1S ((1 << 4)) 60 /* 61 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 62 * bits 1, 17, 18, 19, 20, 21, 22, 23 63 * port enable/disable, and 64 * change bits: connect, PED, 65 * warm port reset changed (reserved zero for USB 2.0 ports), 66 * over-current, reset, link state, and L1 change 67 */ 68 #define XHCI_PORT_RW1CS ((1 << 1) | (0x7f << 17)) 69 /* 70 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 71 * latched in 72 */ 73 #define XHCI_PORT_RW ((1 << 16)) 74 /* 75 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 76 * bits 2, 24, 28:31 77 */ 78 #define XHCI_PORT_RZ ((1 << 2) | (1 << 24) | (0xf << 28)) 79 80 /* 81 * XHCI Register Space. 82 */ 83 struct xhci_hccr { 84 uint32_t cr_capbase; 85 uint32_t cr_hcsparams1; 86 uint32_t cr_hcsparams2; 87 uint32_t cr_hcsparams3; 88 uint32_t cr_hccparams; 89 uint32_t cr_dboff; 90 uint32_t cr_rtsoff; 91 92 /* hc_capbase bitmasks */ 93 /* bits 7:0 - how long is the Capabilities register */ 94 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 95 /* bits 31:16 */ 96 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 97 98 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 99 /* bits 0:7, Max Device Slots */ 100 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 101 #define HCS_SLOTS_MASK 0xff 102 /* bits 8:18, Max Interrupters */ 103 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 104 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 105 #define HCS_MAX_PORTS_SHIFT 24 106 #define HCS_MAX_PORTS_MASK (0x7f << HCS_MAX_PORTS_SHIFT) 107 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 108 109 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 110 /* bits 0:3, frames or uframes that SW needs to queue transactions 111 * ahead of the HW to meet periodic deadlines */ 112 #define HCS_IST(p) (((p) >> 0) & 0xf) 113 /* bits 4:7, max number of Event Ring segments */ 114 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 115 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 116 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ 117 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f) 118 119 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 120 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 121 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 122 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 123 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 124 125 /* HCCPARAMS - hcc_params - bitmasks */ 126 /* true: HC can use 64-bit address pointers */ 127 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 128 /* true: HC can do bandwidth negotiation */ 129 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 130 /* true: HC uses 64-byte Device Context structures 131 * FIXME 64-byte context structures aren't supported yet. 132 */ 133 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 134 /* true: HC has port power switches */ 135 #define HCC_PPC(p) ((p) & (1 << 3)) 136 /* true: HC has port indicators */ 137 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 138 /* true: HC has Light HC Reset Capability */ 139 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 140 /* true: HC supports latency tolerance messaging */ 141 #define HCC_LTC(p) ((p) & (1 << 6)) 142 /* true: no secondary Stream ID Support */ 143 #define HCC_NSS(p) ((p) & (1 << 7)) 144 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 145 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 146 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 147 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 148 149 /* db_off bitmask - bits 0:1 reserved */ 150 #define DBOFF_MASK (~0x3) 151 152 /* run_regs_off bitmask - bits 0:4 reserved */ 153 #define RTSOFF_MASK (~0x1f) 154 155 }; 156 157 struct xhci_hcor_port_regs { 158 volatile uint32_t or_portsc; 159 volatile uint32_t or_portpmsc; 160 volatile uint32_t or_portli; 161 volatile uint32_t reserved_3; 162 }; 163 164 struct xhci_hcor { 165 volatile uint32_t or_usbcmd; 166 volatile uint32_t or_usbsts; 167 volatile uint32_t or_pagesize; 168 volatile uint32_t reserved_0[2]; 169 volatile uint32_t or_dnctrl; 170 volatile uint64_t or_crcr; 171 volatile uint32_t reserved_1[4]; 172 volatile uint64_t or_dcbaap; 173 volatile uint32_t or_config; 174 volatile uint32_t reserved_2[241]; 175 struct xhci_hcor_port_regs portregs[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS]; 176 177 uint32_t reserved_4[CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS * 254]; 178 }; 179 180 /* USBCMD - USB command - command bitmasks */ 181 /* start/stop HC execution - do not write unless HC is halted*/ 182 #define CMD_RUN XHCI_CMD_RUN 183 /* Reset HC - resets internal HC state machine and all registers (except 184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 185 * The xHCI driver must reinitialize the xHC after setting this bit. 186 */ 187 #define CMD_RESET (1 << 1) 188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 189 #define CMD_EIE XHCI_CMD_EIE 190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 191 #define CMD_HSEIE XHCI_CMD_HSEIE 192 /* bits 4:6 are reserved (and should be preserved on writes). */ 193 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 194 #define CMD_LRESET (1 << 7) 195 /* host controller save/restore state. */ 196 #define CMD_CSS (1 << 8) 197 #define CMD_CRS (1 << 9) 198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 199 #define CMD_EWE XHCI_CMD_EWE 200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 202 * '0' means the xHC can power it off if all ports are in the disconnect, 203 * disabled, or powered-off state. 204 */ 205 #define CMD_PM_INDEX (1 << 11) 206 /* bits 12:31 are reserved (and should be preserved on writes). */ 207 208 /* USBSTS - USB status - status bitmasks */ 209 /* HC not running - set to 1 when run/stop bit is cleared. */ 210 #define STS_HALT XHCI_STS_HALT 211 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 212 #define STS_FATAL (1 << 2) 213 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 214 #define STS_EINT (1 << 3) 215 /* port change detect */ 216 #define STS_PORT (1 << 4) 217 /* bits 5:7 reserved and zeroed */ 218 /* save state status - '1' means xHC is saving state */ 219 #define STS_SAVE (1 << 8) 220 /* restore state status - '1' means xHC is restoring state */ 221 #define STS_RESTORE (1 << 9) 222 /* true: save or restore error */ 223 #define STS_SRE (1 << 10) 224 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 225 #define STS_CNR XHCI_STS_CNR 226 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 227 #define STS_HCE (1 << 12) 228 /* bits 13:31 reserved and should be preserved */ 229 230 /* 231 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 232 * Generate a device notification event when the HC sees a transaction with a 233 * notification type that matches a bit set in this bit field. 234 */ 235 #define DEV_NOTE_MASK (0xffff) 236 #define ENABLE_DEV_NOTE(x) (1 << (x)) 237 /* Most of the device notification types should only be used for debug. 238 * SW does need to pay attention to function wake notifications. 239 */ 240 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 241 242 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 243 /* bit 0 is the command ring cycle state */ 244 /* stop ring operation after completion of the currently executing command */ 245 #define CMD_RING_PAUSE (1 << 1) 246 /* stop ring immediately - abort the currently executing command */ 247 #define CMD_RING_ABORT (1 << 2) 248 /* true: command ring is running */ 249 #define CMD_RING_RUNNING (1 << 3) 250 /* bits 4:5 reserved and should be preserved */ 251 /* Command Ring pointer - bit mask for the lower 32 bits. */ 252 #define CMD_RING_RSVD_BITS (0x3f) 253 254 /* CONFIG - Configure Register - config_reg bitmasks */ 255 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 256 #define MAX_DEVS(p) ((p) & 0xff) 257 /* bits 8:31 - reserved and should be preserved */ 258 259 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 260 /* true: device connected */ 261 #define PORT_CONNECT (1 << 0) 262 /* true: port enabled */ 263 #define PORT_PE (1 << 1) 264 /* bit 2 reserved and zeroed */ 265 /* true: port has an over-current condition */ 266 #define PORT_OC (1 << 3) 267 /* true: port reset signaling asserted */ 268 #define PORT_RESET (1 << 4) 269 /* Port Link State - bits 5:8 270 * A read gives the current link PM state of the port, 271 * a write with Link State Write Strobe set sets the link state. 272 */ 273 #define PORT_PLS_MASK (0xf << 5) 274 #define XDEV_U0 (0x0 << 5) 275 #define XDEV_U2 (0x2 << 5) 276 #define XDEV_U3 (0x3 << 5) 277 #define XDEV_RESUME (0xf << 5) 278 /* true: port has power (see HCC_PPC) */ 279 #define PORT_POWER (1 << 9) 280 /* bits 10:13 indicate device speed: 281 * 0 - undefined speed - port hasn't be initialized by a reset yet 282 * 1 - full speed 283 * 2 - low speed 284 * 3 - high speed 285 * 4 - super speed 286 * 5-15 reserved 287 */ 288 #define DEV_SPEED_MASK (0xf << 10) 289 #define XDEV_FS (0x1 << 10) 290 #define XDEV_LS (0x2 << 10) 291 #define XDEV_HS (0x3 << 10) 292 #define XDEV_SS (0x4 << 10) 293 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 294 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 295 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 296 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 297 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 298 /* Bits 20:23 in the Slot Context are the speed for the device */ 299 #define SLOT_SPEED_FS (XDEV_FS << 10) 300 #define SLOT_SPEED_LS (XDEV_LS << 10) 301 #define SLOT_SPEED_HS (XDEV_HS << 10) 302 #define SLOT_SPEED_SS (XDEV_SS << 10) 303 /* Port Indicator Control */ 304 #define PORT_LED_OFF (0 << 14) 305 #define PORT_LED_AMBER (1 << 14) 306 #define PORT_LED_GREEN (2 << 14) 307 #define PORT_LED_MASK (3 << 14) 308 /* Port Link State Write Strobe - set this when changing link state */ 309 #define PORT_LINK_STROBE (1 << 16) 310 /* true: connect status change */ 311 #define PORT_CSC (1 << 17) 312 /* true: port enable change */ 313 #define PORT_PEC (1 << 18) 314 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 315 * into an enabled state, and the device into the default state. A "warm" reset 316 * also resets the link, forcing the device through the link training sequence. 317 * SW can also look at the Port Reset register to see when warm reset is done. 318 */ 319 #define PORT_WRC (1 << 19) 320 /* true: over-current change */ 321 #define PORT_OCC (1 << 20) 322 /* true: reset change - 1 to 0 transition of PORT_RESET */ 323 #define PORT_RC (1 << 21) 324 /* port link status change - set on some port link state transitions: 325 * Transition Reason 326 * -------------------------------------------------------------------------- 327 * - U3 to Resume Wakeup signaling from a device 328 * - Resume to Recovery to U0 USB 3.0 device resume 329 * - Resume to U0 USB 2.0 device resume 330 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 331 * - U3 to U0 Software resume of USB 2.0 device complete 332 * - U2 to U0 L1 resume of USB 2.1 device complete 333 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 334 * - U0 to disabled L1 entry error with USB 2.1 device 335 * - Any state to inactive Error on USB 3.0 port 336 */ 337 #define PORT_PLC (1 << 22) 338 /* port configure error change - port failed to configure its link partner */ 339 #define PORT_CEC (1 << 23) 340 /* bit 24 reserved */ 341 /* wake on connect (enable) */ 342 #define PORT_WKCONN_E (1 << 25) 343 /* wake on disconnect (enable) */ 344 #define PORT_WKDISC_E (1 << 26) 345 /* wake on over-current (enable) */ 346 #define PORT_WKOC_E (1 << 27) 347 /* bits 28:29 reserved */ 348 /* true: device is removable - for USB 3.0 roothub emulation */ 349 #define PORT_DEV_REMOVE (1 << 30) 350 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 351 #define PORT_WR (1 << 31) 352 353 /* We mark duplicate entries with -1 */ 354 #define DUPLICATE_ENTRY ((u8)(-1)) 355 356 /* Port Power Management Status and Control - port_power_base bitmasks */ 357 /* Inactivity timer value for transitions into U1, in microseconds. 358 * Timeout can be up to 127us. 0xFF means an infinite timeout. 359 */ 360 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 361 /* Inactivity timer value for transitions into U2 */ 362 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 363 /* Bits 24:31 for port testing */ 364 365 /* USB2 Protocol PORTSPMSC */ 366 #define PORT_L1S_MASK 7 367 #define PORT_L1S_SUCCESS 1 368 #define PORT_RWE (1 << 3) 369 #define PORT_HIRD(p) (((p) & 0xf) << 4) 370 #define PORT_HIRD_MASK (0xf << 4) 371 #define PORT_L1DS(p) (((p) & 0xff) << 8) 372 #define PORT_HLE (1 << 16) 373 374 /** 375 * struct xhci_intr_reg - Interrupt Register Set 376 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 377 * interrupts and check for pending interrupts. 378 * @irq_control: IMOD - Interrupt Moderation Register. 379 * Used to throttle interrupts. 380 * @erst_size: Number of segments in the 381 Event Ring Segment Table (ERST). 382 * @erst_base: ERST base address. 383 * @erst_dequeue: Event ring dequeue pointer. 384 * 385 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 386 * Ring Segment Table (ERST) associated with it. 387 * The event ring is comprised of multiple segments of the same size. 388 * The HC places events on the ring and "updates the Cycle bit in the TRBs to 389 * indicate to software the current position of the Enqueue Pointer." 390 * The HCD (Linux) processes those events and updates the dequeue pointer. 391 */ 392 struct xhci_intr_reg { 393 volatile __le32 irq_pending; 394 volatile __le32 irq_control; 395 volatile __le32 erst_size; 396 volatile __le32 rsvd; 397 volatile __le64 erst_base; 398 volatile __le64 erst_dequeue; 399 }; 400 401 /* irq_pending bitmasks */ 402 #define ER_IRQ_PENDING(p) ((p) & 0x1) 403 /* bits 2:31 need to be preserved */ 404 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 405 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 406 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 407 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 408 409 /* irq_control bitmasks */ 410 /* Minimum interval between interrupts (in 250ns intervals). The interval 411 * between interrupts will be longer if there are no events on the event ring. 412 * Default is 4000 (1 ms). 413 */ 414 #define ER_IRQ_INTERVAL_MASK (0xffff) 415 /* Counter used to count down the time to the next interrupt - HW use only */ 416 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 417 418 /* erst_size bitmasks */ 419 /* Preserve bits 16:31 of erst_size */ 420 #define ERST_SIZE_MASK (0xffff << 16) 421 422 /* erst_dequeue bitmasks */ 423 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 424 * where the current dequeue pointer lies. This is an optional HW hint. 425 */ 426 #define ERST_DESI_MASK (0x7) 427 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 428 * a work queue (or delayed service routine)? 429 */ 430 #define ERST_EHB (1 << 3) 431 #define ERST_PTR_MASK (0xf) 432 433 /** 434 * struct xhci_run_regs 435 * @microframe_index: MFINDEX - current microframe number 436 * 437 * Section 5.5 Host Controller Runtime Registers: 438 * "Software should read and write these registers using only Dword (32 bit) 439 * or larger accesses" 440 */ 441 struct xhci_run_regs { 442 __le32 microframe_index; 443 __le32 rsvd[7]; 444 struct xhci_intr_reg ir_set[128]; 445 }; 446 447 /** 448 * struct doorbell_array 449 * 450 * Bits 0 - 7: Endpoint target 451 * Bits 8 - 15: RsvdZ 452 * Bits 16 - 31: Stream ID 453 * 454 * Section 5.6 455 */ 456 struct xhci_doorbell_array { 457 volatile __le32 doorbell[256]; 458 }; 459 460 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 461 #define DB_VALUE_HOST 0x00000000 462 463 /** 464 * struct xhci_protocol_caps 465 * @revision: major revision, minor revision, capability ID, 466 * and next capability pointer. 467 * @name_string: Four ASCII characters to say which spec this xHC 468 * follows, typically "USB ". 469 * @port_info: Port offset, count, and protocol-defined information. 470 */ 471 struct xhci_protocol_caps { 472 u32 revision; 473 u32 name_string; 474 u32 port_info; 475 }; 476 477 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 478 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 479 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 480 481 /** 482 * struct xhci_container_ctx 483 * @type: Type of context. Used to calculated offsets to contained contexts. 484 * @size: Size of the context data 485 * @bytes: The raw context data given to HW 486 * @dma: dma address of the bytes 487 * 488 * Represents either a Device or Input context. Holds a pointer to the raw 489 * memory used for the context (bytes) and dma address of it (dma). 490 */ 491 struct xhci_container_ctx { 492 unsigned type; 493 #define XHCI_CTX_TYPE_DEVICE 0x1 494 #define XHCI_CTX_TYPE_INPUT 0x2 495 496 int size; 497 u8 *bytes; 498 }; 499 500 /** 501 * struct xhci_slot_ctx 502 * @dev_info: Route string, device speed, hub info, and last valid endpoint 503 * @dev_info2: Max exit latency for device number, root hub port number 504 * @tt_info: tt_info is used to construct split transaction tokens 505 * @dev_state: slot state and device address 506 * 507 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 508 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 509 * reserved at the end of the slot context for HC internal use. 510 */ 511 struct xhci_slot_ctx { 512 __le32 dev_info; 513 __le32 dev_info2; 514 __le32 tt_info; 515 __le32 dev_state; 516 /* offset 0x10 to 0x1f reserved for HC internal use */ 517 __le32 reserved[4]; 518 }; 519 520 /* dev_info bitmasks */ 521 /* Route String - 0:19 */ 522 #define ROUTE_STRING_MASK (0xfffff) 523 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 524 #define DEV_SPEED (0xf << 20) 525 /* bit 24 reserved */ 526 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 527 #define DEV_MTT (0x1 << 25) 528 /* Set if the device is a hub - bit 26 */ 529 #define DEV_HUB (0x1 << 26) 530 /* Index of the last valid endpoint context in this device context - 27:31 */ 531 #define LAST_CTX_MASK (0x1f << 27) 532 #define LAST_CTX(p) ((p) << 27) 533 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 534 #define SLOT_FLAG (1 << 0) 535 #define EP0_FLAG (1 << 1) 536 537 /* dev_info2 bitmasks */ 538 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 539 #define MAX_EXIT (0xffff) 540 /* Root hub port number that is needed to access the USB device */ 541 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 542 #define ROOT_HUB_PORT_MASK (0xff) 543 #define ROOT_HUB_PORT_SHIFT (16) 544 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 545 /* Maximum number of ports under a hub device */ 546 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 547 548 /* tt_info bitmasks */ 549 /* 550 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 551 * The Slot ID of the hub that isolates the high speed signaling from 552 * this low or full-speed device. '0' if attached to root hub port. 553 */ 554 #define TT_SLOT (0xff) 555 /* 556 * The number of the downstream facing port of the high-speed hub 557 * '0' if the device is not low or full speed. 558 */ 559 #define TT_PORT (0xff << 8) 560 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 561 562 /* dev_state bitmasks */ 563 /* USB device address - assigned by the HC */ 564 #define DEV_ADDR_MASK (0xff) 565 /* bits 8:26 reserved */ 566 /* Slot state */ 567 #define SLOT_STATE (0x1f << 27) 568 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 569 570 #define SLOT_STATE_DISABLED 0 571 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 572 #define SLOT_STATE_DEFAULT 1 573 #define SLOT_STATE_ADDRESSED 2 574 #define SLOT_STATE_CONFIGURED 3 575 576 /** 577 * struct xhci_ep_ctx 578 * @ep_info: endpoint state, streams, mult, and interval information. 579 * @ep_info2: information on endpoint type, max packet size, max burst size, 580 * error count, and whether the HC will force an event for all 581 * transactions. 582 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 583 * defines one stream, this points to the endpoint transfer ring. 584 * Otherwise, it points to a stream context array, which has a 585 * ring pointer for each flow. 586 * @tx_info: 587 * Average TRB lengths for the endpoint ring and 588 * max payload within an Endpoint Service Interval Time (ESIT). 589 * 590 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context 591 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes 592 * reserved at the end of the endpoint context for HC internal use. 593 */ 594 struct xhci_ep_ctx { 595 __le32 ep_info; 596 __le32 ep_info2; 597 __le64 deq; 598 __le32 tx_info; 599 /* offset 0x14 - 0x1f reserved for HC internal use */ 600 __le32 reserved[3]; 601 }; 602 603 /* ep_info bitmasks */ 604 /* 605 * Endpoint State - bits 0:2 606 * 0 - disabled 607 * 1 - running 608 * 2 - halted due to halt condition - ok to manipulate endpoint ring 609 * 3 - stopped 610 * 4 - TRB error 611 * 5-7 - reserved 612 */ 613 #define EP_STATE_MASK (0xf) 614 #define EP_STATE_DISABLED 0 615 #define EP_STATE_RUNNING 1 616 #define EP_STATE_HALTED 2 617 #define EP_STATE_STOPPED 3 618 #define EP_STATE_ERROR 4 619 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 620 #define EP_MULT(p) (((p) & 0x3) << 8) 621 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 622 /* bits 10:14 are Max Primary Streams */ 623 /* bit 15 is Linear Stream Array */ 624 /* Interval - period between requests to an endpoint - 125u increments. */ 625 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 626 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 627 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 628 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 629 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 630 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 631 #define EP_HAS_LSA (1 << 15) 632 633 /* ep_info2 bitmasks */ 634 /* 635 * Force Event - generate transfer events for all TRBs for this endpoint 636 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 637 */ 638 #define FORCE_EVENT (0x1) 639 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 640 #define ERROR_COUNT_SHIFT (1) 641 #define ERROR_COUNT_MASK (0x3) 642 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 643 #define EP_TYPE(p) ((p) << 3) 644 #define EP_TYPE_SHIFT (3) 645 #define ISOC_OUT_EP 1 646 #define BULK_OUT_EP 2 647 #define INT_OUT_EP 3 648 #define CTRL_EP 4 649 #define ISOC_IN_EP 5 650 #define BULK_IN_EP 6 651 #define INT_IN_EP 7 652 /* bit 6 reserved */ 653 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 654 #define MAX_BURST(p) (((p)&0xff) << 8) 655 #define MAX_BURST_MASK (0xff) 656 #define MAX_BURST_SHIFT (8) 657 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 658 #define MAX_PACKET(p) (((p)&0xffff) << 16) 659 #define MAX_PACKET_MASK (0xffff) 660 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 661 #define MAX_PACKET_SHIFT (16) 662 663 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 664 * USB2.0 spec 9.6.6. 665 */ 666 #define GET_MAX_PACKET(p) ((p) & 0x7ff) 667 668 /* tx_info bitmasks */ 669 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 670 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 671 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 672 673 /* deq bitmasks */ 674 #define EP_CTX_CYCLE_MASK (1 << 0) 675 676 677 /** 678 * struct xhci_input_control_context 679 * Input control context; see section 6.2.5. 680 * 681 * @drop_context: set the bit of the endpoint context you want to disable 682 * @add_context: set the bit of the endpoint context you want to enable 683 */ 684 struct xhci_input_control_ctx { 685 volatile __le32 drop_flags; 686 volatile __le32 add_flags; 687 __le32 rsvd2[6]; 688 }; 689 690 691 /** 692 * struct xhci_device_context_array 693 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 694 */ 695 struct xhci_device_context_array { 696 /* 64-bit device addresses; we only write 32-bit addresses */ 697 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 698 }; 699 /* TODO: write function to set the 64-bit device DMA address */ 700 /* 701 * TODO: change this to be dynamically sized at HC mem init time since the HC 702 * might not be able to handle the maximum number of devices possible. 703 */ 704 705 706 struct xhci_transfer_event { 707 /* 64-bit buffer address, or immediate data */ 708 __le64 buffer; 709 __le32 transfer_len; 710 /* This field is interpreted differently based on the type of TRB */ 711 volatile __le32 flags; 712 }; 713 714 /* Transfer event TRB length bit mask */ 715 /* bits 0:23 */ 716 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 717 718 /** Transfer Event bit fields **/ 719 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 720 721 /* Completion Code - only applicable for some types of TRBs */ 722 #define COMP_CODE_MASK (0xff << 24) 723 #define COMP_CODE_SHIFT (24) 724 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 725 726 typedef enum { 727 COMP_SUCCESS = 1, 728 /* Data Buffer Error */ 729 COMP_DB_ERR, /* 2 */ 730 /* Babble Detected Error */ 731 COMP_BABBLE, /* 3 */ 732 /* USB Transaction Error */ 733 COMP_TX_ERR, /* 4 */ 734 /* TRB Error - some TRB field is invalid */ 735 COMP_TRB_ERR, /* 5 */ 736 /* Stall Error - USB device is stalled */ 737 COMP_STALL, /* 6 */ 738 /* Resource Error - HC doesn't have memory for that device configuration */ 739 COMP_ENOMEM, /* 7 */ 740 /* Bandwidth Error - not enough room in schedule for this dev config */ 741 COMP_BW_ERR, /* 8 */ 742 /* No Slots Available Error - HC ran out of device slots */ 743 COMP_ENOSLOTS, /* 9 */ 744 /* Invalid Stream Type Error */ 745 COMP_STREAM_ERR, /* 10 */ 746 /* Slot Not Enabled Error - doorbell rung for disabled device slot */ 747 COMP_EBADSLT, /* 11 */ 748 /* Endpoint Not Enabled Error */ 749 COMP_EBADEP,/* 12 */ 750 /* Short Packet */ 751 COMP_SHORT_TX, /* 13 */ 752 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 753 COMP_UNDERRUN, /* 14 */ 754 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 755 COMP_OVERRUN, /* 15 */ 756 /* Virtual Function Event Ring Full Error */ 757 COMP_VF_FULL, /* 16 */ 758 /* Parameter Error - Context parameter is invalid */ 759 COMP_EINVAL, /* 17 */ 760 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 761 COMP_BW_OVER,/* 18 */ 762 /* Context State Error - illegal context state transition requested */ 763 COMP_CTX_STATE,/* 19 */ 764 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 765 COMP_PING_ERR,/* 20 */ 766 /* Event Ring is full */ 767 COMP_ER_FULL,/* 21 */ 768 /* Incompatible Device Error */ 769 COMP_DEV_ERR,/* 22 */ 770 /* Missed Service Error - HC couldn't service an isoc ep within interval */ 771 COMP_MISSED_INT,/* 23 */ 772 /* Successfully stopped command ring */ 773 COMP_CMD_STOP, /* 24 */ 774 /* Successfully aborted current command and stopped command ring */ 775 COMP_CMD_ABORT, /* 25 */ 776 /* Stopped - transfer was terminated by a stop endpoint command */ 777 COMP_STOP,/* 26 */ 778 /* Same as COMP_EP_STOPPED, but the transferred length in the event 779 * is invalid */ 780 COMP_STOP_INVAL, /* 27*/ 781 /* Control Abort Error - Debug Capability - control pipe aborted */ 782 COMP_DBG_ABORT, /* 28 */ 783 /* Max Exit Latency Too Large Error */ 784 COMP_MEL_ERR,/* 29 */ 785 /* TRB type 30 reserved */ 786 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 787 COMP_BUFF_OVER = 31, 788 /* Event Lost Error - xHC has an "internal event overrun condition" */ 789 COMP_ISSUES, /* 32 */ 790 /* Undefined Error - reported when other error codes don't apply */ 791 COMP_UNKNOWN, /* 33 */ 792 /* Invalid Stream ID Error */ 793 COMP_STRID_ERR, /* 34 */ 794 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 795 COMP_2ND_BW_ERR, /* 35 */ 796 /* Split Transaction Error */ 797 COMP_SPLIT_ERR /* 36 */ 798 799 } xhci_comp_code; 800 801 struct xhci_link_trb { 802 /* 64-bit segment pointer*/ 803 volatile __le64 segment_ptr; 804 volatile __le32 intr_target; 805 volatile __le32 control; 806 }; 807 808 /* control bitfields */ 809 #define LINK_TOGGLE (0x1 << 1) 810 811 /* Command completion event TRB */ 812 struct xhci_event_cmd { 813 /* Pointer to command TRB, or the value passed by the event data trb */ 814 volatile __le64 cmd_trb; 815 volatile __le32 status; 816 volatile __le32 flags; 817 }; 818 819 /* flags bitmasks */ 820 /* bits 16:23 are the virtual function ID */ 821 /* bits 24:31 are the slot ID */ 822 #define TRB_TO_SLOT_ID(p) (((p) & (0xff << 24)) >> 24) 823 #define TRB_TO_SLOT_ID_SHIFT (24) 824 #define TRB_TO_SLOT_ID_MASK (0xff << TRB_TO_SLOT_ID_SHIFT) 825 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 826 #define SLOT_ID_FOR_TRB_MASK (0xff) 827 #define SLOT_ID_FOR_TRB_SHIFT (24) 828 829 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 830 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 831 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 832 833 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 834 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 835 #define LAST_EP_INDEX 30 836 837 /* Set TR Dequeue Pointer command TRB fields */ 838 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 839 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 840 841 842 /* Port Status Change Event TRB fields */ 843 /* Port ID - bits 31:24 */ 844 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 845 #define PORT_ID_SHIFT (24) 846 #define PORT_ID_MASK (0xff << PORT_ID_SHIFT) 847 848 /* Normal TRB fields */ 849 /* transfer_len bitmasks - bits 0:16 */ 850 #define TRB_LEN(p) ((p) & 0x1ffff) 851 #define TRB_LEN_MASK (0x1ffff) 852 /* Interrupter Target - which MSI-X vector to target the completion event at */ 853 #define TRB_INTR_TARGET_SHIFT (22) 854 #define TRB_INTR_TARGET_MASK (0x3ff) 855 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 856 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 857 #define TRB_TBC(p) (((p) & 0x3) << 7) 858 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 859 860 /* Cycle bit - indicates TRB ownership by HC or HCD */ 861 #define TRB_CYCLE (1<<0) 862 /* 863 * Force next event data TRB to be evaluated before task switch. 864 * Used to pass OS data back after a TD completes. 865 */ 866 #define TRB_ENT (1<<1) 867 /* Interrupt on short packet */ 868 #define TRB_ISP (1<<2) 869 /* Set PCIe no snoop attribute */ 870 #define TRB_NO_SNOOP (1<<3) 871 /* Chain multiple TRBs into a TD */ 872 #define TRB_CHAIN (1<<4) 873 /* Interrupt on completion */ 874 #define TRB_IOC (1<<5) 875 /* The buffer pointer contains immediate data */ 876 #define TRB_IDT (1<<6) 877 878 /* Block Event Interrupt */ 879 #define TRB_BEI (1<<9) 880 881 /* Control transfer TRB specific fields */ 882 #define TRB_DIR_IN (1<<16) 883 #define TRB_TX_TYPE(p) ((p) << 16) 884 #define TRB_TX_TYPE_SHIFT (16) 885 #define TRB_DATA_OUT 2 886 #define TRB_DATA_IN 3 887 888 /* Isochronous TRB specific fields */ 889 #define TRB_SIA (1 << 31) 890 891 struct xhci_generic_trb { 892 volatile __le32 field[4]; 893 }; 894 895 union xhci_trb { 896 struct xhci_link_trb link; 897 struct xhci_transfer_event trans_event; 898 struct xhci_event_cmd event_cmd; 899 struct xhci_generic_trb generic; 900 }; 901 902 /* TRB bit mask */ 903 #define TRB_TYPE_BITMASK (0xfc00) 904 #define TRB_TYPE(p) ((p) << 10) 905 #define TRB_TYPE_SHIFT (10) 906 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 907 908 /* TRB type IDs */ 909 typedef enum { 910 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 911 TRB_NORMAL = 1, 912 /* setup stage for control transfers */ 913 TRB_SETUP, /* 2 */ 914 /* data stage for control transfers */ 915 TRB_DATA, /* 3 */ 916 /* status stage for control transfers */ 917 TRB_STATUS, /* 4 */ 918 /* isoc transfers */ 919 TRB_ISOC, /* 5 */ 920 /* TRB for linking ring segments */ 921 TRB_LINK, /* 6 */ 922 /* TRB for EVENT DATA */ 923 TRB_EVENT_DATA, /* 7 */ 924 /* Transfer Ring No-op (not for the command ring) */ 925 TRB_TR_NOOP, /* 8 */ 926 /* Command TRBs */ 927 /* Enable Slot Command */ 928 TRB_ENABLE_SLOT, /* 9 */ 929 /* Disable Slot Command */ 930 TRB_DISABLE_SLOT, /* 10 */ 931 /* Address Device Command */ 932 TRB_ADDR_DEV, /* 11 */ 933 /* Configure Endpoint Command */ 934 TRB_CONFIG_EP, /* 12 */ 935 /* Evaluate Context Command */ 936 TRB_EVAL_CONTEXT, /* 13 */ 937 /* Reset Endpoint Command */ 938 TRB_RESET_EP, /* 14 */ 939 /* Stop Transfer Ring Command */ 940 TRB_STOP_RING, /* 15 */ 941 /* Set Transfer Ring Dequeue Pointer Command */ 942 TRB_SET_DEQ, /* 16 */ 943 /* Reset Device Command */ 944 TRB_RESET_DEV, /* 17 */ 945 /* Force Event Command (opt) */ 946 TRB_FORCE_EVENT, /* 18 */ 947 /* Negotiate Bandwidth Command (opt) */ 948 TRB_NEG_BANDWIDTH, /* 19 */ 949 /* Set Latency Tolerance Value Command (opt) */ 950 TRB_SET_LT, /* 20 */ 951 /* Get port bandwidth Command */ 952 TRB_GET_BW, /* 21 */ 953 /* Force Header Command - generate a transaction or link management packet */ 954 TRB_FORCE_HEADER, /* 22 */ 955 /* No-op Command - not for transfer rings */ 956 TRB_CMD_NOOP, /* 23 */ 957 /* TRB IDs 24-31 reserved */ 958 /* Event TRBS */ 959 /* Transfer Event */ 960 TRB_TRANSFER = 32, 961 /* Command Completion Event */ 962 TRB_COMPLETION, /* 33 */ 963 /* Port Status Change Event */ 964 TRB_PORT_STATUS, /* 34 */ 965 /* Bandwidth Request Event (opt) */ 966 TRB_BANDWIDTH_EVENT, /* 35 */ 967 /* Doorbell Event (opt) */ 968 TRB_DOORBELL, /* 36 */ 969 /* Host Controller Event */ 970 TRB_HC_EVENT, /* 37 */ 971 /* Device Notification Event - device sent function wake notification */ 972 TRB_DEV_NOTE, /* 38 */ 973 /* MFINDEX Wrap Event - microframe counter wrapped */ 974 TRB_MFINDEX_WRAP, /* 39 */ 975 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 976 /* Nec vendor-specific command completion event. */ 977 TRB_NEC_CMD_COMP = 48, /* 48 */ 978 /* Get NEC firmware revision. */ 979 TRB_NEC_GET_FW, /* 49 */ 980 } trb_type; 981 982 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 983 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 984 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 985 cpu_to_le32(TRB_TYPE(TRB_LINK))) 986 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 987 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 988 989 /* 990 * TRBS_PER_SEGMENT must be a multiple of 4, 991 * since the command ring is 64-byte aligned. 992 * It must also be greater than 16. 993 */ 994 #define TRBS_PER_SEGMENT 64 995 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 996 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 997 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 998 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE). 999 * Change this if you change TRBS_PER_SEGMENT! 1000 */ 1001 #define SEGMENT_SHIFT 10 1002 /* TRB buffer pointers can't cross 64KB boundaries */ 1003 #define TRB_MAX_BUFF_SHIFT 16 1004 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1005 1006 struct xhci_segment { 1007 union xhci_trb *trbs; 1008 /* private to HCD */ 1009 struct xhci_segment *next; 1010 }; 1011 1012 struct xhci_ring { 1013 struct xhci_segment *first_seg; 1014 union xhci_trb *enqueue; 1015 struct xhci_segment *enq_seg; 1016 union xhci_trb *dequeue; 1017 struct xhci_segment *deq_seg; 1018 /* 1019 * Write the cycle state into the TRB cycle field to give ownership of 1020 * the TRB to the host controller (if we are the producer), or to check 1021 * if we own the TRB (if we are the consumer). See section 4.9.1. 1022 */ 1023 volatile u32 cycle_state; 1024 unsigned int num_segs; 1025 }; 1026 1027 struct xhci_erst_entry { 1028 /* 64-bit event ring segment address */ 1029 __le64 seg_addr; 1030 __le32 seg_size; 1031 /* Set to zero */ 1032 __le32 rsvd; 1033 }; 1034 1035 struct xhci_erst { 1036 struct xhci_erst_entry *entries; 1037 unsigned int num_entries; 1038 /* Num entries the ERST can contain */ 1039 unsigned int erst_size; 1040 }; 1041 1042 /* 1043 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1044 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1045 * meaning 64 ring segments. 1046 * Initial allocated size of the ERST, in number of entries */ 1047 #define ERST_NUM_SEGS 3 1048 /* Initial number of event segment rings allocated */ 1049 #define ERST_ENTRIES 3 1050 /* Initial allocated size of the ERST, in number of entries */ 1051 #define ERST_SIZE 64 1052 /* Poll every 60 seconds */ 1053 #define POLL_TIMEOUT 60 1054 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1055 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1056 /* XXX: Make these module parameters */ 1057 1058 struct xhci_virt_ep { 1059 struct xhci_ring *ring; 1060 unsigned int ep_state; 1061 #define SET_DEQ_PENDING (1 << 0) 1062 #define EP_HALTED (1 << 1) /* For stall handling */ 1063 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 1064 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 1065 #define EP_GETTING_STREAMS (1 << 3) 1066 #define EP_HAS_STREAMS (1 << 4) 1067 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 1068 #define EP_GETTING_NO_STREAMS (1 << 5) 1069 }; 1070 1071 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 1072 1073 struct xhci_virt_device { 1074 struct usb_device *udev; 1075 /* 1076 * Commands to the hardware are passed an "input context" that 1077 * tells the hardware what to change in its data structures. 1078 * The hardware will return changes in an "output context" that 1079 * software must allocate for the hardware. We need to keep 1080 * track of input and output contexts separately because 1081 * these commands might fail and we don't trust the hardware. 1082 */ 1083 struct xhci_container_ctx *out_ctx; 1084 /* Used for addressing devices and configuration changes */ 1085 struct xhci_container_ctx *in_ctx; 1086 /* Rings saved to ensure old alt settings can be re-instated */ 1087 #define XHCI_MAX_RINGS_CACHED 31 1088 struct xhci_virt_ep eps[31]; 1089 }; 1090 1091 /* TODO: copied from ehci.h - can be refactored? */ 1092 /* xHCI spec says all registers are little endian */ 1093 static inline unsigned int xhci_readl(uint32_t volatile *regs) 1094 { 1095 return readl(regs); 1096 } 1097 1098 static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) 1099 { 1100 writel(val, regs); 1101 } 1102 1103 /* 1104 * Registers should always be accessed with double word or quad word accesses. 1105 * Some xHCI implementations may support 64-bit address pointers. Registers 1106 * with 64-bit address pointers should be written to with dword accesses by 1107 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1108 * xHCI implementations that do not support 64-bit address pointers will ignore 1109 * the high dword, and write order is irrelevant. 1110 */ 1111 static inline u64 xhci_readq(__le64 volatile *regs) 1112 { 1113 __u32 *ptr = (__u32 *)regs; 1114 u64 val_lo = readl(ptr); 1115 u64 val_hi = readl(ptr + 1); 1116 return val_lo + (val_hi << 32); 1117 } 1118 1119 static inline void xhci_writeq(__le64 volatile *regs, const u64 val) 1120 { 1121 __u32 *ptr = (__u32 *)regs; 1122 u32 val_lo = lower_32_bits(val); 1123 /* FIXME */ 1124 u32 val_hi = 0; 1125 writel(val_lo, ptr); 1126 writel(val_hi, ptr + 1); 1127 } 1128 1129 int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, 1130 struct xhci_hcor **ret_hcor); 1131 void xhci_hcd_stop(int index); 1132 1133 1134 /************************************************************* 1135 EXTENDED CAPABILITY DEFINITIONS 1136 *************************************************************/ 1137 /* Up to 16 ms to halt an HC */ 1138 #define XHCI_MAX_HALT_USEC (16*1000) 1139 /* HC not running - set to 1 when run/stop bit is cleared. */ 1140 #define XHCI_STS_HALT (1 << 0) 1141 1142 /* HCCPARAMS offset from PCI base address */ 1143 #define XHCI_HCC_PARAMS_OFFSET 0x10 1144 /* HCCPARAMS contains the first extended capability pointer */ 1145 #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) 1146 1147 /* Command and Status registers offset from the Operational Registers address */ 1148 #define XHCI_CMD_OFFSET 0x00 1149 #define XHCI_STS_OFFSET 0x04 1150 1151 #define XHCI_MAX_EXT_CAPS 50 1152 1153 /* Capability Register */ 1154 /* bits 7:0 - how long is the Capabilities register */ 1155 #define XHCI_HC_LENGTH(p) (((p) >> 00) & 0x00ff) 1156 1157 /* Extended capability register fields */ 1158 #define XHCI_EXT_CAPS_ID(p) (((p) >> 0) & 0xff) 1159 #define XHCI_EXT_CAPS_NEXT(p) (((p) >> 8) & 0xff) 1160 #define XHCI_EXT_CAPS_VAL(p) ((p) >> 16) 1161 /* Extended capability IDs - ID 0 reserved */ 1162 #define XHCI_EXT_CAPS_LEGACY 1 1163 #define XHCI_EXT_CAPS_PROTOCOL 2 1164 #define XHCI_EXT_CAPS_PM 3 1165 #define XHCI_EXT_CAPS_VIRT 4 1166 #define XHCI_EXT_CAPS_ROUTE 5 1167 /* IDs 6-9 reserved */ 1168 #define XHCI_EXT_CAPS_DEBUG 10 1169 /* USB Legacy Support Capability - section 7.1.1 */ 1170 #define XHCI_HC_BIOS_OWNED (1 << 16) 1171 #define XHCI_HC_OS_OWNED (1 << 24) 1172 1173 /* USB Legacy Support Capability - section 7.1.1 */ 1174 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1175 #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) 1176 1177 /* USB Legacy Support Control and Status Register - section 7.1.2 */ 1178 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ 1179 #define XHCI_LEGACY_CONTROL_OFFSET (0x04) 1180 /* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ 1181 #define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17)) 1182 1183 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ 1184 #define XHCI_L1C (1 << 16) 1185 1186 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ 1187 #define XHCI_HLC (1 << 19) 1188 1189 /* command register values to disable interrupts and halt the HC */ 1190 /* start/stop HC execution - do not write unless HC is halted*/ 1191 #define XHCI_CMD_RUN (1 << 0) 1192 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ 1193 #define XHCI_CMD_EIE (1 << 2) 1194 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ 1195 #define XHCI_CMD_HSEIE (1 << 3) 1196 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 1197 #define XHCI_CMD_EWE (1 << 10) 1198 1199 #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) 1200 1201 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 1202 #define XHCI_STS_CNR (1 << 11) 1203 1204 struct xhci_ctrl { 1205 struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ 1206 struct xhci_hcor *hcor; 1207 struct xhci_doorbell_array *dba; 1208 struct xhci_run_regs *run_regs; 1209 struct xhci_device_context_array *dcbaa \ 1210 __attribute__ ((aligned(ARCH_DMA_MINALIGN))); 1211 struct xhci_ring *event_ring; 1212 struct xhci_ring *cmd_ring; 1213 struct xhci_ring *transfer_ring; 1214 struct xhci_segment *seg; 1215 struct xhci_intr_reg *ir_set; 1216 struct xhci_erst erst; 1217 struct xhci_erst_entry entry[ERST_NUM_SEGS]; 1218 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1219 int rootdev; 1220 }; 1221 1222 unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); 1223 struct xhci_input_control_ctx 1224 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1225 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl, 1226 struct xhci_container_ctx *ctx); 1227 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl, 1228 struct xhci_container_ctx *ctx, 1229 unsigned int ep_index); 1230 void xhci_endpoint_copy(struct xhci_ctrl *ctrl, 1231 struct xhci_container_ctx *in_ctx, 1232 struct xhci_container_ctx *out_ctx, 1233 unsigned int ep_index); 1234 void xhci_slot_copy(struct xhci_ctrl *ctrl, 1235 struct xhci_container_ctx *in_ctx, 1236 struct xhci_container_ctx *out_ctx); 1237 void xhci_setup_addressable_virt_dev(struct usb_device *udev); 1238 void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, 1239 u32 slot_id, u32 ep_index, trb_type cmd); 1240 void xhci_acknowledge_event(struct xhci_ctrl *ctrl); 1241 union xhci_trb *xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected); 1242 int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, 1243 int length, void *buffer); 1244 int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, 1245 struct devrequest *req, int length, void *buffer); 1246 int xhci_check_maxpacket(struct usb_device *udev); 1247 void xhci_flush_cache(uint32_t addr, u32 type_len); 1248 void xhci_inval_cache(uint32_t addr, u32 type_len); 1249 void xhci_cleanup(struct xhci_ctrl *ctrl); 1250 struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs); 1251 int xhci_alloc_virt_device(struct usb_device *udev); 1252 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, 1253 struct xhci_hcor *hcor); 1254 1255 #endif /* HOST_XHCI_H_ */ 1256