xref: /openbmc/u-boot/drivers/usb/host/xhci.c (revision ad5b5801)
1 /*
2  * USB HOST XHCI Controller stack
3  *
4  * Based on xHCI host controller driver in linux-kernel
5  * by Sarah Sharp.
6  *
7  * Copyright (C) 2008 Intel Corp.
8  * Author: Sarah Sharp
9  *
10  * Copyright (C) 2013 Samsung Electronics Co.Ltd
11  * Authors: Vivek Gautam <gautam.vivek@samsung.com>
12  *	    Vikas Sajjan <vikas.sajjan@samsung.com>
13  *
14  * SPDX-License-Identifier:	GPL-2.0+
15  */
16 
17 /**
18  * This file gives the xhci stack for usb3.0 looking into
19  * xhci specification Rev1.0 (5/21/10).
20  * The quirk devices support hasn't been given yet.
21  */
22 
23 #include <common.h>
24 #include <dm.h>
25 #include <asm/byteorder.h>
26 #include <usb.h>
27 #include <malloc.h>
28 #include <watchdog.h>
29 #include <asm/cache.h>
30 #include <asm/unaligned.h>
31 #include <asm-generic/errno.h>
32 #include "xhci.h"
33 
34 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
35 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
36 #endif
37 
38 static struct descriptor {
39 	struct usb_hub_descriptor hub;
40 	struct usb_device_descriptor device;
41 	struct usb_config_descriptor config;
42 	struct usb_interface_descriptor interface;
43 	struct usb_endpoint_descriptor endpoint;
44 	struct usb_ss_ep_comp_descriptor ep_companion;
45 } __attribute__ ((packed)) descriptor = {
46 	{
47 		0xc,		/* bDescLength */
48 		0x2a,		/* bDescriptorType: hub descriptor */
49 		2,		/* bNrPorts -- runtime modified */
50 		cpu_to_le16(0x8), /* wHubCharacteristics */
51 		10,		/* bPwrOn2PwrGood */
52 		0,		/* bHubCntrCurrent */
53 		{},		/* Device removable */
54 		{}		/* at most 7 ports! XXX */
55 	},
56 	{
57 		0x12,		/* bLength */
58 		1,		/* bDescriptorType: UDESC_DEVICE */
59 		cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
60 		9,		/* bDeviceClass: UDCLASS_HUB */
61 		0,		/* bDeviceSubClass: UDSUBCLASS_HUB */
62 		3,		/* bDeviceProtocol: UDPROTO_SSHUBSTT */
63 		9,		/* bMaxPacketSize: 512 bytes  2^9 */
64 		0x0000,		/* idVendor */
65 		0x0000,		/* idProduct */
66 		cpu_to_le16(0x0100), /* bcdDevice */
67 		1,		/* iManufacturer */
68 		2,		/* iProduct */
69 		0,		/* iSerialNumber */
70 		1		/* bNumConfigurations: 1 */
71 	},
72 	{
73 		0x9,
74 		2,		/* bDescriptorType: UDESC_CONFIG */
75 		cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
76 		1,		/* bNumInterface */
77 		1,		/* bConfigurationValue */
78 		0,		/* iConfiguration */
79 		0x40,		/* bmAttributes: UC_SELF_POWER */
80 		0		/* bMaxPower */
81 	},
82 	{
83 		0x9,		/* bLength */
84 		4,		/* bDescriptorType: UDESC_INTERFACE */
85 		0,		/* bInterfaceNumber */
86 		0,		/* bAlternateSetting */
87 		1,		/* bNumEndpoints */
88 		9,		/* bInterfaceClass: UICLASS_HUB */
89 		0,		/* bInterfaceSubClass: UISUBCLASS_HUB */
90 		0,		/* bInterfaceProtocol: UIPROTO_HSHUBSTT */
91 		0		/* iInterface */
92 	},
93 	{
94 		0x7,		/* bLength */
95 		5,		/* bDescriptorType: UDESC_ENDPOINT */
96 		0x81,		/* bEndpointAddress: IN endpoint 1 */
97 		3,		/* bmAttributes: UE_INTERRUPT */
98 		8,		/* wMaxPacketSize */
99 		255		/* bInterval */
100 	},
101 	{
102 		0x06,		/* ss_bLength */
103 		0x30,		/* ss_bDescriptorType: SS EP Companion */
104 		0x00,		/* ss_bMaxBurst: allows 1 TX between ACKs */
105 		/* ss_bmAttributes: 1 packet per service interval */
106 		0x00,
107 		/* ss_wBytesPerInterval: 15 bits for max 15 ports */
108 		cpu_to_le16(0x02),
109 	},
110 };
111 
112 #ifndef CONFIG_DM_USB
113 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
114 #endif
115 
116 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
117 {
118 #ifdef CONFIG_DM_USB
119 	struct udevice *dev;
120 
121 	/* Find the USB controller */
122 	for (dev = udev->dev;
123 	     device_get_uclass_id(dev) != UCLASS_USB;
124 	     dev = dev->parent)
125 		;
126 	return dev_get_priv(dev);
127 #else
128 	return udev->controller;
129 #endif
130 }
131 
132 /**
133  * Waits for as per specified amount of time
134  * for the "result" to match with "done"
135  *
136  * @param ptr	pointer to the register to be read
137  * @param mask	mask for the value read
138  * @param done	value to be campared with result
139  * @param usec	time to wait till
140  * @return 0 if handshake is success else < 0 on failure
141  */
142 static int handshake(uint32_t volatile *ptr, uint32_t mask,
143 					uint32_t done, int usec)
144 {
145 	uint32_t result;
146 
147 	do {
148 		result = xhci_readl(ptr);
149 		if (result == ~(uint32_t)0)
150 			return -ENODEV;
151 		result &= mask;
152 		if (result == done)
153 			return 0;
154 		usec--;
155 		udelay(1);
156 	} while (usec > 0);
157 
158 	return -ETIMEDOUT;
159 }
160 
161 /**
162  * Set the run bit and wait for the host to be running.
163  *
164  * @param hcor	pointer to host controller operation registers
165  * @return status of the Handshake
166  */
167 static int xhci_start(struct xhci_hcor *hcor)
168 {
169 	u32 temp;
170 	int ret;
171 
172 	puts("Starting the controller\n");
173 	temp = xhci_readl(&hcor->or_usbcmd);
174 	temp |= (CMD_RUN);
175 	xhci_writel(&hcor->or_usbcmd, temp);
176 
177 	/*
178 	 * Wait for the HCHalted Status bit to be 0 to indicate the host is
179 	 * running.
180 	 */
181 	ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
182 	if (ret)
183 		debug("Host took too long to start, "
184 				"waited %u microseconds.\n",
185 				XHCI_MAX_HALT_USEC);
186 	return ret;
187 }
188 
189 /**
190  * Resets the XHCI Controller
191  *
192  * @param hcor	pointer to host controller operation registers
193  * @return -EBUSY if XHCI Controller is not halted else status of handshake
194  */
195 int xhci_reset(struct xhci_hcor *hcor)
196 {
197 	u32 cmd;
198 	u32 state;
199 	int ret;
200 
201 	/* Halting the Host first */
202 	debug("// Halt the HC: %p\n", hcor);
203 	state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
204 	if (!state) {
205 		cmd = xhci_readl(&hcor->or_usbcmd);
206 		cmd &= ~CMD_RUN;
207 		xhci_writel(&hcor->or_usbcmd, cmd);
208 	}
209 
210 	ret = handshake(&hcor->or_usbsts,
211 			STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
212 	if (ret) {
213 		printf("Host not halted after %u microseconds.\n",
214 				XHCI_MAX_HALT_USEC);
215 		return -EBUSY;
216 	}
217 
218 	debug("// Reset the HC\n");
219 	cmd = xhci_readl(&hcor->or_usbcmd);
220 	cmd |= CMD_RESET;
221 	xhci_writel(&hcor->or_usbcmd, cmd);
222 
223 	ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
224 	if (ret)
225 		return ret;
226 
227 	/*
228 	 * xHCI cannot write to any doorbells or operational registers other
229 	 * than status until the "Controller Not Ready" flag is cleared.
230 	 */
231 	return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
232 }
233 
234 /**
235  * Used for passing endpoint bitmasks between the core and HCDs.
236  * Find the index for an endpoint given its descriptor.
237  * Use the return value to right shift 1 for the bitmask.
238  *
239  * Index  = (epnum * 2) + direction - 1,
240  * where direction = 0 for OUT, 1 for IN.
241  * For control endpoints, the IN index is used (OUT index is unused), so
242  * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
243  *
244  * @param desc	USB enpdoint Descriptor
245  * @return index of the Endpoint
246  */
247 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
248 {
249 	unsigned int index;
250 
251 	if (usb_endpoint_xfer_control(desc))
252 		index = (unsigned int)(usb_endpoint_num(desc) * 2);
253 	else
254 		index = (unsigned int)((usb_endpoint_num(desc) * 2) -
255 				(usb_endpoint_dir_in(desc) ? 0 : 1));
256 
257 	return index;
258 }
259 
260 /**
261  * Issue a configure endpoint command or evaluate context command
262  * and wait for it to finish.
263  *
264  * @param udev	pointer to the Device Data Structure
265  * @param ctx_change	flag to indicate the Context has changed or NOT
266  * @return 0 on success, -1 on failure
267  */
268 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
269 {
270 	struct xhci_container_ctx *in_ctx;
271 	struct xhci_virt_device *virt_dev;
272 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
273 	union xhci_trb *event;
274 
275 	virt_dev = ctrl->devs[udev->slot_id];
276 	in_ctx = virt_dev->in_ctx;
277 
278 	xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
279 	xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
280 			   ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
281 	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
282 	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
283 		!= udev->slot_id);
284 
285 	switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
286 	case COMP_SUCCESS:
287 		debug("Successful %s command\n",
288 			ctx_change ? "Evaluate Context" : "Configure Endpoint");
289 		break;
290 	default:
291 		printf("ERROR: %s command returned completion code %d.\n",
292 			ctx_change ? "Evaluate Context" : "Configure Endpoint",
293 			GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
294 		return -EINVAL;
295 	}
296 
297 	xhci_acknowledge_event(ctrl);
298 
299 	return 0;
300 }
301 
302 /**
303  * Configure the endpoint, programming the device contexts.
304  *
305  * @param udev	pointer to the USB device structure
306  * @return returns the status of the xhci_configure_endpoints
307  */
308 static int xhci_set_configuration(struct usb_device *udev)
309 {
310 	struct xhci_container_ctx *in_ctx;
311 	struct xhci_container_ctx *out_ctx;
312 	struct xhci_input_control_ctx *ctrl_ctx;
313 	struct xhci_slot_ctx *slot_ctx;
314 	struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
315 	int cur_ep;
316 	int max_ep_flag = 0;
317 	int ep_index;
318 	unsigned int dir;
319 	unsigned int ep_type;
320 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
321 	int num_of_ep;
322 	int ep_flag = 0;
323 	u64 trb_64 = 0;
324 	int slot_id = udev->slot_id;
325 	struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
326 	struct usb_interface *ifdesc;
327 
328 	out_ctx = virt_dev->out_ctx;
329 	in_ctx = virt_dev->in_ctx;
330 
331 	num_of_ep = udev->config.if_desc[0].no_of_ep;
332 	ifdesc = &udev->config.if_desc[0];
333 
334 	ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
335 	/* Zero the input context control */
336 	ctrl_ctx->add_flags = 0;
337 	ctrl_ctx->drop_flags = 0;
338 
339 	/* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
340 	for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
341 		ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
342 		ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
343 		if (max_ep_flag < ep_flag)
344 			max_ep_flag = ep_flag;
345 	}
346 
347 	xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
348 
349 	/* slot context */
350 	xhci_slot_copy(ctrl, in_ctx, out_ctx);
351 	slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
352 	slot_ctx->dev_info &= ~(LAST_CTX_MASK);
353 	slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
354 
355 	xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
356 
357 	/* filling up ep contexts */
358 	for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
359 		struct usb_endpoint_descriptor *endpt_desc = NULL;
360 
361 		endpt_desc = &ifdesc->ep_desc[cur_ep];
362 		trb_64 = 0;
363 
364 		ep_index = xhci_get_ep_index(endpt_desc);
365 		ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
366 
367 		/* Allocate the ep rings */
368 		virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
369 		if (!virt_dev->eps[ep_index].ring)
370 			return -ENOMEM;
371 
372 		/*NOTE: ep_desc[0] actually represents EP1 and so on */
373 		dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
374 		ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
375 		ep_ctx[ep_index]->ep_info2 =
376 			cpu_to_le32(ep_type << EP_TYPE_SHIFT);
377 		ep_ctx[ep_index]->ep_info2 |=
378 			cpu_to_le32(MAX_PACKET
379 			(get_unaligned(&endpt_desc->wMaxPacketSize)));
380 
381 		ep_ctx[ep_index]->ep_info2 |=
382 			cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
383 			((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
384 
385 		trb_64 = (uintptr_t)
386 				virt_dev->eps[ep_index].ring->enqueue;
387 		ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
388 				virt_dev->eps[ep_index].ring->cycle_state);
389 	}
390 
391 	return xhci_configure_endpoints(udev, false);
392 }
393 
394 /**
395  * Issue an Address Device command (which will issue a SetAddress request to
396  * the device).
397  *
398  * @param udev pointer to the Device Data Structure
399  * @return 0 if successful else error code on failure
400  */
401 static int xhci_address_device(struct usb_device *udev, int root_portnr)
402 {
403 	int ret = 0;
404 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
405 	struct xhci_slot_ctx *slot_ctx;
406 	struct xhci_input_control_ctx *ctrl_ctx;
407 	struct xhci_virt_device *virt_dev;
408 	int slot_id = udev->slot_id;
409 	union xhci_trb *event;
410 
411 	virt_dev = ctrl->devs[slot_id];
412 
413 	/*
414 	 * This is the first Set Address since device plug-in
415 	 * so setting up the slot context.
416 	 */
417 	debug("Setting up addressable devices %p\n", ctrl->dcbaa);
418 	xhci_setup_addressable_virt_dev(ctrl, udev->slot_id, udev->speed,
419 					root_portnr);
420 
421 	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
422 	ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
423 	ctrl_ctx->drop_flags = 0;
424 
425 	xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
426 	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
427 	BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
428 
429 	switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
430 	case COMP_CTX_STATE:
431 	case COMP_EBADSLT:
432 		printf("Setup ERROR: address device command for slot %d.\n",
433 								slot_id);
434 		ret = -EINVAL;
435 		break;
436 	case COMP_TX_ERR:
437 		puts("Device not responding to set address.\n");
438 		ret = -EPROTO;
439 		break;
440 	case COMP_DEV_ERR:
441 		puts("ERROR: Incompatible device"
442 					"for address device command.\n");
443 		ret = -ENODEV;
444 		break;
445 	case COMP_SUCCESS:
446 		debug("Successful Address Device command\n");
447 		udev->status = 0;
448 		break;
449 	default:
450 		printf("ERROR: unexpected command completion code 0x%x.\n",
451 			GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
452 		ret = -EINVAL;
453 		break;
454 	}
455 
456 	xhci_acknowledge_event(ctrl);
457 
458 	if (ret < 0)
459 		/*
460 		 * TODO: Unsuccessful Address Device command shall leave the
461 		 * slot in default state. So, issue Disable Slot command now.
462 		 */
463 		return ret;
464 
465 	xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
466 			 virt_dev->out_ctx->size);
467 	slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
468 
469 	debug("xHC internal address is: %d\n",
470 		le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
471 
472 	return 0;
473 }
474 
475 /**
476  * Issue Enable slot command to the controller to allocate
477  * device slot and assign the slot id. It fails if the xHC
478  * ran out of device slots, the Enable Slot command timed out,
479  * or allocating memory failed.
480  *
481  * @param udev	pointer to the Device Data Structure
482  * @return Returns 0 on succes else return error code on failure
483  */
484 int _xhci_alloc_device(struct usb_device *udev)
485 {
486 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
487 	union xhci_trb *event;
488 	int ret;
489 
490 	/*
491 	 * Root hub will be first device to be initailized.
492 	 * If this device is root-hub, don't do any xHC related
493 	 * stuff.
494 	 */
495 	if (ctrl->rootdev == 0) {
496 		udev->speed = USB_SPEED_SUPER;
497 		return 0;
498 	}
499 
500 	xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
501 	event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
502 	BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
503 		!= COMP_SUCCESS);
504 
505 	udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
506 
507 	xhci_acknowledge_event(ctrl);
508 
509 	ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
510 	if (ret < 0) {
511 		/*
512 		 * TODO: Unsuccessful Address Device command shall leave
513 		 * the slot in default. So, issue Disable Slot command now.
514 		 */
515 		puts("Could not allocate xHCI USB device data structures\n");
516 		return ret;
517 	}
518 
519 	return 0;
520 }
521 
522 #ifndef CONFIG_DM_USB
523 int usb_alloc_device(struct usb_device *udev)
524 {
525 	return _xhci_alloc_device(udev);
526 }
527 #endif
528 
529 /*
530  * Full speed devices may have a max packet size greater than 8 bytes, but the
531  * USB core doesn't know that until it reads the first 8 bytes of the
532  * descriptor.  If the usb_device's max packet size changes after that point,
533  * we need to issue an evaluate context command and wait on it.
534  *
535  * @param udev	pointer to the Device Data Structure
536  * @return returns the status of the xhci_configure_endpoints
537  */
538 int xhci_check_maxpacket(struct usb_device *udev)
539 {
540 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
541 	unsigned int slot_id = udev->slot_id;
542 	int ep_index = 0;	/* control endpoint */
543 	struct xhci_container_ctx *in_ctx;
544 	struct xhci_container_ctx *out_ctx;
545 	struct xhci_input_control_ctx *ctrl_ctx;
546 	struct xhci_ep_ctx *ep_ctx;
547 	int max_packet_size;
548 	int hw_max_packet_size;
549 	int ret = 0;
550 	struct usb_interface *ifdesc;
551 
552 	ifdesc = &udev->config.if_desc[0];
553 
554 	out_ctx = ctrl->devs[slot_id]->out_ctx;
555 	xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
556 
557 	ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
558 	hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
559 	max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
560 	if (hw_max_packet_size != max_packet_size) {
561 		debug("Max Packet Size for ep 0 changed.\n");
562 		debug("Max packet size in usb_device = %d\n", max_packet_size);
563 		debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
564 		debug("Issuing evaluate context command.\n");
565 
566 		/* Set up the modified control endpoint 0 */
567 		xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
568 				ctrl->devs[slot_id]->out_ctx, ep_index);
569 		in_ctx = ctrl->devs[slot_id]->in_ctx;
570 		ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
571 		ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
572 		ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
573 
574 		/*
575 		 * Set up the input context flags for the command
576 		 * FIXME: This won't work if a non-default control endpoint
577 		 * changes max packet sizes.
578 		 */
579 		ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
580 		ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
581 		ctrl_ctx->drop_flags = 0;
582 
583 		ret = xhci_configure_endpoints(udev, true);
584 	}
585 	return ret;
586 }
587 
588 /**
589  * Clears the Change bits of the Port Status Register
590  *
591  * @param wValue	request value
592  * @param wIndex	request index
593  * @param addr		address of posrt status register
594  * @param port_status	state of port status register
595  * @return none
596  */
597 static void xhci_clear_port_change_bit(u16 wValue,
598 		u16 wIndex, volatile uint32_t *addr, u32 port_status)
599 {
600 	char *port_change_bit;
601 	u32 status;
602 
603 	switch (wValue) {
604 	case USB_PORT_FEAT_C_RESET:
605 		status = PORT_RC;
606 		port_change_bit = "reset";
607 		break;
608 	case USB_PORT_FEAT_C_CONNECTION:
609 		status = PORT_CSC;
610 		port_change_bit = "connect";
611 		break;
612 	case USB_PORT_FEAT_C_OVER_CURRENT:
613 		status = PORT_OCC;
614 		port_change_bit = "over-current";
615 		break;
616 	case USB_PORT_FEAT_C_ENABLE:
617 		status = PORT_PEC;
618 		port_change_bit = "enable/disable";
619 		break;
620 	case USB_PORT_FEAT_C_SUSPEND:
621 		status = PORT_PLC;
622 		port_change_bit = "suspend/resume";
623 		break;
624 	default:
625 		/* Should never happen */
626 		return;
627 	}
628 
629 	/* Change bits are all write 1 to clear */
630 	xhci_writel(addr, port_status | status);
631 
632 	port_status = xhci_readl(addr);
633 	debug("clear port %s change, actual port %d status  = 0x%x\n",
634 			port_change_bit, wIndex, port_status);
635 }
636 
637 /**
638  * Save Read Only (RO) bits and save read/write bits where
639  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
640  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
641  *
642  * @param state	state of the Port Status and Control Regsiter
643  * @return a value that would result in the port being in the
644  *	   same state, if the value was written to the port
645  *	   status control register.
646  */
647 static u32 xhci_port_state_to_neutral(u32 state)
648 {
649 	/* Save read-only status and port state */
650 	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
651 }
652 
653 /**
654  * Submits the Requests to the XHCI Host Controller
655  *
656  * @param udev pointer to the USB device structure
657  * @param pipe contains the DIR_IN or OUT , devnum
658  * @param buffer buffer to be read/written based on the request
659  * @return returns 0 if successful else -1 on failure
660  */
661 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
662 			void *buffer, struct devrequest *req)
663 {
664 	uint8_t tmpbuf[4];
665 	u16 typeReq;
666 	void *srcptr = NULL;
667 	int len, srclen;
668 	uint32_t reg;
669 	volatile uint32_t *status_reg;
670 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
671 	struct xhci_hcor *hcor = ctrl->hcor;
672 
673 	if ((req->requesttype & USB_RT_PORT) &&
674 	    le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
675 		printf("The request port(%d) is not configured\n",
676 			le16_to_cpu(req->index) - 1);
677 		return -EINVAL;
678 	}
679 
680 	status_reg = (volatile uint32_t *)
681 		     (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
682 	srclen = 0;
683 
684 	typeReq = req->request | req->requesttype << 8;
685 
686 	switch (typeReq) {
687 	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
688 		switch (le16_to_cpu(req->value) >> 8) {
689 		case USB_DT_DEVICE:
690 			debug("USB_DT_DEVICE request\n");
691 			srcptr = &descriptor.device;
692 			srclen = 0x12;
693 			break;
694 		case USB_DT_CONFIG:
695 			debug("USB_DT_CONFIG config\n");
696 			srcptr = &descriptor.config;
697 			srclen = 0x19;
698 			break;
699 		case USB_DT_STRING:
700 			debug("USB_DT_STRING config\n");
701 			switch (le16_to_cpu(req->value) & 0xff) {
702 			case 0:	/* Language */
703 				srcptr = "\4\3\11\4";
704 				srclen = 4;
705 				break;
706 			case 1:	/* Vendor String  */
707 				srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
708 				srclen = 14;
709 				break;
710 			case 2:	/* Product Name */
711 				srcptr = "\52\3X\0H\0C\0I\0 "
712 					 "\0H\0o\0s\0t\0 "
713 					 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
714 				srclen = 42;
715 				break;
716 			default:
717 				printf("unknown value DT_STRING %x\n",
718 					le16_to_cpu(req->value));
719 				goto unknown;
720 			}
721 			break;
722 		default:
723 			printf("unknown value %x\n", le16_to_cpu(req->value));
724 			goto unknown;
725 		}
726 		break;
727 	case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
728 		switch (le16_to_cpu(req->value) >> 8) {
729 		case USB_DT_HUB:
730 			debug("USB_DT_HUB config\n");
731 			srcptr = &descriptor.hub;
732 			srclen = 0x8;
733 			break;
734 		default:
735 			printf("unknown value %x\n", le16_to_cpu(req->value));
736 			goto unknown;
737 		}
738 		break;
739 	case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
740 		debug("USB_REQ_SET_ADDRESS\n");
741 		ctrl->rootdev = le16_to_cpu(req->value);
742 		break;
743 	case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
744 		/* Do nothing */
745 		break;
746 	case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
747 		tmpbuf[0] = 1;	/* USB_STATUS_SELFPOWERED */
748 		tmpbuf[1] = 0;
749 		srcptr = tmpbuf;
750 		srclen = 2;
751 		break;
752 	case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
753 		memset(tmpbuf, 0, 4);
754 		reg = xhci_readl(status_reg);
755 		if (reg & PORT_CONNECT) {
756 			tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
757 			switch (reg & DEV_SPEED_MASK) {
758 			case XDEV_FS:
759 				debug("SPEED = FULLSPEED\n");
760 				break;
761 			case XDEV_LS:
762 				debug("SPEED = LOWSPEED\n");
763 				tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
764 				break;
765 			case XDEV_HS:
766 				debug("SPEED = HIGHSPEED\n");
767 				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
768 				break;
769 			case XDEV_SS:
770 				debug("SPEED = SUPERSPEED\n");
771 				tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
772 				break;
773 			}
774 		}
775 		if (reg & PORT_PE)
776 			tmpbuf[0] |= USB_PORT_STAT_ENABLE;
777 		if ((reg & PORT_PLS_MASK) == XDEV_U3)
778 			tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
779 		if (reg & PORT_OC)
780 			tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
781 		if (reg & PORT_RESET)
782 			tmpbuf[0] |= USB_PORT_STAT_RESET;
783 		if (reg & PORT_POWER)
784 			/*
785 			 * XXX: This Port power bit (for USB 3.0 hub)
786 			 * we are faking in USB 2.0 hub port status;
787 			 * since there's a change in bit positions in
788 			 * two:
789 			 * USB 2.0 port status PP is at position[8]
790 			 * USB 3.0 port status PP is at position[9]
791 			 * So, we are still keeping it at position [8]
792 			 */
793 			tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
794 		if (reg & PORT_CSC)
795 			tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
796 		if (reg & PORT_PEC)
797 			tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
798 		if (reg & PORT_OCC)
799 			tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
800 		if (reg & PORT_RC)
801 			tmpbuf[2] |= USB_PORT_STAT_C_RESET;
802 
803 		srcptr = tmpbuf;
804 		srclen = 4;
805 		break;
806 	case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
807 		reg = xhci_readl(status_reg);
808 		reg = xhci_port_state_to_neutral(reg);
809 		switch (le16_to_cpu(req->value)) {
810 		case USB_PORT_FEAT_ENABLE:
811 			reg |= PORT_PE;
812 			xhci_writel(status_reg, reg);
813 			break;
814 		case USB_PORT_FEAT_POWER:
815 			reg |= PORT_POWER;
816 			xhci_writel(status_reg, reg);
817 			break;
818 		case USB_PORT_FEAT_RESET:
819 			reg |= PORT_RESET;
820 			xhci_writel(status_reg, reg);
821 			break;
822 		default:
823 			printf("unknown feature %x\n", le16_to_cpu(req->value));
824 			goto unknown;
825 		}
826 		break;
827 	case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
828 		reg = xhci_readl(status_reg);
829 		reg = xhci_port_state_to_neutral(reg);
830 		switch (le16_to_cpu(req->value)) {
831 		case USB_PORT_FEAT_ENABLE:
832 			reg &= ~PORT_PE;
833 			break;
834 		case USB_PORT_FEAT_POWER:
835 			reg &= ~PORT_POWER;
836 			break;
837 		case USB_PORT_FEAT_C_RESET:
838 		case USB_PORT_FEAT_C_CONNECTION:
839 		case USB_PORT_FEAT_C_OVER_CURRENT:
840 		case USB_PORT_FEAT_C_ENABLE:
841 			xhci_clear_port_change_bit((le16_to_cpu(req->value)),
842 							le16_to_cpu(req->index),
843 							status_reg, reg);
844 			break;
845 		default:
846 			printf("unknown feature %x\n", le16_to_cpu(req->value));
847 			goto unknown;
848 		}
849 		xhci_writel(status_reg, reg);
850 		break;
851 	default:
852 		puts("Unknown request\n");
853 		goto unknown;
854 	}
855 
856 	debug("scrlen = %d\n req->length = %d\n",
857 		srclen, le16_to_cpu(req->length));
858 
859 	len = min(srclen, (int)le16_to_cpu(req->length));
860 
861 	if (srcptr != NULL && len > 0)
862 		memcpy(buffer, srcptr, len);
863 	else
864 		debug("Len is 0\n");
865 
866 	udev->act_len = len;
867 	udev->status = 0;
868 
869 	return 0;
870 
871 unknown:
872 	udev->act_len = 0;
873 	udev->status = USB_ST_STALLED;
874 
875 	return -ENODEV;
876 }
877 
878 /**
879  * Submits the INT request to XHCI Host cotroller
880  *
881  * @param udev	pointer to the USB device
882  * @param pipe		contains the DIR_IN or OUT , devnum
883  * @param buffer	buffer to be read/written based on the request
884  * @param length	length of the buffer
885  * @param interval	interval of the interrupt
886  * @return 0
887  */
888 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
889 				void *buffer, int length, int interval)
890 {
891 	/*
892 	 * TODO: Not addressing any interrupt type transfer requests
893 	 * Add support for it later.
894 	 */
895 	return -EINVAL;
896 }
897 
898 /**
899  * submit the BULK type of request to the USB Device
900  *
901  * @param udev	pointer to the USB device
902  * @param pipe		contains the DIR_IN or OUT , devnum
903  * @param buffer	buffer to be read/written based on the request
904  * @param length	length of the buffer
905  * @return returns 0 if successful else -1 on failure
906  */
907 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
908 				 void *buffer, int length)
909 {
910 	if (usb_pipetype(pipe) != PIPE_BULK) {
911 		printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
912 		return -EINVAL;
913 	}
914 
915 	return xhci_bulk_tx(udev, pipe, length, buffer);
916 }
917 
918 /**
919  * submit the control type of request to the Root hub/Device based on the devnum
920  *
921  * @param udev	pointer to the USB device
922  * @param pipe		contains the DIR_IN or OUT , devnum
923  * @param buffer	buffer to be read/written based on the request
924  * @param length	length of the buffer
925  * @param setup		Request type
926  * @param root_portnr	Root port number that this device is on
927  * @return returns 0 if successful else -1 on failure
928  */
929 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
930 				    void *buffer, int length,
931 				    struct devrequest *setup, int root_portnr)
932 {
933 	struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
934 	int ret = 0;
935 
936 	if (usb_pipetype(pipe) != PIPE_CONTROL) {
937 		printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
938 		return -EINVAL;
939 	}
940 
941 	if (usb_pipedevice(pipe) == ctrl->rootdev)
942 		return xhci_submit_root(udev, pipe, buffer, setup);
943 
944 	if (setup->request == USB_REQ_SET_ADDRESS &&
945 	   (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
946 		return xhci_address_device(udev, root_portnr);
947 
948 	if (setup->request == USB_REQ_SET_CONFIGURATION &&
949 	   (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
950 		ret = xhci_set_configuration(udev);
951 		if (ret) {
952 			puts("Failed to configure xHCI endpoint\n");
953 			return ret;
954 		}
955 	}
956 
957 	return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
958 }
959 
960 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
961 {
962 	struct xhci_hccr *hccr;
963 	struct xhci_hcor *hcor;
964 	uint32_t val;
965 	uint32_t val2;
966 	uint32_t reg;
967 
968 	hccr = ctrl->hccr;
969 	hcor = ctrl->hcor;
970 	/*
971 	 * Program the Number of Device Slots Enabled field in the CONFIG
972 	 * register with the max value of slots the HC can handle.
973 	 */
974 	val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
975 	val2 = xhci_readl(&hcor->or_config);
976 	val |= (val2 & ~HCS_SLOTS_MASK);
977 	xhci_writel(&hcor->or_config, val);
978 
979 	/* initializing xhci data structures */
980 	if (xhci_mem_init(ctrl, hccr, hcor) < 0)
981 		return -ENOMEM;
982 
983 	reg = xhci_readl(&hccr->cr_hcsparams1);
984 	descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
985 						HCS_MAX_PORTS_SHIFT);
986 	printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
987 
988 	/* Port Indicators */
989 	reg = xhci_readl(&hccr->cr_hccparams);
990 	if (HCS_INDICATOR(reg))
991 		put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
992 				| 0x80, &descriptor.hub.wHubCharacteristics);
993 
994 	/* Port Power Control */
995 	if (HCC_PPC(reg))
996 		put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
997 				| 0x01, &descriptor.hub.wHubCharacteristics);
998 
999 	if (xhci_start(hcor)) {
1000 		xhci_reset(hcor);
1001 		return -ENODEV;
1002 	}
1003 
1004 	/* Zero'ing IRQ control register and IRQ pending register */
1005 	xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1006 	xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1007 
1008 	reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1009 	printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1010 
1011 	return 0;
1012 }
1013 
1014 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
1015 {
1016 	u32 temp;
1017 
1018 	xhci_reset(ctrl->hcor);
1019 
1020 	debug("// Disabling event ring interrupts\n");
1021 	temp = xhci_readl(&ctrl->hcor->or_usbsts);
1022 	xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1023 	temp = xhci_readl(&ctrl->ir_set->irq_pending);
1024 	xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1025 
1026 	return 0;
1027 }
1028 
1029 #ifndef CONFIG_DM_USB
1030 int submit_control_msg(struct usb_device *udev, unsigned long pipe,
1031 		       void *buffer, int length, struct devrequest *setup)
1032 {
1033 	struct usb_device *hop = udev;
1034 
1035 	if (hop->parent)
1036 		while (hop->parent->parent)
1037 			hop = hop->parent;
1038 
1039 	return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1040 					hop->portnr);
1041 }
1042 
1043 int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1044 		    int length)
1045 {
1046 	return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1047 }
1048 
1049 int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1050 		   int length, int interval)
1051 {
1052 	return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
1053 }
1054 
1055 /**
1056  * Intialises the XHCI host controller
1057  * and allocates the necessary data structures
1058  *
1059  * @param index	index to the host controller data structure
1060  * @return pointer to the intialised controller
1061  */
1062 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1063 {
1064 	struct xhci_hccr *hccr;
1065 	struct xhci_hcor *hcor;
1066 	struct xhci_ctrl *ctrl;
1067 	int ret;
1068 
1069 	*controller = NULL;
1070 
1071 	if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
1072 		return -ENODEV;
1073 
1074 	if (xhci_reset(hcor) != 0)
1075 		return -ENODEV;
1076 
1077 	ctrl = &xhcic[index];
1078 
1079 	ctrl->hccr = hccr;
1080 	ctrl->hcor = hcor;
1081 
1082 	ret = xhci_lowlevel_init(ctrl);
1083 
1084 	if (ret) {
1085 		ctrl->hccr = NULL;
1086 		ctrl->hcor = NULL;
1087 	} else {
1088 		*controller = &xhcic[index];
1089 	}
1090 
1091 	return ret;
1092 }
1093 
1094 /**
1095  * Stops the XHCI host controller
1096  * and cleans up all the related data structures
1097  *
1098  * @param index	index to the host controller data structure
1099  * @return none
1100  */
1101 int usb_lowlevel_stop(int index)
1102 {
1103 	struct xhci_ctrl *ctrl = (xhcic + index);
1104 
1105 	if (ctrl->hcor) {
1106 		xhci_lowlevel_stop(ctrl);
1107 		xhci_hcd_stop(index);
1108 		xhci_cleanup(ctrl);
1109 	}
1110 
1111 	return 0;
1112 }
1113 #endif /* CONFIG_DM_USB */
1114 
1115 #ifdef CONFIG_DM_USB
1116 /*
1117 static struct usb_device *get_usb_device(struct udevice *dev)
1118 {
1119 	struct usb_device *udev;
1120 
1121 	if (device_get_uclass_id(dev) == UCLASS_USB)
1122 		udev = dev_get_uclass_priv(dev);
1123 	else
1124 		udev = dev_get_parent_priv(dev);
1125 
1126 	return udev;
1127 }
1128 */
1129 static bool is_root_hub(struct udevice *dev)
1130 {
1131 	if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB)
1132 		return true;
1133 
1134 	return false;
1135 }
1136 
1137 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1138 				   unsigned long pipe, void *buffer, int length,
1139 				   struct devrequest *setup)
1140 {
1141 	struct usb_device *uhop;
1142 	struct udevice *hub;
1143 	int root_portnr = 0;
1144 
1145 	debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1146 	      dev->name, udev, udev->dev->name, udev->portnr);
1147 	hub = udev->dev;
1148 	if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
1149 		/* Figure out our port number on the root hub */
1150 		if (is_root_hub(hub)) {
1151 			root_portnr = udev->portnr;
1152 		} else {
1153 			while (!is_root_hub(hub->parent))
1154 				hub = hub->parent;
1155 			uhop = dev_get_parent_priv(hub);
1156 			root_portnr = uhop->portnr;
1157 		}
1158 	}
1159 /*
1160 	struct usb_device *hop = udev;
1161 
1162 	if (hop->parent)
1163 		while (hop->parent->parent)
1164 			hop = hop->parent;
1165 */
1166 	return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1167 					root_portnr);
1168 }
1169 
1170 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1171 				unsigned long pipe, void *buffer, int length)
1172 {
1173 	debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1174 	return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1175 }
1176 
1177 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1178 			       unsigned long pipe, void *buffer, int length,
1179 			       int interval)
1180 {
1181 	debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1182 	return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
1183 }
1184 
1185 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
1186 {
1187 	debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1188 	return _xhci_alloc_device(udev);
1189 }
1190 
1191 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
1192 		  struct xhci_hcor *hcor)
1193 {
1194 	struct xhci_ctrl *ctrl = dev_get_priv(dev);
1195 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1196 	int ret;
1197 
1198 	debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
1199 	      ctrl, hccr, hcor);
1200 
1201 	ctrl->dev = dev;
1202 
1203 	/*
1204 	 * XHCI needs to issue a Address device command to setup
1205 	 * proper device context structures, before it can interact
1206 	 * with the device. So a get_descriptor will fail before any
1207 	 * of that is done for XHCI unlike EHCI.
1208 	 */
1209 	priv->desc_before_addr = false;
1210 
1211 	ret = xhci_reset(hcor);
1212 	if (ret)
1213 		goto err;
1214 
1215 	ctrl->hccr = hccr;
1216 	ctrl->hcor = hcor;
1217 	ret = xhci_lowlevel_init(ctrl);
1218 	if (ret)
1219 		goto err;
1220 
1221 	return 0;
1222 err:
1223 	free(ctrl);
1224 	debug("%s: failed, ret=%d\n", __func__, ret);
1225 	return ret;
1226 }
1227 
1228 int xhci_deregister(struct udevice *dev)
1229 {
1230 	struct xhci_ctrl *ctrl = dev_get_priv(dev);
1231 
1232 	xhci_lowlevel_stop(ctrl);
1233 	xhci_cleanup(ctrl);
1234 
1235 	return 0;
1236 }
1237 
1238 struct dm_usb_ops xhci_usb_ops = {
1239 	.control = xhci_submit_control_msg,
1240 	.bulk = xhci_submit_bulk_msg,
1241 	.interrupt = xhci_submit_int_msg,
1242 	.alloc_device = xhci_alloc_device,
1243 };
1244 
1245 #endif
1246